JP2000285033A - Method and device for detecting fault of memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory fault detection method capable of reducing the load of a processor by adopting suitable frequency and improving a response to a memory access by solving problems that load is increased due to the execution of memory check in each memory access and a response to a memory access is deteriorated in a conventional memory fault detection method. SOLUTION: In the memory fault detection method and device, a fault detection means 21 in a processor 2 writes check data in a memory 1, reads out the written data, stores the data in a check memory 24, which checks data. Thereby operation for detecting a fault in the memory 1 is executed asynchronously with a memory access by a data processing means 23 and a fault informing means 22 displays a fault message when the means 23 accesses the memory 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a memory failure, and more particularly to a method for detecting a memory failure capable of improving a response of a memory access in a processing device having a memory.

[0002]

2. Description of the Related Art Conventionally, ROM (Read Only Memory), R
If a failure of a memory such as an AM (Random Access Memory) cannot be detected by hardware, the data read from the memory is replaced by a software command.
Data check such as RC (Cyclic Redundancy Check) check and sum value check are performed to detect a failure in the memory.

A conventional memory check method using software will be described with reference to FIG. FIG. 3 is a flowchart showing a conventional memory failure detection method. When a processing device having a memory generates a request to access the memory (S31), a memory block including necessary data is read from the memory (S32). And 1
A memory check for blocks is performed (S33).

[0004] As a result of the memory check in step S33, it is determined whether or not there is a memory check error (S34). If there is no error (No), a process is performed on the accessed data (S35). If there is an error in the determination process S34 (in the case of Yes), a process of displaying an error message is performed (S36), and the process ends (S37).

[0005] Incidentally, regarding the conventional memory fault detection,
JP-A-7-1 published on June 23, 1995
No. 62439, entitled "Memory Failure Detection Method in ATM Cell Temporary Storage Device" (Applicant: NEC Corporation, Inventor: Tatsuo Nakagawa). In this technology, when an invalid and undefined cell flows into a device for temporarily storing ATM cells, a test is performed using an unused memory area, and a memory failure can be performed without preparing an extra memory. It is to detect. In particular, in the prior art of the above publication,
At the time of writing to the memory, a parity bit or CRC is added to the original data, and when the data is read from the memory, the parity bit or CRC of the data is recalculated, and the consistency with the added parity bit or CRC is verified. It states that a failure is detected.

[0006]

However, in the conventional memory failure detection method, since a memory check is performed every time the memory is accessed, the load on the processing device increases, and the response time to a user operation increases. However, there is a problem that the response time of the memory access is poor.

Further, since a memory check is performed every time the memory is accessed, there is no correlation between the failure occurrence rate and the number of checks, and failure detection is often performed more than necessary. There was a problem that was not.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a memory failure detection method capable of reducing the load on a processing device and improving the response of memory access at an appropriate frequency.

[0009]

SUMMARY OF THE INVENTION The present invention, which solves the above-mentioned problems of the prior art, provides a method and an apparatus for detecting a memory failure, in which a load on a processing device having a memory is reduced.
The memory access is to detect the memory failure by reading the test data written in the memory asynchronously, and it is possible to improve the response at the time of the memory access.

According to the present invention, in the method and apparatus for detecting a memory failure, when the load on the processing device having the memory is reduced, the memory failure is detected asynchronously with the memory access, but the notification of the memory failure is performed at the time of the memory access. Thereby, the response at the time of memory access can be improved, and a memory failure can be notified at the time of memory access.

[0011]

Embodiments of the present invention will be described with reference to the drawings. Note that the function realizing means described below may be any circuit or device as long as it realizes the function, and a part or all of the function may be realized by software. is there. Furthermore,
The function realizing means may be realized by a plurality of circuits, or the plurality of function realizing means may be realized by a single circuit.

[0012] Explaining the concept of the general concept, the memory failure detection method of the present invention detects a memory failure asynchronously with a memory access. In particular, the memory failure detection is performed when the load on the processing device is reduced. Thus, the response at the time of memory access can be improved.

A memory failure detection method according to an embodiment of the present invention (this method) is to write check data into a failure detection target memory, read the data, store the data in the check memory, and store the check data in the check memory. The operation for detecting a memory failure is performed asynchronously to the memory access for data processing by checking the data in the memory, and the operation for reporting the detected failure is performed asynchronously with the failure detection operation. By not performing the detection at the time of memory access, the response of memory access can be improved. Further, by performing the failure notification operation in synchronization with the memory access, the response of the memory access is improved, and an operation as if a failure was detected at the time of access is enabled.

A configuration for realizing the memory failure detection method according to the embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration block diagram for realizing a memory failure detection method according to an embodiment of the present invention. As shown in FIG. 1, an apparatus for realizing a memory failure detection method of the present invention (the present apparatus) detects a failure in the memory 1 while accessing the memory 1 and performing data processing while accessing the memory 1. The processing device 2 is basically composed of a processing device 2, and the processing device 2 performs a fault detection unit 21 for detecting a fault in the memory 1, a fault notification unit 22 for notifying the detected fault, and performs data processing on the memory 1. It comprises a data processing means 23 and a check memory 24 for storing a data block of a failure detection target read from the memory 1.

Next, a specific configuration of each section of the apparatus will be described. The memory 1 is a memory on which data processing such as reading or writing of data is performed, and is subjected to a memory check. The memory 1 may be a ROM, a RAM, or the like, and in particular, a DRAM (Dynamic RAM), a flash ROM, or the like.

The processing device 2 accesses the memory 1 and detects a failure in the memory 1. In the example of FIG. 1, the memory 1 is provided outside the processing device 2. However, the processing device 2 may include the memory 1. Although the check memory 24 is provided in the processing device 2, the check memory 24 may be provided outside. However,
In order to speed up the checking process, the built-in memory is more efficient.

The failure detecting means 21 in the processing device 2
The failure notifying unit 22 and the data processing unit 23 are basically realized by software, and a corresponding program is read from a program storage area inside the processing device 2 to execute processing in each unit.

The failure detecting means 21 writes several bytes of check data in the failure detection target area of the memory 1, reads out the written check data from the memory 1 and stores it in the check memory 24. Perform a memory check on the data in 24,
A failure on the memory 1 is detected. As a memory check method, a method such as a horizontal / vertical parity check, a CRC check, and a sum value check is used. The timing of failure detection will be described later.

The fault notifying means 22 is for notifying the fault detected by the fault detecting means 21.
Is connected to the display device, a failure message is displayed on the screen. Specifically, the fault detected by the fault detecting means 21 is set as flag information, and when the processing device 2 accesses the memory 1, the fault notifying means 22 is activated, and the memory is referenced by referring to the flag. Display a message as if a failure was detected during access. Further, the failure notification unit 22 not only displays the failure message, but also performs a process of stopping the CPU after displaying the failure message as a subsequent response, and also displays a necessary message on the error file after the failure message is displayed. It logs information and performs processing to resume processing.

The data processing means 23 performs access processing such as reading or writing of data to the memory 1. The functions of the data processing means 23 may include processing such as data processing and editing and calculation. In the conventional method, a memory check is performed for each access performed by the data processing unit 23. However, in the present invention, the access processing, the processing for detecting a memory failure, and the processing for reporting a memory failure are separately and independently performed. (Asynchronous) and different operation timings.

Check memory (check storage unit) 2
Reference numeral 4 denotes a memory in which a data block of check data written in the memory 1 is read from the memory 1 and the data block is written. The check memory 24 is a memory known to have no failure or a memory capable of detecting a failure in hardware.
Otherwise, if a failure occurs in the check memory 24, it becomes impossible to distinguish between a failure in the memory 1 and a failure in the check memory 24.

The operation of the present apparatus will be briefly described. When the failure detection means 21 of the processing device 2 is activated, the failure detection means 2
1 writes the check data in a corresponding area of the memory 1, reads a data block from the area, and stores it in the check memory 24. Further, the failure detecting means 21 performs a check such as a CRC check on the data stored in the check memory 24 and sets the check result in a flag.

When the fault notifying means 22 of the processing device 2 is activated, the fault notifying means 22 refers to the flag indicating the fault detection result, and displays a fault message on the screen of the display device if there is a fault. . Further, the failure notifying unit 22 performs the stop processing or the logging of the CPU after the display of the failure message, and executes the restart processing.

Next, the timing of detection by the failure detection means 21 and the timing of notification by the failure notification means 22 will be described. As for the detection timing, a failure detection timing is obtained based on the reliability of the memory, and the failure is detected in accordance therewith. Specifically, there are a case where a failure is detected at a fixed time and a case where a failure is detected when a specific condition is met.

A case where a failure is detected at a fixed time will be described. The detection time is determined from the operation time of the device and the detection timing. Since the check is performed at a fixed time, the check time is determined by a timer interrupt process, a constant activation process, or the like. For example, in a device operating from 8:00 to 17:00, the detection timing is set to 1
Assuming 10 times a day, every other hour (8:00, 9:00, ... 1,
At 7:00), a fault is detected. Further, for example, in a device operating for 24 hours, if the detection timing is set to 150 times a day, failure detection is performed every 10 minutes (144 times a day).

A case where a failure is detected under a specific condition will be described. For example, in a specific task process assigned by the scheduler, a check is performed once every 100 times the task is started, 256 bytes each. Also,
In a device that starts and stops every day, fault detection is performed once at the time of startup. In addition, failure detection is performed when a message indicating the end of communication is received. In addition, failure detection is performed during the end processing of the day.

Further, when the processing load is small, a failure can be detected when the processing load is small. For example, in a 24-hour information display device, all memories are checked once each time during the night when no information is transmitted.

Next, the processing of the memory failure detection method according to the embodiment of the present invention will be described with reference to FIG. FIG. 2 is a flowchart illustrating processing of the memory failure detection method according to the embodiment of the present invention. When the failure detecting means 21 is started and the memory failure detection (memory failure check) is started (S11), the failure check of the data corresponding to one memory block is performed on the check data written in the check memory 24. Perform (S12). And
As a result of the memory check, it is determined whether there is an error (S13).

If there is no error in the judgment processing S13 (No), the check processing is terminated (S1).
5). If there is an error (in the case of Yes), the flag corresponding to the check target block is turned ON (S1).
4). This flag is a flag indicating a failure detection in the memory (memory failure flag). When a failure check is performed on a plurality of memory blocks, a plurality of memory failure flags corresponding to the plurality of memory blocks are required, and the correspondence between the memory blocks and the flags can be understood.

Next, the processing of the memory fault notification method according to the embodiment of the present invention will be described with reference to FIG. FIG. 3 is a flowchart illustrating a process of the memory failure notification method according to the embodiment of the present invention. This notification method is an example in which a previously detected memory failure is reported as if it had been detected at the time of memory access.

In the present apparatus, when the data processing means 23 is activated and a request for access to the memory 1 is generated (S21), the memory failure flag used in the processing of FIG. Is determined (S22). If there is a memory failure in this determination processing S22 (in the case of Yes), an error message is displayed on the screen of the display device (S23), and the processing ends (S26).

If there is no memory failure in the judgment processing S22 (No), a memory block containing necessary data is read (S24), and processing for the accessed data is performed (S25), and the processing is terminated. Do (S
26).

According to the memory failure detection method according to the embodiment of the present invention, since the memory failure is detected asynchronously with respect to the memory access, the load on the processing device 2 is reduced, and the response time to the user operation is reduced. There is an effect that the influence can be reduced and memory access can be speeded up.

Further, according to the present method, a memory fault can be detected when there is room for the apparatus, taking into account the processing load and the like. Further, according to the present method, a memory failure can be detected at an appropriate number of times according to the frequency of occurrence of a memory failure. Also,
According to this method, even when the memory capacity is large, the memory failure is detected in units of small data blocks, so that the memory failure can be detected without affecting the performance of the processing device. In addition, in the present method, since the memory failure detection is performed by software, hardware functions are not required, and there is an effect that the entire apparatus can be made inexpensive.

[0035]

According to the present invention, a memory failure detection method and apparatus for detecting a memory failure asynchronously with the memory access when the load on the processing device is small, not at the time of the memory access. There is an effect that the response can be improved.

According to the present invention, the memory failure is detected asynchronously with the memory access when the load on the processing device is light, but the memory failure detection method and the device perform the memory failure notification at the time of the memory access. This has the effect of improving the response at the time of access and notifying a memory failure at the time of memory access.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an apparatus for implementing a memory failure detection method according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating processing of a memory failure detection method according to the embodiment of the present invention.

FIG. 3 is a flowchart illustrating a process of a memory failure notification method according to the embodiment of the present invention;

FIG. 4 is a flowchart illustrating a conventional memory failure detection method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory, 2 ... Processing device, 21 ... Fault detection means,
22: fault notification means, 23: data processing means, 2
4 ... Check memory

Claims (4)

[Claims] 1. A method for detecting a memory failure by reading test data written in a memory asynchronously with a memory access when a specific time or a specific condition is met so that a load on a processing device having a memory is reduced. Characteristic memory failure detection method. 2. When a specific time or a specific condition is met so that a load on a processing device having a memory is reduced, test data written to the memory is read asynchronously with memory access, and a memory failure is detected. A memory failure detection method, wherein when a failure is detected, a memory failure is reported at the time of memory access. 3. A memory for failure detection, a check storage unit for storing data read from the memory,
Failure detection for writing check data in the memory, storing the written data from the memory in the check storage unit, performing a memory check on the data in the check storage unit, and detecting a failure in the memory Means, the operation of the failure detection means operates asynchronously,
A failure notification unit that displays a failure message based on the result of the failure detection. 4. The apparatus according to claim 3, wherein the failure detection means operates at times other than the time of memory access, and the failure notification means operates at the time of memory access.