JP2000284984A - Debug system and information storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize real time trace on mass production chips with a small number of terminals, and to attain trace even when an absolute branch instruction is executed continuously or with short intervals. SOLUTION: This system 20 is a debug system for outputting status information indicating the execution state of a CPU 12 and the trace information of a target system to device an absolute branch destination address and output them. In this case, this system includes a trace information generating part 27 which generates trace information by specifying a part other than one part of the absolute branch destination addresses based on at least one of information related with an address area in which a program to be executed by the target system is present and the status information received from the target system at the time of receiving one part of the absolute branch destination addresses from the target system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a debugging system and an information storage medium used for the debugging system.

[0002]

2. Description of the Related Art In recent years, there has been an increasing demand for microcomputers that are incorporated in electronic devices such as game machines, car navigation systems, printers, and personal digital assistants, and that can implement advanced information processing. Such an embedded microcomputer is usually mounted on a user board called a target system. In order to support the development of software that operates this target system, ICE (In-Cir
A software development support tool called cuit emulator) is widely used.

[0003] Conventionally, such ICE has been
An ICE called a CPU replacement type as shown in FIG. 1 occupied the mainstream. In this CPU replacement type ICE,
At the time of debugging, the microcomputer 302 is detached from the target system 300, and a probe 306 of the debugging tool 304 is connected instead. Then, the debug tool 304 emulates the operation of the detached microcomputer 302. Also, the debug tool 304 performs various processes necessary for acquiring and debugging trace information.

However, this CPU replacement type IC
In E, when the internal operating frequency of the microcomputer 302 increases, real-time tracing becomes difficult due to a delay of a signal generated in the probe 306 or a buffer for storing trace information.

In order to solve such a problem, a system which enables real-time tracing on a mass-produced chip has been developed. At this time, if information such as an address bus is to be stored in the trace buffer in real time as trace information, several tens of dedicated terminals are required. Here, such terminals are necessary only at the time of debugging and are unnecessary for the end user.

Therefore, the present applicant outputs trace information for realizing a real-time trace to four dedicated terminals,
We are developing a system that enables real-time tracing from this trace information.

More specifically, CPU execution status information is output to three terminals every clock, and when an absolute branch is generated by an absolute branch instruction or the like, the PC value of the branch destination is serially output to one terminal in the next 27 clock cycles. Output. An absolute branch instruction is an instruction whose branch destination address is determined by the value of a register or the like during the execution of a program, and whose instruction cannot determine the branch destination. Therefore, when an absolute branch instruction is generated, it is not possible to know the branch destination from the instruction code of the program, so that it is possible to trace by outputting the PC value of the branch destination.

However, since the PC value is serially output to one terminal, if the absolute branch instruction is executed consecutively or at intervals of several instructions, the information of the PC value is interrupted on the way and trace cannot be performed. was there.

The present invention has been made in view of the above technical problems, and an object of the present invention is to realize a real-time trace on a mass-produced chip with a small number of terminals and to execute an absolute branch instruction continuously or An object of the present invention is to provide a debug system and an information storage medium that can be traced even when executed at short intervals.

[0010]

SUMMARY OF THE INVENTION The present invention is a debug system for outputting trace information of a target system which divides and outputs status information indicating an execution state of a CPU and an absolute branch destination address. Means for receiving the extracted absolute branch destination address and status information, and, when a part of the absolute branch destination address is received from the target system, information on an address area where a program to be executed by the target system exists and status received from the target system Trace information generating means for generating trace information by specifying a part other than a part of the absolute branch destination address based on at least one of the information.

Further, an information storage medium according to the present invention is characterized in that it contains information for realizing the above means.

The division and output of the address information of the absolute branch destination means, for example, a case where the address of the absolute branch destination is serially output one or several bits at a time.

The information related to the address area where the program exists is, for example, address assignment information of a map. If the address area where the program exists can be specified from the number of bits that can be taken as the address,
That information may be used. For example, if it is a 16-bit address, 6
Since an address area of 4 kbytes can be specified, the address area where the program exists can be set to 0 to 64 kbytes.

The information on the address area where the program exists may be stored in the debug system in advance, or may be received when generating trace information.

In the case where the absolute branch destination address is divided and output from the target system, if an absolute branch occurs at a short interval, a new absolute branch destination is output before all the previous absolute destination addresses have been output. In some cases, only part of the absolute branch destination address can be received.

According to the present invention, even in such a case, based on at least one of the information relating to the address area where the program to be executed by the target system exists and the status information received from the target system, other than a part of the absolute branch destination address The trace information can be generated by specifying the part.

The debug system of the present invention can generate trace information similar to that of a normal ICE or the like from a small amount of debug information such as status information and an absolute branch destination address. This also has the effect of contributing to cost reduction of the target system.

In the debugging system according to the present invention, the trace information generating means may extract a candidate address group having a part of the received absolute branch destination address information as lower bits,
An absolute branch destination address is specified from the candidate address group.

The information storage medium according to the present invention is characterized by including information for realizing the above means.

By extracting a candidate address group in which a part of the received address information of the absolute branch destination is set to the lower bits as in the present invention, the addresses of the potential absolute branch destinations can be narrowed down to the candidate address group. It is possible to specify the absolute branch destination more efficiently.

In the debugging system according to the present invention, the trace information generating means predicts from an array of status information received from the target system and a machine language instruction sequence of a program indicated by a given candidate address included in the candidate address group. The address information of the absolute branch destination is specified by comparing with an array of status information.

Further, an information storage medium according to the present invention is characterized by including information for realizing the above means.

Here, the information for grasping a machine language instruction sequence of a program executed by the target system may be a machine language instruction code sequence expressed in a binary or hexadecimal system, or may be a machine language instruction sequence. An instruction code string in which the code string is represented by a mnemonic code may be used. It is sufficient if at least the machine language instruction sequence executed by the CPU of the target system can be grasped. Note that information for grasping a machine language instruction sequence of a program executed by the target system may be held in the debug system in advance,
You may get it later.

If the address included in the candidate address group is an absolute branch destination address, the address is predicted from the array of status information received from the target system and the machine language instruction sequence of the program indicated by the address included in the candidate address group. Should match the status information array. Therefore, by comparing these, if they do not match, it can be determined that the address is not an address of an absolute branch destination.

In this way, according to the present invention, even when only a part of the address information of the absolute branch destination can be received, the address of the absolute branch destination can be specified more accurately to generate the trace information.

[0026] The debugging system of the present invention may include, as the status information, information for determining whether the execution state of the CPU of the target system belongs to execution of a normal instruction, execution of an absolute branch instruction, or execution of a relative branch instruction. It is characterized by.

[0027] The information storage medium according to the present invention is characterized by containing information for realizing the above means.

Here, the relative branch instruction is an instruction for branching to an address explicitly described in a program, and is an instruction capable of determining a branch destination from a source code.
An absolute branch instruction is an instruction whose branch destination address is determined by the value of a register during execution of a program, and cannot be determined from a source code. A normal instruction is an instruction executed in the order of instruction addresses. When the information indicating which of the three types belongs to and the address information of the absolute branch destination are obtained, it is possible to perform tracing by comparing the information with the information of the machine language instruction sequence of the execution program. Therefore, real-time tracing can be performed from information received from as few as three terminals.

According to the present invention, there is provided a debugging system for generating trace information of a target system which divides and outputs address information of an absolute branch destination, wherein the means receives a part of the address information of the absolute branch destination from the target system. Means for specifying a part other than a part of the absolute branch destination address information received based on the information on the address area where the program exists.

The information storage medium according to the present invention is characterized by including information for realizing the above means.

The division and output of the address information of the absolute branch destination means, for example, the case where the address of the absolute branch destination is serially output one or several bits at a time.

According to the present invention, even when an absolute branch occurs at short intervals and only a part of the absolute absolute destination address can be received, the address of the absolute branch destination is specified to generate trace information. Therefore, even when the absolute branch instruction can continuously obtain only a part of the information of the program counter, the trace information can be generated.

Further, since the debug system of the present invention can generate trace information similar to that of a normal ICE or the like from a small amount of debug information, it is possible to reduce the number of debug terminals of the target system and contribute to the cost reduction of the target system. It also has the effect of being able to.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

1. First, the configuration of the present embodiment will be described with reference to FIG.

As shown in FIG. 2, the microcomputer 10, which is a target system to be debugged,
CPU (central processing unit) 12, execution information output unit 1
4, including the internal memory 16.

Here, the execution information output section 16 outputs execution information for realizing a real-time trace to four dedicated terminals. Specifically, the CPU outputs command execution status information to three terminals (DST [2: 0]) every clock,
When the PC absolute branch execution occurs, the branch destination PC value (DPCO) is serially output to one terminal in the next 27 clock cycles.

The internal memory 16 stores programs executed by the target system.

The debugging system 20 of the present embodiment
Is composed of a debug tool 21 directly connected to a target microcomputer, and a host computer 23 connected to the debug tool.

The debug tool 21 executes the execution information acquisition unit 2
2, including a target memory writing unit 28, and the host computer 23 includes a program information storage unit 26, a trace information generation unit 27, and a program information writing unit 29.

The execution information acquisition section 22 has a 3-bit DST
[2: 0] and the DPCO representing the PC (program counter) value of the branch destination are stored in the internal trace memory 24. If a trace range is specified, DST [2: 0] and DPCO in that range are stored in the trace memory.

Since the branch destination PC is serially output one bit at a time from the lower bit, if a new absolute branch occurs before all bits are output, only a part of the address information of the absolute branch destination can be received. Will be.

The target memory writing unit 28 has a function of loading a program into the internal memory 16 of the target system and rewriting a program of the memory of the target system, and transmits the program via a TXD / RXD line (bidirectional communication line). Then, data to be written to the internal memory 14 of the microcomputer 10 is transmitted.

The program information storage section 26 stores a machine language code sequence of the same program as the program stored in the internal memory 16 of the target system.

When a part of the absolute branch destination address is received from the target system, the trace information generation unit 27 performs at least one of information on an address area where a program to be executed by the target system exists and status information received from the target system. Based on the above, a process for generating trace information by specifying a part other than a part of the absolute branch destination address is performed. Further, a candidate address group having a part of the received address information of the absolute branch destination as lower bits is extracted, and specified by an array of status information received from the target system and a given candidate address included in the candidate address group. A process for specifying the address information of the absolute branch destination by comparing the array of the status information predicted from the machine language code string is performed.

Further, a process for generating trace information before the occurrence of an absolute branch instruction is performed based on the execution start address of the target system of the debug system and the machine language code sequence of the program executed by the target CPU.

If the status information stored in the memory indicates that the trigger point matches, the trigger point address of the debug system and the machine language code sequence of the program executed by the target , A process of generating trace information before the occurrence of the absolute branch instruction is performed.

When the status information stored in the memory indicates the occurrence of an absolute branch, whether or not the occurrence of the absolute branch is caused by the occurrence of an interrupt is determined based on a machine language code sequence of the program to determine the trace information. Is performed.

When generating trace information, a machine language code sequence of a program stored in the program information storage unit 26 is used.

The program information writing section 29 loads the same program as the program loaded into the memory of the target system into the program information storage section 26 or reads out the program code stored in the memory of the target system to read the program. A process of writing to the information storage unit 26 or rewriting a program stored in the program information storage unit 26 to have the same content as the program of the target system is performed.

2. Contents of Status Information Output by Target System FIG. 3 is a diagram showing a relationship between an output value of DST [2: 0] (hereinafter referred to as DST information) and a CPU instruction execution state.
Here, the PC relative branch instruction is an instruction that branches to an address explicitly described in the program, and the branch destination can be determined from the instruction code. A PC absolute branch instruction is an instruction whose branch destination address is determined by the value of a register during execution of a program, and the branch destination cannot be determined from the instruction code.

Therefore, in the present embodiment, when a PC absolute branch instruction is generated, tracing is enabled by outputting the PC value (DPCO) of the branch destination.

That is, when the microprocessor is executing instructions in the order of addresses (DST information is 000 or 10).
If it is 0), it is possible to know how far the program counter has advanced, so that tracing is possible from the instruction code of the program. Also, when the microprocessor executes the PC relative branch instruction (when the DST information is 001 or 101), the branch destination can be known from the instruction code of the program, so that tracing is possible.

However, when the microprocessor executes the PC absolute branch instruction (when the DST information is 010 or 110), it is not possible to trace only with the DST information because the branch destination is not known from the instruction code of the program. Therefore, in such a case, tracing is enabled by outputting the PC value (DPCO) of the branch destination.

3. Process for specifying branch destination address Since the target system outputs the PC value serially to one terminal, when the absolute branch instruction is executed continuously or at intervals of several instructions, the PC value information is output in the middle. There was a problem that it was interrupted and tracing was not possible.

Therefore, in the present embodiment, even when only a part of the PC value can be obtained, the trace information of the absolute branch can be specified based on the map information described later and the DST information. The generation unit 27 performs a process for specifying a branch destination address as described below.

FIGS. 4A and 4B are diagrams for explaining the extraction of a group of candidate addresses for specifying the address of the absolute branch destination.

Numeral 310 in FIG. 4A indicates hexadecimal information of the PC value obtained from the DPCO signal.
The PC value is output 27 bits, one bit at a time, starting from the lower bit. If a new absolute branch occurs during this time, the PC value of the new absolute branch destination is output there. Is interrupted there.

Reference numeral 310 denotes information 1212 corresponding to the lower 12 bits, in which the PC value is interrupted.
16 is not obtained. In such a case, if the first four bits 316 (one digit since it is a hexadecimal code) are set to 0, the PC value which is a candidate for an absolute branch destination is 2 ¹⁶ = 6553.
The number is six (see 320 in FIG. 4A). Therefore, it is difficult to specify the actual PC value.

Therefore, in this embodiment, as shown in FIG. 4B, the map information 330 of the memory to which the CPU of the target system is connected is stored in the parameter file 340 of the debug system. Map information 330
Is information on an address where a program exists. For example, in the map information 330, the RAM1, the IROM, and the RAM2 are connected to the target CPU.
Address 0-7FF of M1, 80000-80F of IROM
This indicates that the program is stored at the address FF, address 90000-9FFFF of the RAM2.

The information of the lower 12 bits of the PC value is shown in FIG.
Assuming that the address is 802 as in (A), there is no candidate in the RAM1, the address 80802 is a candidate in the IROM, the 16 candidates 90802 to 9F802 are the candidates in the RAM2, and the total number of candidates is 17 ( FIG. 4 (B)
340).

FIGS. 5A to 5C are diagrams for explaining the process of specifying the address of the absolute branch destination from the candidate group extracted from the map information. FIG. 5A shows the DST information 350 stored in the trace memory 24 after the execution of the absolute branch instruction.

FIG. 5B shows an instruction code 360 after address 80802, which is one of the candidate groups specified by the map information, an instruction type 370 of the instruction code, and an output when the instruction code is executed. Represents the DST information 380 that will be generated.

FIG. 5C shows the case where the instruction code 390 at address 90802 or later, which is one of the candidate groups specified by the map information, the instruction type 400 of the instruction code and the instruction code are executed. Will be output to
The ST information 410 is shown. The output of the other candidate groups will be expected similarly to FIGS. 5B and 5C.
A T information sequence is generated, and the trace memory 24 shown in FIG.
Is compared with the DST information 350 of FIG. If they are the same, the candidate is specified as the branch destination address. Here, since the DST information sequence output by executing the instruction after the address 80802 in FIG. 5B matches the DST information 350 in the trace memory 34 in FIG.
Address 2 is specified as a branch destination address.

FIGS. 6, 7 and 8 are flowcharts showing an operation example of the processing for specifying the branch destination address when the absolute branch occurs at short intervals and the program counter value is not output from all bits from the DPCO.

First, the overall flow of the incomplete PC value analysis process will be described with reference to FIG.

At the start of the incomplete PC value analysis process,
First, the candidate PC value (ulWorkPc) and the number of candidates (ulExpectNum)
(Step S10).

Then, the loop A (steps S20 to S4)
In step 0), a candidate PC search process using map information is performed for the number of memories for which map information is defined in the parameter file (step S30). For example, in FIG. 4B, in the parameter file 340, RAM1, IR
Since the map information of the three memories OM and RAM2 is defined, the candidate PC value search processing is performed three times. In this candidate PC value search process, the candidate PC value (ulWorkP
c) The number of candidates (ulExpectNum) is updated.

When the loop A ends, it is determined whether or not the set number of candidates (ulExpectNum) is one. And the number of candidates (u
If lExpectNum) = 1, it is determined that one PC value has been specified, and the candidate PC value (ulWorkPc) updated in the candidate PC value specification processing is set as the address actually executed by the CPU, and the trace data generation processing is performed. (Step S5)
0, S60).

Next, a detailed processing example of the candidate PC search processing using the map information (step S30 in FIG. 6) will be described with reference to FIG.

The start address (ulMapTopAddr) obtained by shifting the top address of the memory defined by the map information to the right by the number of output bits of the DPCO signal is set.
Also, the end address of the memory defined by the map information, which is shifted to the right by the number of output bits of the DPCO signal, is set to the end address (ulMapBottomAddr).

For example, when the output of the DPCO signal is 12 bits as described with reference to FIGS.
(See 312 of (A)).
The start address (ulMapTopAddr) is set to 00990, which is 0000 shifted right by 12 bits. Also RA
The end address (ulMapBottomAdd) of 0009F obtained by shifting the last address 9FFFF of M2 to the right by 12 bits is added.
Set to r). Since the first address 90000 and the last address 9FFFF are represented by hexadecimal numbers, each digit represents a 4-bit DPCO signal.

Then, in loop B, the start address (ulMapTop
The following processing is repeated from Addr) to the end address (ulMapBottomAddr) (steps S120 to S170). For example, in the case of FIG. 4B, the repetition is performed from 00990 to 0009F 16 times.

First, the start address (ulMapTopAddr) is set to D
To the left shifted by the number of output bits of the PCO signal,
The sum of the output PC values obtained from the DPCO is set as the processing target PC value (ulPC) (step S13).
0).

Then, the PC value to be processed (ul
Work address (un
The processing target PC value (ulPC) is set in WorkAddr (step S140).

For example, in FIG. 4B, the first start address (ulMapTopAddr) is 00990. Therefore, if this is shifted to the left by 12 bits which is the number of output bits of the DPCO signal, it becomes 09000. This is DP
090802, which is obtained by adding the PC value 000802 in the output obtained from the CO, is set as the processing target PC value (ulPC).

Then, for the processing target PC value (ulPC), D
Perform PC value identification processing using ST information (step S
150).

Then, in preparation for the next loop, the start address (ulMapTopAddr) is updated (step S16).
0). In FIG. 4B, the start address (ulMapTopAddr) is updated to 00901.

Next, a detailed example of the PC value specifying process using the DST information (step S150 in FIG. 7) will be described with reference to FIG.

In the loop C, the following processing is repeated by the number of output bits of the DPCO signal (steps S210 to S25)
0). In the present embodiment, one bit of the DPCO is output every clock, so that approximately DCO is generated after an absolute branch instruction is generated.
This is because the subsequent instructions are executed by the number of output bits of the PCO signal, so that the DST information indicating the execution state of the subsequent instructions by the number of output bits of the DPCO signal is stored in the trace memory.

For example, in FIG. 4B, since the number of output bits of the DPCO signal is 12 bits, the processes from steps S220 to S240 are repeated 12 times.

First, the DST code to be compared (ucKindCode)
The DS that will be output when the instruction code on the program indicated by the work address (unWorkAddr) is executed
The T signal is substituted (step S220). For example, FIG.
In (B), since the work address 1 (362) points to the add instruction which is a non-branch instruction, the DST information '000' which will be output when the non-branch instruction is executed.
Is substituted for the DST code (ucKindCode) to be compared.

Then, the corresponding DST in the trace memory
If the signal and the comparison target DST code are compared (ucKindCode) and they do not match, it is determined that the processing target PC value is not the PC value of the absolute branch destination to be obtained, and the process exits the loop C (step S230).

If they match, the work address (unWork
Addr) at the next instruction code position (step S
240). α is an instruction size for shifting to the next instruction. For example, in FIG. 5B, when one instruction is 2 bytes, the work address 1 (362) to the work address 2
(364).

When the loop C is executed by the number of output bits of the DPCO signal, the DST signal when the instruction code after the candidate PC value is executed and the DST signal stored in the trace memory all match. Therefore, the processing target PC value (ulPC) is set to the candidate PC value (ulWorkPc), assuming that the processing target PC value (ulPC) is the address of the absolute branch destination to be obtained. The number of candidates (ulExpe
ctNum) is incremented (step S260).

[0086] 4. Processing for Realizing Trace Function without Stopping Target System In this embodiment, in order to generate trace information without stopping execution of the target system, machine language of a program stored in an internal memory of the target system is used. The instruction sequence (hereinafter referred to as program information) is stored in the program information storage unit 26 of the host computer.

By doing so, for example, the DST code (ucKindCode) to be compared with the DST signal on the trace memory can be created from the program information stored in the program information storage unit 26.
Therefore, it is not necessary to read the internal memory 16 of the target system when generating the trace information, so that the trace information can be generated without stopping the execution of the target system.

The internal memory 1 of the target system
6 does not need to be read, so that the processing time for generating trace information can be greatly reduced.

In the present embodiment, the program information writing unit 29 stores the program information stored in the internal memory 16 of the target system, which is used for tracing, in the program information storage unit 26 of the host computer. Such processing is performed.

FIG. 9 is a flowchart for explaining an operation example when a program is loaded into the internal memory of the target system.

In this embodiment, when a program is loaded into the internal memory of the target system, if there is a trace of the program, the program content loaded into the internal memory of the target system is written into the program information storage unit (step S310, S320, S
330).

FIG. 10 is a flowchart for explaining an operation example when rewriting a program in the target system.

In this embodiment, when a program in the internal memory of the target system is rewritten, if a trace of the program is scheduled, the corresponding portion of the program stored in the program information storage unit is made the same as the program of the target system. Rewrite to contents (Step S
410, S420, S430).

FIG. 11 is a flow chart for explaining an operation example in the case where the program is already loaded in the internal memory of the target system without loading the program.

When tracing the program, the start address and the end address of the memory storing the program are specified from the map information (steps S510 and S520). Then, the contents specified by the start address and the end address of the internal memory of the target system are read and written into the program information storage unit (step S530).

[0096] 5. FIG. 12 is a diagram for explaining a program counter analysis process before the generation of an absolute branch instruction. FIG. 12 shows that the instructions i1, i2,...
This shows how the status information DST1 to DST12 are stored in the trace memory. In the present embodiment, since the target system does not output the program counter value until the absolute branch instruction is executed, the program counter value is not output until the instruction i9 is executed. Therefore, the instructions i1 to i8 executed before the occurrence of the absolute branch
However, there was a problem that the execution position could not be specified and trace information could not be created.

Therefore, in the present embodiment, the following configuration is employed to specify the program counter at the time of executing the instruction corresponding to the head status information DST1 stored in the trace memory.

That is, when the range designation tracing is not performed, the execution start address is acquired by the debug system, for example, when the execution start position of the program is designated and executed. Then, in the no overwrite mode in which the trace memory is not overwritten, status information output from the target system is accumulated.

Here, when the range designation tracing is not performed, the target system outputs DST information as status information for all executed instructions. Therefore, the DS stored at the top of the trace memory
The T information DST1 can be specified as output by the instruction corresponding to the execution start address.

The target system according to the present embodiment can perform a range designation trace for outputting only status information corresponding to instructions from the start address to the end address by setting the start address and the end address as trigger addresses. . At this time, the trigger address set in the target system is acquired in advance by the debug system.

When performing such range designation tracing, the DST information DST stored at the head of the trace memory is used.
1 can be specified as the one output by the instruction corresponding to the trigger address specified as the start address.

FIG. 13 is a flowchart showing an example of the operation of analyzing the program counter at the time of outputting the oldest data stored in the trace memory.

When performing the range designation trace, the candidate P
The trigger address 1 which is the head address is set in C (ulPC) (steps S610 and S620).

When the range designation tracing is not performed and the trace memory is not overwritten, the candidate P
The program counter value immediately before the start of the trace is set in C (ulPC) (steps S630 and S640). Note that the address value of the instruction to be executed is set in the program counter value immediately before the start of the trace.

Then, trace information is generated using the candidate PC (ulPC) as the address value of the instruction corresponding to the oldest status information in the trace memory (step S65).
0).

6. FIG. 14 is a diagram for explaining a process of determining whether status information indicating execution of an absolute branch instruction is due to instruction execution or hardware interrupt.

As shown at 1410 in FIG. 14, when the status information stored in the trace memory indicates the execution of an absolute branch instruction, the status information is based on the execution of a normal absolute branch instruction and the hardware interrupt In some cases.

Therefore, in this embodiment, the status information is compared with the information of the machine language instruction sequence of the program stored in the program information storage unit to determine whether the status information is due to execution of a normal absolute branch instruction or a hardware interrupt. Is determined.

Assuming that the machine language instruction sequence of the instruction corresponding to the trace information stored in the trace memory is i1, i2,..., If the status information of 1410 is based on the execution of a normal absolute branch instruction, the corresponding machine Word instruction is 1
420, i3. If this i3 is not an absolute branch instruction, it is possible to determine that the status information in 1410 is not due to a normal execution of an absolute branch instruction but to a hardware interrupt.

FIG. 15 is a flowchart for explaining an operation example of a process for determining whether status information indicating execution of an absolute branch instruction is due to instruction execution or hardware interrupt.

The processing of loop A is performed by the number of DST information stored in the trace memory (step S710)
To S760).

If the DST information indicates the execution of the absolute branch instruction, first, the address indicated by the program counter at the time of outputting the DST information is analyzed (step S72).
0, S730). If the instruction code at the address indicated by the program counter of the analysis result is not an absolute branch instruction, it is determined as a hardware interrupt occurrence location and registered in the data (steps S740 and S750).

7. Configuration Example of Target System and Debug Tool FIG. 16 shows a detailed configuration example of the microcomputer and the debug system of the present embodiment. As shown in FIG. 16, the microcomputer 1020 includes a CPU 102
2. BCU (bus control unit) 1026, internal memory (mini monitor ROM 1042 and mini monitor RAM 10)
44, an internal ROM and an internal RAM other than 44), a clock generator 1030, a mini monitor 1040 (first monitor means), and an execution information output unit 1050.

Here, the CPU 1022 performs an execution process of various instructions, and includes an internal register 1024. The internal register 1024 is a general-purpose register R0
R15, special registers SP (stack pointer register), AHR (upper register of product-sum result data), ALR (lower register of product-sum result data), and the like.

The BCU 1026 controls the bus. For example, it is connected to a Harvard architecture bus 1031 connected to the CPU 1022, a bus 1032 connected to the internal memory 1028, an external bus 1033 connected to the external memory 1036, a mini monitor unit 1040, an execution information output unit 1050, and the like. Internal bus 103
4 is performed.

The clock generation unit 1030 generates various clocks used in the microcomputer 1020. The clock generation unit 1030 uses the BCL
A clock is also supplied to the external debug tool 1060 via K.

The mini-monitor unit 1040 has a mini-monitor RO
M1042, mini monitor RAM 1044, control register 1046, and SIO1048.

Here, in the mini monitor ROM 1042,
The mini monitor program is stored. In this embodiment,
This mini-monitor program is designed to process only simple and primitive commands such as GO, read, and write. For this reason, the mini monitor ROM 42
The memory capacity of the microcomputer 1020 can be reduced to, for example, about 256 bytes, and the microcomputer 1020 can be downsized while having an on-chip debugging function.

The contents of the internal register 1024 of the CPU 1022 are saved in the mini monitor RAM 1044 when shifting to the debug mode (when a break occurs in the user program). As a result, the execution of the user program can be properly restarted after the end of the debug mode. Also, the reading of the contents of the internal register can be realized by a primitive read command or the like of the mini monitor program.

The control register 1046 is a register for controlling various debugging processes, and has a step execution enable bit, a break enable bit, a break address bit, a trace enable bit, and the like. CPU 102 operated by a mini monitor program
2 writes data to each bit of the control register 1046 or reads data of each bit, whereby various debugging processes are realized.

The SIO 1048 is for transmitting and receiving data to and from a debug tool 1060 provided outside the microcomputer 1020. SIO1
048 and the debugging tool 1060, TXD / R
They are connected by XD (data transmission / reception line).

The execution information output unit 1050 is for realizing a real-time trace function, and is DST information (DST information) which is status information indicating the execution state of the CPU.
[2: 0]) and the PC (program counter) value (DPCO) at the branch destination when the PC absolute branch occurs is output as execution information to the outside via the dedicated four terminals.

Between the execution information output unit 1050 and the debug tool 1060, three DST [2: 0] for outputting status information of the instruction execution of the CPU 1022 and the PC (program counter) value of the absolute branch destination are serially transmitted. Are connected by four lines, one DPCO, which outputs one bit at a time.

The debug tool 1060 includes a main monitor unit 1062 and an execution information acquisition unit 1064, and includes a host system 106 realized by a personal computer or the like.
6 is connected.

The main monitor 106 performs processing for converting (decomposing) a debug command input from the host system 1066 into a primitive command. Then, when the main monitor unit 1062 transmits data instructing the execution of the primitive command to the mini monitor unit 1040, the mini monitor unit 1040 performs a process for executing the designated primitive command.

The execution information acquisition unit 1064 stores the 3-bit DST [2: 0] and the DPCO representing the PC (program counter) value of the branch destination in the internal trace memory 11.
04. If a trace range is specified, DST [2: 0] and DPCO in that range are stored in the trace memory.

Next, in this embodiment, a configuration for loading a program from the debug system to the internal memory of the microcomputer and rewriting information in the internal memory will be described.

As shown in FIG. 17, in the present embodiment, the microcomputer 1020 includes a CPU (central processing unit) 1022 and a mini monitor unit (first monitor means) 1040 which is a main part of the present embodiment. Further, a main monitor unit (second monitor unit) 1062 is provided outside the microcomputer 1020. Here, the main monitor unit 1062 is, for example, the host computer 1
066 is converted (disassembled) into a primitive command. Also,
The mini monitor unit 1040 transmits and receives data to and from the main monitor unit 1062. Then, the mini monitor unit 104
0 determines the primitive command to be executed based on the data received from the main monitor unit 1062, and performs processing for executing the primitive command.

Here, the debug commands to be converted by the main monitor unit 1062 include program load, GO, step execution, memory write, memory read, internal register write, internal register read, breakpoint setting, breakpoint Commands such as release can be considered. The main monitor unit 1062 is
These various and complex debug commands, for example G
O, Write (write to a given address on the memory map in the debug mode), Read (read from a given address on the memory map), etc., are converted into simple and primitive commands. By doing so, the instruction code size of the mini-monitor program that performs the processing of the mini-monitor unit 1040 can be significantly reduced.

As a result, a program can be loaded from the debug system into the internal memory of the microcomputer, and information in the internal memory can be rewritten. That is, when a program is loaded to the microcomputer as the target system or when a memory write is performed, these debug commands are issued from the host computer.

8. Conversion to Primitive Command FIGS. 18A, 18B, 18C, and 18D schematically show a process of converting various debug commands to primitive commands.

For example, as shown in FIG.
D ..., SUB ..., AND ..., OR ...,
XOR ..., LD. Assume that a debug command has been issued to load the 12-byte program W.) into address 80010h. In this case, the program load command is a write (80010h, ADD
..., SUB), light (80014h, AND ...)
..., OR ...), light (80018h, XOR ...)
・, LD. W ...) are converted into three primitive write commands. That is, the mini-monitor program executes the three primitive write commands, thereby realizing the program load command.

Assume that a debug command called a step execution command is issued as shown in FIG. Then, the step execution command is converted into a write command to the step execution enable bit of the control register 1046 in FIG. 16 and a GO command. That is,
The step execution command is realized by the mini-monitor program executing the primitive write command and GO command.

It is also assumed that a debug command called an internal register read command has been issued as shown in FIG. Then, this internal register read command is
This is converted into a read command from the mini monitor RAM 44 (a save destination of the contents of the internal register) on the memory map.
That is, when the mini-monitor program executes the primitive read command, the internal register read command is realized. The internal register write command, the memory read command, and the memory write command are realized in the same manner.

It is also assumed that a debug command called a breakpoint setting command for setting a trigger address as a breakpoint has been issued as shown in FIG. Then, this breakpoint setting command is
It is converted into a write command to the break enable bit and the break address bit of the control register 1046. That is, when the mini-monitor program executes the primitive write command, the breakpoint setting command is realized.

As described above, in this embodiment, complicated and various debug commands are converted into primitive and simple read, write, and GO commands. Since the mini-monitor program only needs to execute the primitive read, write, and GO commands, the instruction code size of the mini-monitor program becomes very small.
As a result, the memory capacity of the mini monitor ROM 1042 can be reduced, and the on-chip debugging function can be realized with a small hardware scale.

9. Configuration Example of Debug Tool FIG. 19 shows a configuration example of the debug tool 1060.

The CPU 1090 executes a program stored in the ROM 1108,
0 is to be controlled overall. Transmission / reception switching unit 109
Reference numeral 2 is for switching between transmission and reception of data. The clock control unit 1094 controls the S
It controls the clock supplied to the CLK terminal, the address up counter 1100, and the trace memory 1104. BCLK from the microcomputer 1020 (SIO 1048) is input to the clock control unit 1094. The clock control unit 1094 includes a frequency detection circuit 1095 and a frequency division circuit 1096. Frequency detection circuit 1
095 detects the frequency range to which the frequency of BCLK belongs, and outputs the result to the control register 1098. The dividing ratio in the dividing circuit 1096 is determined by the control register 1098.
Is controlled by That is, a main monitor program (main monitor ROM 110) executed by the CPU 1090
Reads the frequency range of BCLK from the control register 1098. Then, the main monitor program determines an optimum frequency division ratio according to the frequency range, and writes the frequency division ratio into the control register 1098. And
The frequency dividing circuit 1096 divides BCLK by this frequency dividing ratio to generate SMC2, and outputs it to the SCLK terminal of the CPU 1090.

Address up counter 1100 is for counting up the address of the trace memory. The selector 1102 selects one of the line 1122 (the address output from the address up counter 1100) and the line 1124 (the address from the address bus 1120), and outputs data to the address terminal of the trace memory 1104. The selector 1106 is connected to the line 1126 (DST [2: 0], DPCO which is the output of the execution information output unit 1050 in FIG. 16) and the line 1128
(Data bus 1118), and outputs data to the data terminal of the trace memory 1104 or retrieves data from the data terminal.

A ROM 1108 is a main monitor ROM 11
10 (corresponding to the main monitor 1062 in FIG. 16), and the main monitor ROM 1110 stores a main monitor program. This main monitor program performs processing for converting a debug command into a primitive command as described with reference to FIGS. 18A to 18D. The RAM 1112 is a work area of the CPU 1090.

An RS232C interface 1114,
The parallel interface 1116 serves as an interface with the host computer 1066 shown in FIG. 16, and a debug command from the host system 1066 receives a CPU 1090 via these interfaces.
Will be entered. The clock generation unit 1118
A clock for operating the CPU 1090 is generated.

Next, the real-time trace processing in this embodiment will be briefly described. In the present embodiment, FIG.
Indicating status information of the instruction execution of the CPU 1022
Bit DST [2: 0] and D representing the PC value of the branch destination
The PCO is stored in the trace memory 1104. Then, trace data is generated based on the data stored in the trace memory 1104 and the information of the machine language instruction sequence of the user program stored in the program information storage unit of the host computer 1066. By doing so, the microcomputer 1020 and the debug tool 1
The real-time tracing function can be realized while reducing the number of connection lines to 060.

In the user program execution mode,
The line 1122 is selected, and the output of the address up counter 1100 is input to the address terminal of the trace memory 1104 via the selector 1102. Also, the line 1126 is selected, and the DST is
[2: 0], the DPCO is input to the data terminal of the trace memory 1104. Here, address up counter 1
20. First, the CPU 1090 uses the data bus 1118 and the address bus 1120 as shown in FIG.
A start address is set as shown in FIG. A ST / SP (start / stop) terminal of the address up counter 1100 has a DST for specifying a trace range.
The line [2] is connected. Then, as shown in FIG. 20B, the first pulse 130 is applied to the line of DST [2].
Is input, the address up counter 1100 starts address up counting. And DST
When the second pulse 132 is input to the line [2],
The address up-count of the address up counter 1100 stops, and the trace operation stops. Thus, the data (DST [2:
0], DPCO) can be stored in the trace memory 1104.

On the other hand, when the mode shifts from the user program execution mode to the debug mode, the line 1124 is selected, and the address from the address bus 1120 is input to the address terminal of the trace memory 1104 via the selector 1102. The line 1128 is selected, and data from the trace memory 1104 is output to the data bus 1118 via the selector 1106. As a result, the data (DST) stored in the trace memory 1104
[2: 0], DPCO) in debug mode
1090 (main monitor program) can be read. Then, it is possible to generate trace data based on the read data and the information of the machine language instruction sequence of the user program.

Note that the present invention is not limited to this embodiment,
Various modifications can be made within the scope of the present invention.

For example, in the present embodiment, the case where the means for realizing the function of the debug system is provided separately in the debug tool and the host computer has been described, but the present invention is not limited to this. A means for implementing all functions may be provided in one of the debug tool and the host computer to implement the debug system.

In the present embodiment, the case where the PC value of the branch destination is serially output bit by bit from the target system has been described as an example, but the present invention is not limited to this. A terminal for outputting a branch destination PC for several bits may be prepared and serially output for several bits.

In the present embodiment, the case where the range designation trace is performed by using two trigger addresses has been described as an example, but the present invention is not limited to this. For example, one or three or more trigger points may be set, or a range may not be specified by a trigger point.

The configurations of the microcomputer and the debug tool are not limited to those described in the present embodiment, and various modifications can be made.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a CPU replacement type ICE.

FIG. 2 is a diagram for describing a configuration of the present embodiment.

FIG. 3 is a diagram illustrating a relationship between an output value of DST [2: 0] and an instruction execution state of a CPU.

FIGS. 4A and 4B are diagrams for explaining extraction of a candidate address group for specifying an address of an absolute branch destination;

FIGS. 5A to 5C are diagrams for explaining a process of specifying an address of an absolute branch destination from a candidate group extracted from map information;

FIG. 6 is a flowchart illustrating an operation example of a process of specifying a branch destination address when an absolute branch occurs at a short interval and a program counter value is not output in all bits from the DPCO.

FIG. 7 is a flowchart illustrating an operation example of a process of specifying a branch destination address when an absolute branch occurs at a short interval and a program counter value is not output in all bits from the DPCO.

FIG. 8 is a flowchart illustrating an operation example of a process of specifying a branch destination address when an absolute branch occurs at short intervals and a program counter value is not output in all bits from the DPCO.

FIG. 9 is a flowchart for explaining an operation example when a program is loaded into the internal memory of the target system.

FIG. 10 is a flowchart for explaining an operation example when rewriting a program code in a target system.

FIG. 11 is a flowchart for explaining an operation example in a case where a program is already loaded in an internal memory of a target system without being loaded;

FIG. 12 is a diagram for describing a program counter analysis process before the occurrence of an absolute branch instruction.

FIG. 13 is a flowchart illustrating an operation example of a process of analyzing a program counter at the time of outputting the oldest data stored in the trace memory.

FIG. 14 is a diagram illustrating a process of determining whether status information indicating the execution of an absolute branch instruction is due to instruction execution or a hardware interrupt.

FIG. 15 is a flowchart for explaining an operation example of a process of determining whether status information indicating absolute branch instruction execution is due to instruction execution or hardware interrupt.

FIG. 16 is a functional block diagram illustrating a configuration example of a microcomputer and a debugging system.

FIG. 17 is a diagram for explaining a debug command execution process according to the present embodiment;

FIGS. 18A to 18D are diagrams for explaining a process of converting (decomposing) a debug command into a primitive command.

FIG. 19 is a functional block diagram illustrating a detailed configuration example of a debug tool.

FIG. 20 is a diagram showing a relationship between DST [2] and a trace range.

[Explanation of symbols]

 Reference Signs List 10 microcomputer 12 CPU (central processing unit) 14 execution information output unit 16 internal memory 20 debug system 22 execution information acquisition unit 24 trace memory 26 program information storage unit 27 trace information generation unit 28 target memory writing unit 29 program information writing unit 1020 Microcomputer 1022 CPU 1024 Internal register 1026 BCU 1028 Internal memory 1030 Clock generation unit 1036 External memory 1040 Mini monitor unit 1042 Mini monitor ROM 1044 Mini monitor RAM 1046 Control register 1048 SIO 1050 Execution information output unit 1060 Debug tool 1062 Main monitor unit 1064 Execution information acquisition unit 1066 Host computer 1090 CPU 1092 Transmission / reception off Part 1094 clock control unit 1095 frequency detector 1096 frequency divider 1098 control register 1100 address up counter 1102 selector 1104 trace memory 1106 selector 1108 ROM 1110 external monitor ROM 1112 RAM 1114 RS232C interface 1116 parallel interface 1118 clock generator

Claims (10)

[Claims] 1. A debug system for outputting trace information of a target system which divides and outputs status information indicating an execution state of a CPU and an absolute branch destination address, wherein the absolute branch destination address and the status are divided from the target system. Means for receiving information, when receiving a part of the absolute branch destination address from the target system, based on at least one of information on an address area where a program to be executed by the target system exists and status information received from the target system, Trace information generating means for generating trace information by specifying a part other than a part of the absolute branch destination address. 2. The trace information generating means according to claim 1, wherein said trace information generating means extracts a candidate address group having a part of the received address information of the absolute branch destination as a lower bit, and extracts the absolute branch destination from the candidate address group. A debugging system characterized by specifying an address of a debugger. 3. The program according to claim 1, wherein said trace information generating means includes an array of status information received from a target system and a program specified by a given candidate address included in a candidate address group. A debugging system characterized in that address information of an absolute branch destination is specified by comparing with an array of status information predicted from a machine language instruction sequence. 4. The system according to claim 1, wherein the status information includes a CP of a target system.
A debug system comprising information for determining whether the execution state of U belongs to execution of a normal instruction, execution of an absolute branch instruction, or execution of a relative branch instruction. 5. A debug system for generating trace information of a target system that divides and outputs address information of an absolute branch destination, wherein the means receives a part of the address information of the absolute branch destination from the target system, and a program. Means for specifying a part other than a part of the address information of the absolute branch destination received based on the information on the address area where the data exists. 6. A computer-readable information storage medium for controlling a debug system which outputs status information indicating an execution state of a CPU and trace information of a target system which divides and outputs an absolute branch destination address. Means for receiving the absolute branch destination address and status information divided from the target system, and information and a target relating to an address area where a program to be executed by the target system exists when a part of the absolute branch destination address is received from the target system. Trace information generating means for generating trace information by specifying a part other than a part of the absolute branch destination address based on at least one of the status information received from the system; and Characteristic information storage medium. 7. The trace information generating means according to claim 6, wherein said trace information generating means extracts a candidate address group having a part of the received address information of the absolute branch destination as lower bits, and extracts the absolute branch destination from the candidate address group. An information storage medium containing information necessary for specifying an address of the information. 8. The program according to claim 6, wherein the trace information generating means includes an array of status information received from the target system and a program specified by a given candidate address included in a candidate address group. An information storage medium including information necessary for specifying address information of an absolute branch destination by comparing with an array of status information predicted from a machine language instruction sequence. 9. The target system according to claim 6, wherein the status information includes a CP of a target system.
An information storage medium comprising information necessary for determining whether the execution state of U belongs to execution of a normal instruction, execution of an absolute branch instruction, or execution of a relative branch instruction. 10. A computer-readable information storage medium for controlling a debug system for generating trace information of a target system that divides and outputs address information of an absolute branch destination, wherein the absolute branch from the target system is performed. Means for receiving a part of the previous address information, and means for specifying a part other than a part of the absolute branch destination address information received based on the information on the address area where the program exists, necessary information for realizing: An information storage medium comprising: