JP2000278652A - Information processing unit, its method and served medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transmit an image signal and a signal that differs from the image signal requiring synchronization with a clock signal. SOLUTION: A parallel serial converter 84 converts a drive signal for drivers 88a-88c into a serial signal and gives the signal to a signal changeover device 111. The signal changeover device 111 transmits a serial signal to a signal line not in use among signal lines for a horizontal synchronizing signal, a vertical synchronizing signal and an enable signal. A signal converter 112 converts a TTL signal into a LVDS signal and transmits it to a display section 3. A signal converter 122 of the display section 3 converts the LVDS signal into a TTL signal. A signal changeover device transmits only the serial signal with a flag added thereto to a serial parallel converter 87, which converts the serial signal into a parallel signal on the basis of the clock signal and the vertical synchronizing signal and outputs the resultant signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus and method, and a providing medium, and more particularly to an information processing apparatus and method for transmitting a signal different from image data when transmitting image data, and a providing medium.

[0002]

2. Description of the Related Art As a recent data transfer technology, LVDS (Low
Voltage Differential Signaling) is becoming popular. LVDS is a low-voltage differential signal transmission method, and is capable of high-speed, large-capacity (about 530 Mbps to 1365 Mbps) data transfer. Since the LVDS method is a low-voltage differential method, the influence of EMI (Electro-Magnetic Interference) can be reduced. Therefore, the LVDS method is particularly suitable for transferring image information to a display which is easily affected by EMI.

[0003]

By the way, the image information to be transferred contains a synchronization signal, and there are two transmission systems. One of the transmission systems is a system in which a horizontal synchronization signal and a vertical synchronization signal are multiplexed and transmitted with a 1-bit enable signal, and the other transmission system separates the horizontal synchronization signal and the vertical synchronization signal into two bits. This is a bit transmission method.

The transmission method of the synchronization signal is statically determined by the system. In the LVDS, one bit is secured for each of the horizontal synchronization signal, the vertical synchronization signal, and the enable signal. It is made to be able to correspond to the transmission system.

[0005] For this reason, for example, when image information is transferred from a main body of a personal computer to a display by the LVDS method and an image is displayed, a horizontal synchronizing signal and a vertical synchronizing signal are multiplexed and a 1-bit enable signal is used. When the method for transmitting the synchronization signal is used, two extra bits of the horizontal synchronization signal and the vertical synchronization signal that are not transmitted are generated, and the transmission of the synchronization signal for transmitting each of the horizontal synchronization signal and the vertical synchronization signal in two bits. When the method is used, there is a problem that one extra bit of the enable signal that is not transmitted is generated.

Further, for example, when there is a driving device driven by a personal computer near the display other than the display, a signal line and an interface dedicated to the driving device despite the extra bits as described above. There was a problem that must be provided.

[0007] The present invention has been made in view of such a situation, and by transmitting a signal different from the image data together with the image data when transferring the image data by the LVDS method, the present invention is effective. The data can be transferred quickly and in a space-saving manner.

[0008]

According to a first aspect of the present invention, there is provided an information processing apparatus for generating a signal different from a predetermined signal based on a clock signal used for the predetermined signal and a synchronization signal used for the predetermined signal. Generating means for generating, and a signal different from the predetermined signal generated by the generating means is superimposed on the predetermined signal line at a time different from the time at which the predetermined signal is predicted to occupy the predetermined signal line in advance. And a superimposing means for performing the operation.

According to a fourth aspect of the present invention, in the information processing method, a generating step of generating a signal different from the predetermined signal based on a clock signal used for the predetermined signal and a synchronization signal used for the predetermined signal, A superimposing step of superimposing a signal different from the predetermined signal generated in the generating step on the predetermined signal line at a time different from the time at which the predetermined signal occupies the predetermined signal line in advance. It is characterized by the following.

According to a fifth aspect of the present invention, the providing medium includes a generating step of generating a signal different from the predetermined signal based on a clock signal used for the predetermined signal and a synchronization signal used for the predetermined signal; And a superimposing step of superimposing a signal different from the predetermined signal generated in the generating step on the predetermined signal line at a time different from a time predicted in advance that the signal occupies the predetermined signal line. A program readable by a computer for executing the program.

[0011] The information processing apparatus according to claim 1, claim 4,
In the information processing method according to the first aspect and the providing medium according to the fifth aspect, a clock signal used for a predetermined signal;
Based on the synchronization signal used for the predetermined signal, a signal different from the predetermined signal is generated, and the predetermined signal occupies a predetermined signal line at a time different from the time predicted in advance to occupy the signal line.
A signal different from the predetermined signal generated by the generation unit is superimposed on the predetermined signal line.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the information processing apparatus according to the present invention will be described below with reference to the drawings.

FIGS. 1 to 6 show examples of the configuration of a portable personal computer to which the present invention is applied. The personal computer 1 is a mini-notebook type personal computer, and basically includes a main body 2 and a display unit 3 which can be opened and closed with respect to the main body 2. 1 is an external perspective view showing a state in which the display unit 3 is opened with respect to the main body 2, FIG. 2 is a plan view of FIG. 1, and FIG. 3 shows a state in which the display unit 3 is closed with respect to the main body 2. 4 is a right side view showing the display unit 3 opened 180 degrees with respect to the main body 2, FIG. 5 is a front view of FIG. 3, and FIG.
FIG. On the main body 2, a keyboard 4 operated when inputting various characters and symbols, and a track point (trademark) 5 operated when moving a mouse cursor are provided on the upper surface thereof. Also,
On the upper surface of the main body 2, there are further provided a speaker 8 for outputting sound and a shutter button 10 operated when capturing an image with the CCD video camera 23 provided on the display unit 3.

A claw 13 is provided at an upper end portion of the display unit 3. As shown in FIG. 3, when the display unit 3 is closed with respect to the main body 2, Is provided with a hole 6 into which the claw 13 is fitted. A slide lever 7 is provided on the front surface of the main body 2 so as to be movable in parallel with the front surface. The slide lever 7 engages with a claw 13 fitted in the hole 6 to lock and unlock. I can do it. By releasing the lock, the display unit 3 can be rotated with respect to the main body 2. Next to the claws 13, a microphone 24
Is attached. This microphone 24 is shown in FIG.
As shown in the figure, the sound from the back can also be picked up.

A programmable power key (PPK) 9 is also provided on the front of the main body 2. As shown in FIG. 4, an exhaust hole 11 is provided on the right side surface of the main body 2, and an intake hole 14 is provided at a lower part of the front surface of the main body 2 as shown in FIG. 5. In addition, a PCMCIA (Personal Computer Memory Card Interna
nation association) card (PC card) is provided.

An LCD for displaying an image is provided on the front of the display unit 3.
(Liquid Crystal Display) 21 is provided, and an imaging unit 22 is provided at the upper end thereof so as to be rotatable with respect to the display unit 3. That is, this imaging unit 22
It can rotate to any position within a range of 180 degrees between the same direction as D21 and the opposite direction (backward direction). A CCD video camera 23 is attached to the imaging unit 22.

A power lamp is provided on the lower body side of the display unit 3.
PL, battery lamp BL, message lamp ML, other LEDs
Is provided. Reference numeral 31 shown in FIG. 3 is a power switch provided on the left side of the main body 2, and reference numeral 25 shown in FIG. 5 is an adjustment ring for adjusting the focus of the CCD video camera 23. Further, reference numeral 26 shown in FIG. 6 is a lid for covering an opening for mounting an additional memory in the main body 2, and reference numeral 41 is a small hole for inserting a pin for releasing the lock nail of the lid 26.
FIG. 7 shows an internal configuration of the personal computer 1. Internal (PCI (Peripheral Componet Interconnec
t)) A CPU (Central Processing Unit) 5
2. PC card 53, RAM (Rando
m Access Memory) 54 and graphic chip 8
1 is connected. This internal bus 51 is connected to an external (ISA (I
hard disk drive (HDD) 56, I / O (input / output) controller 57, keyboard controller 58, track point controller 59, sound chip 60, LCD The controller 83, the modem 50 and the like are connected.

The CPU 52 is a controller that controls each function, and the PC card 53 is appropriately mounted when an optional function is added.

In the RAM 54, when the activation is completed, an e-mail program (application program) 54A, an autopilot program (application program) 54B, and an OS (basic program) 54C are transferred from the HDD 56 and stored. .

The electronic mail program 54A is a program for sending and receiving messages via a network from a communication line such as a telephone line. E-mail program 54
A has an incoming mail acquisition function as a specific function. This incoming mail acquisition function checks the mail server 93 to see if mail addressed to the user (user) has arrived in the mailbox 93A, and if there is mail addressed to the user, acquires the mail. Execute.

The autopilot program 54B includes a plurality of processes (or programs) set in advance.
This is a program that is started and processed sequentially in a preset order.

OS (basic program software) 54C
Controls the basic operation of a computer, such as Windows 95 or Windows 98 (trademark).

On the other hand, a hard disk drive (HDD) 56 on the external bus 55 side has an e-mail program 56
A, an autopilot program 56B and an OS (basic program software) 56C are stored. OS 56C in hard disk drive 56, auto pilot program 56B, and e-mail program 56A
Are sequentially transferred and stored in the RAM 54 during the startup (boot-up) process.

The I / O controller 57 has a microcontroller 61, and the microcontroller 61 is provided with an I / O interface 62. In this microcontroller 61, the I / O interface 6
2, the CPU 63, the RAM 64, and the ROM 69 are connected to each other. The RAM 64 includes a key input status register 65 and an LED (light emitting diode) control register 6.
6, a set time register 67 and a register 68 are provided. The set time register 67 is used to start the operation of the start-up sequence control unit 76 at a time (start-up condition) set by the user in advance. The register 68 stores a correspondence between a preset operation key combination (start condition) and an application program to be started. When the stored operation key combination is input by the user, the register 68 stores the correspondence. The activated application program (for example, e-mail) is activated.

The key input status register 65 stores an operation key flag when the programmable power key (PPK) 9 for one-touch operation is pressed. The LED control register 66 controls the lighting of a message lamp ML that indicates the start-up state of the application program (e-mail) stored in the register 68. The set time register 67 can arbitrarily set a predetermined time.

A backup battery 74 is connected to the microcontroller 61.
The values of the registers 65, 66, and 67 are retained even when the power of the main unit 2 is turned off.

The ROM 69 in the microcontroller 61 stores a wake-up program 70, a key input monitoring program 71, and an LED control program 72 in advance. The ROM 69 is, for example, an EEPROM (electricall
y erasable and programmable read only memory). This EEPROM is also called a flash memory. Further, an RTC (Real-Time Clock) 75 that constantly counts the current time is connected to the microcontroller 61.

The wake-up program 70 in the ROM 69 checks, based on the current time data supplied from the RTC 75, whether or not the time set in the set time register 67 has been reached. , A program for activating a predetermined process (or program). The key input monitoring program 71
This is a program for constantly monitoring whether or not K9 has been pressed by the user. The LED control program 72 is a program for controlling lighting of the message lamp ML.

The ROM 69 further has a BIOS (Basic Input / O
utput System) 73 is written. The BIOS is a basic input / output system, and is a software program that controls data transfer (input / output) between an OS or application software and peripheral devices (display, keyboard, hard disk drive, etc.).

A keyboard controller 58 connected to the external bus 55 controls an input from the keyboard 4. The track point controller 59 controls input of the track point 5.

The sound chip 60 includes the microphone 24
Or an audio signal is supplied to the built-in speaker 8.

The modem 50 can be connected to a communication network 92 such as the Internet, a mail server 93, and the like via a public telephone line 90 and an Internet service provider 91.

The graphic chip 81 connected to the internal bus 51 receives image data captured by the CCD video camera 23 after being processed by the processing unit 82 and then inputting the processed image data. The graphic chip 81 stores the video data input from the CCD video camera 23 via the processing unit 82 in the built-in VRAM 81A, reads out the data as appropriate, and outputs the read data to the LCD controller 83. LCD
The controller 83 controls the image data (TTL (Transistor-Transistor Logic)) supplied from the graphic chip 81.
Signal) to the LVDS driver 85.

The parallel / serial converter 84 converts a signal input in parallel as a signal for driving the driving devices 88 a to 88 c built in the display unit 3 into a serial signal, and outputs the serial signal to the LVDS driver 85. The LVDS driver 85, which has received the image data from the LCD controller 83 and the serial signal from the parallel / serial converter 84 as a TTL signal, converts the received TTL signal into an LVDS signal to be described later and outputs it to the display unit 3.

The LVDS signal transmitted from the LVDS driver 85 is again converted to a TTL signal by the LVDS receiver 86 of the display unit 3, and the converted image data is output to the LCD 21 and displayed. The serial signal output from the LVDS receiver 86 is converted into a parallel signal by the serial-to-parallel converter 87, and then output to the driving devices 88a to 88c, and the respective driving devices 88a to 88c are driven. .

The power switch 31 is operated when the power is turned on or off. The half-press switch 32 is turned on when the shutter button 10 is half-pressed, and the full-press switch 33 is turned on when the shutter button 10 is fully pressed. The inversion switch 34 is connected to the imaging unit 2
2 is rotated 180 degrees (CCD video camera 23
It is turned on when it is rotated in the direction of imaging the opposite side of the CD 21).

FIG. 8 shows a detailed configuration example of a part for transmitting image data from the LVDS driver 85 of the main unit 2 to the LVDS receiver 86 of the display unit 3. Graphic chip 81
Generates image data (TTL signal) and outputs it to the LCD controller 83. The image data includes a red signal, a green signal, a blue signal, a horizontal synchronization signal, a vertical synchronization signal, an enable signal, and a clock signal.

The LCD controller 83 transmits a red signal, a green signal, and a blue signal to the red signal transmitting section 10.
1, green signal transmitting section 102 and blue signal transmitting section 10
3 to 6-bit data TxIN0 to TxIN5, TxIN6
To TxIN11 and TxIN12 to TxIN17 are output and transmitted to the LVDS driver 85 in parallel (accordingly, as a total of 18 bits of data).

The LCD controller 83 transmits the horizontal synchronizing signal, the vertical synchronizing signal, the enable signal, and the clock signal to the horizontal synchronizing signal transmitting section 104, the vertical synchronizing signal transmitting section 105, the enable signal transmitting section 106, and the clock signal transmitting section, respectively. 1-bit data TxIN18,
Output as TxIN19 and TxIN20 and transmit to LVDS driver 85.

The LVDS driver 85 is connected to the signal switching device 11
1, a signal converter 112, a PLL (Phase Locked Loop) circuit 113, and differential signal transmission circuits 114 to 117.

The operation of the signal switching device 111 differs depending on the transmission method of the synchronization signal. The transmission method of the synchronization signal is such that the horizontal synchronization signal and the vertical synchronization signal are multiplexed and the enable signal 1
Either a method of transmitting a synchronization signal using only bits or a method of transmitting a synchronization signal using two bits for each of a horizontal synchronization signal and a vertical synchronization signal.

If the transmission method of the synchronizing signal is the former (only one bit of the enable signal), the signal switching device 111 sends the enable signal from the enable signal transmitting section 106 to the signal conversion device 112 as it is. The horizontal synchronizing signal transmitting unit 10 that transfers and does not transfer the signal
4 and signal lines from the vertical synchronizing signal transmitting section 105 (2 in total).
) Is supplied to the serial signal transmitted from the parallel-serial converter 84 with a flag indicating that it is a serial signal, and is sent to the signal converter 112.

If the transmission method of the synchronization signal is the latter (in the case of two bits of the horizontal synchronization signal and the vertical synchronization signal), the signal switching device 111 controls the horizontal synchronization signal transmission section 104 and the vertical synchronization signal. The signal from the transmitter 105 is transferred to the signal converter 112 as it is, and the serial signal transmitted from the parallel-serial converter 84 to the signal line (1 bit) from the enable signal transmitter 106 to which no signal is transferred. Is supplied with a flag indicating that it is a serial signal, and is sent to the signal converter 112.

The signal switching device 111 determines the transmission method of the synchronization signal based on the presence or absence of a signal input first after power-on from the horizontal synchronization signal transmission unit 104, the vertical synchronization signal transmission unit 105, and the enable signal transmission unit 106. After that, a process corresponding to the determined transmission method of any one of the synchronization signals is performed.

The signal conversion device 112 is provided with the red signal transmitting section 1
01, green signal transmitting unit 102, blue signal transmitting unit 103,
And a signal of a total of 21 bits transmitted in parallel from the signal switching device 111, converts the signal into three signals, and outputs the signals to the differential signal transmission circuits 114 to 116.

The PLL circuit 113 includes the clock signal transmitting unit 1
07, synchronizes the output phase of the internal oscillation circuit with the clock signal (TxCLKIN) sent from the microcomputer 07, and controls and adjusts the time difference generated between the internal clock and the internal clock to achieve high-speed clock access time and high-speed clock access. Operating frequency is realized. The clock signal generated by the PLL circuit 113 is supplied to the differential signal transmission circuit 117, and the differential signal transmission circuit 117 outputs the clock signal (R1
CLKIN + and R1CLKIN-) are output to the display unit 3.

The differential signal transmission circuits 114 to 117 convert received signals into differential signals and output the signals. This differential signal is two signals having the same absolute value and opposite polarities. For example, when the input value is 1 V, the differential signal transmitting circuits 114 to 117 generate two signals of a 1 V signal and a -1 V signal, and when receiving the signals, the differential signal receiving circuits 124 to 117 to be described later. 127 is the operation of taking the difference between the 1V signal and the -1V signal and dividing by 2 ((1-(-1)) / 2
= 1).

The transfer as described above enables transmission of a signal that is strong against noise. That is, for example, when the noise generated when a signal of 1 V is transmitted is αV, the receiving side determines (1 + α) V and (−1 + α) V
Will be received. At this time, the difference is taken as described above and divided by 2 (((1 + α) − (− 1 + α)).
/ 2 = 1), the noise is canceled out.
It is possible to transmit and receive signals that are strong against noise.

As described above, the LVDS driver 85 outputs a parallel signal of a total of 22 bits of TxIN0 to TxIN20 and TxCLKIN to the display unit 3 as four signals.

FIG. 9 shows an input signal (TTL signal) for a transmission signal (LVDS signal) when the signal converter 112 converts a received signal into three signals and outputs the signals from the differential signal transmission circuits 114 to 116. 2 shows an example of the arrangement. In the example of FIG. 9, the red signal transmitting unit 101 and the green signal transmitting unit 1
02 and a red signal output by the blue signal transmitting unit 103
TxIN0 to TxIN5, green signals TxIN6 to TxIN11, and blue signals TxIN12 to TxIN17 are serially arranged within one clock cycle.

Each of the horizontal synchronization signal and the vertical synchronization signal is 1
When sent using bits, TxIN18, TxIN19
Is used, and the last one bit TxIN20 becomes a surplus bit. The horizontal synchronization signal and the vertical synchronization signal are multiplexed and
When sent as a bit enable signal, TxIN20
Are used, and two bits of TxIN18 and TxIN19 are surplus bits. A signal for driving the driving devices 88a to 88c is transmitted using the surplus bits.

FIG. 10 shows an example in which the parallel / serial converter 84 converts an input parallel signal into a serial signal. In FIG. 10, signals for driving the driving devices 88a to 88c built in the display unit 3 are represented by signals a to c, respectively. The parallel-to-serial converter 84 converts the signals a to c input in parallel into serial signals in synchronization with the clock signal input from the clock signal transmission unit 107, and outputs the serial signals. At this time, a synchronization signal is inserted for each predetermined bit (four bits in the example of FIG. 10) for each type of signal so that the signals can be distinguished. In this example,
The horizontal synchronization signal of the image data transmitted from the horizontal synchronization signal transmission unit 104 is used as a synchronization signal.

The vertical synchronizing signal transmitting section 1 is used as a synchronizing signal.
Alternatively, a vertical synchronization signal transmitted from the signal generator 05 or an enable signal transmitted from the enable signal transmitter 106 may be used.

On the other hand, the serial-to-parallel converter 87 receives the serial signal transmitted from the parallel-to-serial converter 84, temporarily stores the serial signal in a built-in memory, and outputs the horizontal synchronizing signal output from the signal switching device 121 and the PLL circuit 123. The serial signals stored in the built-in memory are separated into parallel signals based on the clock signal output from the CPU, and the signals are output to the driving devices 88a to 88c.

Four signals (actually signals from eight signal lines) transmitted from the LVDS driver 85 are received by the differential signal receiving circuits 124 to 127. The received signal is subtracted from the paired signal by each differential signal receiving circuit as described above, is divided by 2, and is output to the signal conversion device 122 and the PLL circuit 123.

The signal converter 122 converts the three received signals (LVDS signals) into TTL signals. The converted output signal is a signal RxOU corresponding to the signals TxIN0 to TxIN20 input to the signal converter 112 of the LVDS driver 85.
Output as T0 to RxOUT20. The signals RxOUT0 to RxOUT5 output as red signals are output to the red signal receiving unit 131 of the LCD 21 by the signals RxOU output as green signals.
The signals T6 to RxOUT11 are output to the green signal receiving unit 132, and the signals RxOUT12 to RxOUT17 output as blue signals are output to the blue signal receiving unit 133, respectively. The signals RxOUT18 to RxOUT20 output as the horizontal synchronization signal, the vertical synchronization signal, the enable signal, and the serial signal are output to the signal switching device 121.

The signal switching device 121 receives the received signal RxOU
Only the serial signal with the serial signal flag is extracted from T18 to T20 and output to the serial / parallel converter 87. Other signals are regarded as a vertical synchronization signal, a horizontal synchronization signal, or an enable signal, and are output to the horizontal synchronization signal receiving unit 134, the vertical synchronization signal receiving unit 135, or the enable signal receiving unit 136, respectively.

The serial signal input to the serial-to-parallel converter 87 is converted into a parallel signal by the serial-to-parallel converter 87 based on the clock signal and the horizontal synchronizing signal received at the same time, and output to the driving devices 88a to 88c. Is done.

The signal input to the PLL circuit 123 is LVDS
The signal is demodulated into a clock signal RxCLKOUT corresponding to the clock signal TxCLKIN input to the PLL circuit 113 of the driver 85, and is output to the serial / parallel converter 87 and the clock signal receiving unit 137 described above.

The LCD 21 includes the red signal receiving section 131, the green signal receiving section 132, and the blue signal receiving section 13 as described above.
3, horizontal synchronization signal receiving section 134, vertical synchronization signal receiving section 1
35, image data is displayed based on the TTL signal received by each of the enable signal receiving unit 136 and the clock signal receiving unit 137.

Next, the operation when the CPU 52 (or the CPU 63) of the main body 2 transmits a signal for driving the driving devices 88a to 88c to the display unit 3 together with an image signal will be described with reference to the flowchart of FIG. I do.

In step S 11, the CPU 52 outputs the driving signals a to c of the driving devices 88 a to 88 c to the parallel / serial converter 84 in parallel via the external bus 55. The parallel / serial converter 84 receives a clock signal from the clock signal transmission unit 107 of the LCD controller 83, receives a horizontal synchronization signal as a synchronization signal from the horizontal synchronization signal transmission unit 104, and converts the signals a to c received from the CPU 52. , The parallel signal is converted into a serial signal as shown in FIG.

The parallel-serial converter 84 outputs the converted serial signal to the signal switching device 111 of the LVDS driver 85 in step S12.

The signal switching device 111 receives the serial signal in step S13, and in step S14,
The serial signal sent from the parallel / serial converter 84 is supplied to an unused signal line with a serial signal flag attached thereto, and transmitted to the signal converter 112. According to the above-described transmission method of the synchronization signal, the unused signal line is a 2-bit signal line of a horizontal synchronization signal and a vertical synchronization signal, or a 1-bit signal line of an enable signal.

In step S15, the signal conversion device 1
12 converts all the received TTL signals into LVDS signals,
The data is transmitted to the display unit 3 via the differential signal transmission devices 114 to 116, and the processing of the main body 2 ends.

Next, the operation of the display unit 3 will be described with reference to FIG. When the LVDS signal is received from the LVDS driver 85, the process starts, and in step S21,
The signal conversion device 122 converts all the received LVDS signals into TT
Convert to L signal and output. In step S22,
The signal switching device 121 receives the TTL signal output from the signal conversion device 122.

In step S23, the signal switching device 1
Reference numeral 21 extracts a serial signal having a serial signal flag from the received TTL signals. And the signal switching device 1
21 transfers only the extracted serial signal to the serial-to-parallel converter 87 in step S24. A signal having no serial signal flag is regarded as a horizontal synchronizing signal, a vertical synchronizing signal, or an enable signal, and is sent to the horizontal synchronizing signal receiving unit 134, the vertical synchronizing signal receiving unit 135, or the enable signal receiving unit 136, respectively. Is output.

In step S25, the serial / parallel converter 87 stores the transferred serial signal in a built-in memory. In step S26, the serial / parallel converter 87
Waits until a horizontal synchronization signal is received, and when it is determined that the horizontal synchronization signal has been received, the serial-parallel converter 87
In step S27, the serial signal stored in the internal memory is converted into a parallel signal based on the received horizontal synchronization signal, and the parallel signals are converted into driving signals 88a to 88c.
And the driving device is driven to complete the processing of the display unit 3.

In this example, as a signal different from the image information, a signal for driving three driving devices requiring a clock signal in addition to the LCD 21 is transmitted to the display unit 3, but four or more driving devices are required. May be transmitted.

As described above, since a signal different from the image data is transmitted together with the image data, no special cables or interfaces for signals of a plurality of driving devices different from the image data are required, and the display unit 3 is not required. High-speed transmission of a signal for driving a plurality of driving devices built in the device.

Note that a providing medium for providing a user with a computer program for performing the above-described processing includes:
In addition to recording media such as magnetic disks, CD-ROMs, and solid-state memories, communication media such as networks and satellites can be used.

[0072]

According to the information processing apparatus according to the first aspect, the information processing method according to the fourth aspect, and the providing medium according to the fifth aspect, the clock used for the predetermined signal together with the predetermined signal. Since a plurality of signals different from the predetermined signal are generated from the signal and the synchronization signal, excess bits can be used without waste, and high-speed operation can be performed without adding a cable or interface for a signal different from the predetermined signal. You will be able to send.

[Brief description of the drawings]

FIG. 1 is an external perspective view showing a state in which a display unit of a portable personal computer to which the present invention is applied is opened with respect to a main body.

FIG. 2 is a plan view showing a plane configuration of the portable personal computer of FIG. 1;

FIG. 3 is a left side view showing a state in which a display unit of the portable personal computer of FIG. 1 is closed with respect to a main body.

FIG. 4 is a right side view showing a state in which a display unit of the portable personal computer of FIG. 1 is opened 180 degrees with respect to a main body.

FIG. 5 is a front view showing a front configuration of the portable personal computer of FIG. 3;

FIG. 6 is a bottom view showing the configuration of the bottom surface of the portable personal computer of FIG. 4;

FIG. 7 is a block diagram showing an example of an internal electrical configuration of the portable personal computer of FIG. 1;

FIG. 8 is a diagram illustrating a detailed configuration of a portion that transmits image data from an LVDS driver of the main body to an LVDS receiver of a display unit.

FIG. 9 is a diagram illustrating an arrangement of a TTL signal in transmitting an LVDS signal.

FIG. 10 is a diagram illustrating conversion of a parallel signal into a serial signal by a parallel / serial converter.

FIG. 11 is a flowchart illustrating an operation when the main body transmits signals for driving three driving devices incorporated in the display unit together with image signals.

FIG. 12 is a flowchart illustrating an operation of the display unit 3 when receiving a signal for driving three driving devices built in the display unit together with an image signal.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Personal computer, 2 main body, 3 display part, 61 microcontroller, 81 graphic chip, 81A VRAM, 82 processing part, 83
LCD controller, 84 parallel-serial converter, 85
LVDS driver, 86 LVDS receiver, 87 serial-to-parallel converter, 88 a to c driver, 101 red signal transmission unit, 102 green signal transmission unit, 103
Blue signal transmitter, 104 Horizontal sync signal transmitter, 1
05 vertical synchronization signal transmission unit, 106 enable signal transmission unit, 107 clock signal transmission unit, 111 signal switching device, 112 signal conversion device, 113 PLL
Circuit, 114 to 117 differential signal transmission circuit, 121
Signal switching device, 122 Signal conversion device, 123
PLL circuit, 124 to 127 differential signal receiving circuit,
131 red signal receiving section, 132 green signal receiving section,
133 blue signal receiving section, 134 horizontal synchronizing signal receiving section, 135 vertical synchronizing signal receiving section, 136 enable signal receiving section, 137 clock signal receiving section

Claims (5)

[Claims] 1. An information processing apparatus for transmitting a predetermined signal of a plurality of bits at a predetermined time via a plurality of predetermined signal lines, wherein the clock signal used for the predetermined signal and the clock signal used for the predetermined signal are used. Generating means for generating a signal different from the predetermined signal based on the synchronization signal; and the generating means at a time different from the time at which the predetermined signal is predicted to occupy the predetermined signal line. An information processing apparatus, comprising: superimposing means for superimposing a signal different from the generated predetermined signal on the predetermined signal line. 2. The information processing apparatus according to claim 1, wherein the predetermined signal is a signal of image data. 3. The information processing apparatus according to claim 1, wherein said generating means converts a parallel signal into a serial signal. 4. An information processing method for an information processing apparatus for transmitting a predetermined signal of a plurality of bits at a predetermined time via a plurality of predetermined signal lines, comprising: a clock signal used for the predetermined signal; A generation step of generating a signal different from the predetermined signal based on a synchronization signal used for the signal; and the predetermined signal is different from a time predicted in advance to occupy the predetermined signal line, An overlapping step of overlapping a signal different from the predetermined signal generated in the generating step on the predetermined signal line. 5. A clock signal used for the predetermined signal and used for the predetermined signal to an information processing apparatus which transmits a predetermined signal of a plurality of bits at a predetermined time via a plurality of predetermined signal lines. A generation step of generating a signal different from the predetermined signal based on a synchronization signal; and the generation step, at a time different from a time that is predicted in advance that the predetermined signal occupies the predetermined signal line, A providing medium for providing a computer-readable program for executing a process including a step of superimposing a signal different from the generated predetermined signal on the predetermined signal line.