JP2000278332A - Multi-ppm encoding method and encoding circuit therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a transmission rate by composing a time-series signals of code patterns showing that one frame has no significant data or has signifi cant data in one slot or has significant data in two successive slots and making pieces of three-bit data, obtained by dividing data to be communicated, corre spond to the code patterns one to one. SOLUTION: The time-series signal is composed of the MPPM code patterns showing that one frame consisting of slots S1 to S4 has significant data in none of the slots, in one slot, and two successive slots. The pieces of 3-bit data (A0A1A2) corresponding to them are 001, 010, 100, 110, 000, 011, 101, and 111. Consequently, a text is transmitted and received by the multi-PPM encoding circuit, etc., composed of a decoder part and a shift register part between information processors by using the 3-bit data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for coding a serial time-series signal, and more particularly to a method for multi-PMM coding of optical communication used for wireless communication and a coding circuit thereof.

[0002]

FIG. 6 shows an information processing apparatus 5A according to the prior art.
An example of a system configuration for performing communication with the information processing device 5B will be described. In FIG. 6, the information processing devices 5A and 5B include an information processing unit 11, a communication control unit 12, a 4PPM encoding circuit 6 including decoder units 6A and 6B and shift register units 3A and 3B, and a transmitting unit 14. , Receiving means 15.

In such a configuration, the text 11a communicated by the information processing device 5A includes SOH (start of heading), header, STX (start of text), text 11a, ETX according to a transmission protocol predetermined by the communication control unit 12. (End of text), is converted into communication data 12A composed of BCC (Transmission Block Check) and the like. This communication data 12A is
On the output side of the communication control unit 12, the 2-bit data 12c is sent to the decoder unit 6A as one frame, and the decoder unit 6A
The bit data 12c is decoded and output to only one of the four slots (s1 to s4) shown in FIG. This output is latched by the shift register unit 3A, and the slots s1 to s4 are sequentially output from the shift register unit 3A to the transmission unit 14. For example, in the case of optical communication, the transmitting unit 14 converts an output from the shift register unit 3A into an optical pulse using a light emitting diode or a laser and outputs the optical pulse.

[0004] 2-bit data output from the transmitting means 14
A serial time-series signal 14c obtained by converting 12c into units of four slots per frame is received by the receiving means 15 of the information processing device 5B (not shown, other information processing devices 5C,...), And is converted into an electric signal 3d. The data is serial-parallel converted by the shift register unit 3B, and the parallel data in units of four slots is converted into data 12d in units of two bits by the decoder unit 6B.
The communication control unit 12 decodes the received communication data 12B, and when the station specified in the header of the communication data 12B is its own station, passes the received text 11b to the information processing unit 11 of the information processing device 5B.

[0005] FIG. 5 shows a 4PP that has recently become popular in optical communication.
This is an encoding method called M (4-Pulse-Position-Modulation), which converts the above-mentioned 2-bit data 12c into one frame for transmission and reception, divides one frame into four slots s1 to s4, and The pulse output from, for example, the transmitting means 14 is emitted in only one slot out of 〜s4. In FIG. 5, 2-bit data (00), (01), (10), and (11) divide one frame into four slots s1 to s4,
2, s3, s4, and a pulse is output only to this one slot.

FIG. 7 shows an example of a 4PPM encoding circuit according to the prior art. In FIG. 7, the 4PPM encoding circuit is
Two-bit data (A0, A1) is used for ON-O of four slots s1 to s4
It comprises a decoder section 6A for decoding into FF signals, and a shift register section 3A for converting the ON-OFF signals of the four slots s1 to s4 from parallel to serial and sequentially outputting the signals. The decoder section 6A includes NOT elements 61 and 62 and AND elements 65 to
66 and a NOR element 64, and decodes 2-bit data (00), (01), (10), and (11) input to the inputs (A0, A1), and outputs the output terminals s1, s2, respectively. , s3, s4, output 1 is output.

The shift register section 3A includes a NOT element 34,
A pair of AND elements 35, 36, NOR element 37, NOT element 38, and five RS-FFs (flip-flops, hereinafter abbreviated as RS-FFs)
And a shift register circuit composed of 40 to 44. The shift / load switching signal S / L (hereinafter abbreviated as signal S / L) provides a signal S / L = Low, and the above four slots s1 to
Parallel loading operation of s4 ON-OFF signal (parallel reading)
And the signal S / L = High, the clock CLK generates RS-FF 41
The data loaded in .about.44 are sequentially shifted to the lower numbered RS-FF and output from the RS-FF 40. The output of the shift register 3A is a 4PPM pulse. CLR is a reset signal, and clears the data loaded in RS-FF 40 to 44 when CLR is low.

FIG. 8 shows an example of a timing chart for explaining the operation of FIG. 7, in which the horizontal axis indicates the time axis, and the vertical axis indicates the signal S / L, clear signal CLR, clock CLK, and 2-bit data in order from the top.
FIG. 3 is an explanatory diagram illustrating A1, A0, output OUT, and correspondence between a frame and a slot. FIG. 8 will be described below with reference to FIG.

In FIG. 8, a signal S / L has four clocks CL.
It goes low every K, and in the example shown, goes low at the third clock, and the inputs (A0, A1 = 00) decoded by the decoder unit 6A are:
The output 1 is set to the slot s1, and the other slots s2 to s4 are set to the output 0. The data (1,0,0,0) of this slot s1 to s4 is A
(1,0,0,0) is written to the RS-FFs 41 to 44 via the ND element 36. This data is transmitted to the lower numbered RS by the clock CLK.
The output pulse is output from the output OUT of RS-FF40.

In the illustrated example, the inputs (A0, A1) are sequentially (00), (0
1), (10), (11), and (00), the output position of the output pulse OUT in units of 4 slots per frame is s1, s
It turns out that it has changed to 2, s3, s4, s1.

FIGS. 9 and 10 show Kazumi Sato, et.al.
ormance Analysis of Multi-PulsePPM with Imperfect
Slot Synchronization in Optical Direct-Detction Ch
annel ”IEICE TRANS.COMMUN., VOL.E77-B, NO.8 AUGUST 1
994. FIG. 3 and FIG. FIG. 9 shows a case where the timing of the received signal is shifted by ΔT with respect to the received clock. FIG. 9 (A) shows the data expressed by continuous pulses, and FIG. 9 (B) shows the separated pulses. Indicates when data is represented.

FIG. 10 shows the above continuous pulse (solid line).
And the separated pulse (dotted line) and the data error rate with respect to the timing offset when the data is expressed. According to this document, it is understood that expressing data by continuous pulses can reduce the error rate of data detection by about one digit compared to expressing data by separated pulses.

[0013]

As described above, in the 4PPM encoding method according to the prior art, for example, the light emission of the light emitting element in optical communication is only one slot out of four, the light emission time is short, and the low power property is excellent. However, in order to transmit and receive data at high speed, the data transmission / reception amount per frame is 2 bits, the time per frame length needs to be shortened, and the optical pulse width needs to be narrowed. Become. In order to achieve this, circuit components and opto devices capable of high-speed response are required, and there is a problem that power consumption is increased in order to deal with the problem of cost increase and high speed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to solve the above-mentioned problems and to change the encoding method without changing the response speed to circuit components or opto devices. Accordingly, an object of the present invention is to provide a multi-PPM encoding method and an encoding circuit for improving a data transmission rate.

[0015]

In order to achieve the above object, according to the present invention, multi-PPM encoding of a signal for performing data communication with a serial time-series signal in which one frame of transmission data is formed in units of four slots is provided. In the method, the time-series signals communicated include: no significant data in one frame; significant data in one slot in one frame;
If there are significant data in two consecutive slots in the frame,
And the data to be communicated is 3
The data is divided into bit-unit data, and the 3-bit data is sequentially converted to 3-frame data into one-frame time-series signal data by associating the 3-bit data with any one of the encoding patterns in a 1: 1 manner. It is assumed that the received one-frame time-series signal data is converted into 3-bit data and converted into communication data.

With this configuration, transmission and reception can be performed by converting 3-bit data into an encoding pattern of 4 slots per frame. As a result, transmission and reception of 2-bit data to 3-bit data can be performed with the same frame length, and the data transmission speed can be improved by 50%. In particular, by setting significant data in two consecutive slots in one frame, it is possible to reduce the error rate degradation due to the timing offset, and by including no significant data in one frame in the coding pattern, The average light emission time in optical communication can be reduced.

The multi-PPM encoding circuit includes a decoder for decoding 3-bit data into an ON-OFF signal of four slots, and a shift register for converting the ON-OFF signal of four slots from parallel to serial and sequentially outputting the signals. And transmission means for transmitting the output as a serial time-series signal.

Further, the multi-PPM encoding circuit includes a receiving means for receiving a serial time-series signal,
A shift register unit for serial-to-parallel conversion of an ON-OFF signal configured in slot units, and a decoder unit for converting the parallel data to data in 3-bit units can be provided.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory diagram for explaining a multi-pulse-position-modulation (PPM) encoding method according to one embodiment of the present invention, and FIG. 2 is a system for performing communication between information processing apparatuses. FIG. 3 is a configuration diagram, FIG. 3 is a diagram of a multi-PPM encoding circuit as one embodiment, and FIG. 4 is a timing chart for explaining an example of the operation of the multi-PPM encoding circuit.
8 are denoted by the same reference numerals.

In FIG. 1, the multi-PPM encoding method of a signal for performing data communication according to the present invention employs one of transmission data.
The frame is a serial time-series signal composed of four slots (s1 to s4).
No significant data in 4 slots (s1 to s4) of one frame (eg, data 0), significant data only in one slot of one frame (eg, data 1), and significant data in two consecutive slots of one frame It is composed of an encoding pattern of "yes".

In such a configuration, the communication control section (11) of the information processing apparatus (1A) on the transmitting side transmits the communication data (12A) sequentially to
The data is divided into bit data (A0, A1, A2) 12a and input to the multi-PPM encoding circuit, where the 3-bit data (A0, A1, A2) 12a
Corresponds to one of the above-mentioned coding patterns in a 1: 1 ratio, and converts the 3-bit data (A0, A1, A2) 12a into one-frame time-series signal data (3a) and transmits the data. The information processing device (1B) on the receiving side converts the received one-frame time-series signal data (3b) into 3-bit data (A0, A1, A2) 12b,
By converting to communication data (11b), the information processing device
Communication between (1A) and (1B) can be performed.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A description will be given with reference to FIGS. FIG. 2 shows an example of a system configuration for performing communication from the information processing apparatus 1A to the information processing apparatus 1B according to the present invention. In FIG. 2, the illustrated example shows an example in which one-way communication is performed from the information processing device 1A (transmission side) to the information processing device 1B (reception side). The information processing devices 1A and 1B include an information processing unit 11, a communication control unit 12, a multi-PPM encoding circuit 2 including decoder units 2A and 2B and shift register units 3A and 3B, a transmitting unit 14, a receiving unit It is composed of 15 and.

In this configuration, the text 11a with which the information processing device 1A communicates, according to a transmission protocol predetermined by the communication control unit 12, for example, when a binary synchronous communication protocol (BSC procedure) is used, SYN , SYN (synchronization),
It is converted into communication data 12A composed of SOH (start of heading), header, STX (start of text), text 11a, ETX (end of text), and BCC (transmission block check). The communication data 12A is divided at the output side of the communication control unit 12 into three-bit data 12a in units of one frame and sent to the decoder unit 2A. The decoder unit 2A divides the three-bit data 12a, for example, as shown in FIG. Decoding is performed in accordance with the illustrated example.

In FIG. 1, a time-series signal communicated according to one embodiment has four slots (s1 to s4) shown in the MPPM coding pattern on the right side corresponding to the 3-bit data 12a on the left side in FIG. No significant data in one frame (data 0 in all slots) / (3-bit data 001) and 1
There is significant data (data 1) in one slot in the frame
/ (3-bit data 010,100,110,000) and significant data (data 1) in two consecutive slots in one frame
Bit data 011, 101, 111) and an encoded pattern of the same.

In FIG. 2, outputs (s1 to s4) of four slots according to the MPPM coding pattern are latched in the shift register 3A, and the data 3a latched in the slots s1 to s4 sequentially from the shift register 3A is transmitted. Output to means 14. For example, in the case of optical communication, the transmitting unit 14 converts the output 3a from the shift register unit 3A into an optical pulse using a light emitting diode or a laser, and outputs the optical pulse to an optical fiber transmission unit or to a space propagation transmission unit. You. Further, when the communication means is wireless communication, in addition to the above-described space propagation transmission means of optical communication, for example, a radio wave is modulated (AM,
FM, PM) and output, or use an acoustic signal or the like.

3-bit data output from the transmitting means 14
The serial time-series signal 14a obtained by converting 12a into a unit of four slots per frame is received by the receiving means 15 of the information processing device 5B (including other information processing devices 5C,. The serial data is converted to serial data by the shift register unit 3B, and the parallel data in units of 4 slots is converted into data 12b in units of 3 bits by the decoder unit 2B, and the communication data 12B received by the communication control unit 12 is decoded. When the station specified in the header section of the communication data 12B is its own station, the text 11b in the received communication data 12B is passed to the information processing section 11 of the information processing device 5B. If the data transmission is performed normally and there is no transmission error, the text 11a transmitted by the information processing device 5A matches the text 11b transmitted by the information processing device 5B.

FIG. 3 shows a multi-PP according to an embodiment of the present invention.
An example of the M encoding circuit 2 is illustrated. In FIG. 3, the multi-PPM encoding circuit 2 converts 3-bit data (A0, A1, A2) into 4 bits.
The decoder unit 2A decodes the ON-OFF signals of the four slots s1 to s4 into ON-OFF signals, and the shift register unit 3A converts the ON-OFF signals of the four slots s1 to s4 from parallel to serial and sequentially outputs the signals. The decoder unit 2A includes NOT elements 21 and 2
2,23, AND elements 24-26,29,30,31 and OR elements 27,32
And a NOR element 28. With this configuration, the input (A0, A1, A1) for outputting data 1 to the output terminals s1 to s4
Input (A) as shown in parenthesized data
The 3-bit data (010) and (011) input to (0, A1, A2) are decoded, and data 1 is output to the output terminal s1 and the 3-bit data (1
00), (011), and (101) are decoded and data 1 is output to the output terminal s2.
And the 3-bit data (111), (110), and (101) are decoded and data 1 is output to the output terminal s3, and the 3-bit data (000), (111)
Decodes and outputs data 1 to the output terminal s4, and the 3-bit data (001) does not output data 1 to any of the output terminals s1 to s4.

The shift register section 3A includes a NOT element 34,
A pair of AND elements 35, 36, NOR element 37, NOT element 38, and five RS-FFs (flip-flops, hereinafter abbreviated as RS-FFs)
40 to 44, and a shift register circuit. With this configuration, the shift / load switching signal
S / L (hereinafter abbreviated as signal S / L) gives signal S / L =
When the signal is low, the parallel load operation of reading the ON-OFF signals of the four slots s1 to s4 in parallel, and when the signal S / L = high,
The data loaded to the RS-FFs 41 to 44 are sequentially shifted to the lower-numbered RS-FFs by the clock CLK and output from the RS-FF 40. The output of the shift register 3A is a multi-PPM pulse. CLR is a reset signal. When CLR is low, the data loaded in the RS-FFs 40 to 44 can be cleared.

FIG. 4 shows an example of a timing chart for explaining the operation of the multi-PPM encoding circuit 2 shown in FIG. 3, in which the horizontal axis is a time axis, and the vertical axis is a signal S / L and a clear signal in order from the top. FIG. 3 is an explanatory diagram for explaining the CLR, clock CLK, 3-bit data A2, A1, A0, output OUT, and correspondence between frames, slots s1 to s4, and output OUT. FIG. 4 will be described below with reference to FIG.

In FIG. 4, the signal S / L has four clocks CL.
It goes low every K, and in the example shown, goes low at the third clock, and the input (A2, A1, A0 = 010) decoded by the decoder unit 2A
Indicates that the output 1 is set to the slot s1 and the other slots s2 to s4 are set to the output 0. Data (1,0,0,0) of this slot s1 ~ s4
Is written to the RS-FFs 41 to 44 via the AND element 36. This data is shifted to the lower numbered RS-FF by the clock CLK, and an output pulse is output from the output OUT of the RS-FF40.

In the illustrated example, the inputs (A0, A1, A2) are sequentially (010),
The output positions of output 1 in units of 4 slots per frame when they change to (100), (110), (000) are s1, s2, s3, s4 in sequence.
And then the inputs (A0, A1, A2) are sequentially (011), (101), (11
1), the output position of output 1 in units of 4 slots per frame changes successively (s1, s2), (s2, s3), (s3, s4) for two consecutive slots, and the input (A0, When A1, A2) is (001), it can be seen that all output positions of four slots s1 to s4 in one frame are output 0.

In the present invention, 3-bit data is converted into one frame by the multi-PPM encoding method shown in FIG. 1 for transmission / reception. When two pulses are transmitted in the same frame, two consecutive pulses are always used. As a result, as described with reference to FIG. 10, the deterioration of the error rate due to the timing deviation (offset) between the reception clock and the reception signal can be reduced. Also, by including the mode of zero output in the transmission output pulse, the average output time (average light emission time in optical communication) can be reduced.

[0033]

[Table 1] Table 1 summarizes the performance comparison between the multi-PPM coding method and the 4PPM coding method. The multi-PPM coding method has 1.5 times the number of communication bits per frame as compared with the 4PPM coding method, and the average output time per bit is 5 times.
/ 6 can be shortened. Here, Ts is the time per slot. In addition, the simulation confirmed that the bit error rate of the multi-PPM encoding method of the present invention was equivalent to that of the 4PPM encoding method.

Although the embodiment of the multi-PPM encoding method according to the present invention has been described with reference to the correspondence between the 3-bit data and the encoding pattern shown in FIG. 1, it is not necessary to limit the correspondence to this. MPPM of the time series signal
The coding pattern is based on the coding pattern of 3-bit data having no significant data in one frame, significant data only in one slot in one frame, and significant data in two consecutive slots in one frame. The communication data is divided into 3-bit data, and the 3-bit data is determined in advance so as to correspond to any one of the above-mentioned coding patterns at a ratio of 1: 1. The effect can be obtained.

[0035]

As described above, according to the MPPM encoding method of the present invention, the number of communication bits per frame is 4P.
It is 1.5 times faster than the PM coding method, and the average light emission time per bit can be reduced to 5/6. Further, the bit error rate can be kept equivalent to the 4PPM coding method.

In the present invention, since the encoding method is changed,
The circuit and the opto-device may be the same as those of the prior art, and there is almost no increase in cost and power consumption, and the transmission speed can be improved by 50%.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating a multi-PPM encoding method according to an embodiment of the present invention;

FIG. 2 is a system configuration diagram for performing communication between information processing apparatuses.

FIG. 3 is a circuit diagram of a multi-PPM encoding circuit according to an embodiment;

FIG. 4 is a timing chart illustrating an example of the operation of a multi-PPM encoding circuit.

FIG. 5 is an explanatory diagram illustrating a multi-PPM encoding method according to the related art.

FIG. 6 is a system configuration diagram for performing communication between information processing apparatuses according to the related art.

FIG. 7 is a prior art 4PPM encoding circuit diagram;

FIG. 8 is a timing chart illustrating an example of an operation of a 4PPM encoding circuit.

9A and 9B are explanatory diagrams of a reception clock and a timing offset of a reception signal. FIG. 9A illustrates data when continuous pulses are used, and FIG. 9B illustrates data when separated pulses are used. Explanatory diagram when

FIG. 10 is a characteristic diagram of a data error rate with respect to a timing offset due to a continuous pulse and a separated pulse.

[Explanation of symbols]

 1A, 1B, 5A, 5B Information processing device 11 Information processing unit 12 Communication control unit 14 Transmission means 15 Receiving means 11a, 11b Text 12A, 12B Communication data 12a, 12b 3-bit data 12c, 12d 2-bit data 2 Multi-PPM encoding Circuit 21 ~ 23,34,38,39 NOT element 24 ~ 26,29,31,35,36 AND element 27,30,32 OR element 28,37 NOR element 40 ~ 44 RS-FF 2A, 2B, 6A, 6B Decoder section 3A, 3B Shift register section 3b, 3d Electric signal A0, A1, A2 Input terminal s1, s2, s3, s4 slot S / L shift / load switching signal CLK clock CLR clear input OUT, 3a, 3c output Ts slot time ΔT Timing offset time

Claims (3)

[Claims] 1. A multi-PPM encoding method for performing a data communication using a serial time-series signal in which one frame of transmission data is formed in units of four slots. None, one slot in one frame has significant data,
It consists of an encoding pattern that two consecutive slots in one frame have significant data, and the data to be communicated is divided into 3-bit data.
3. The multi-PPM encoding method, wherein the 3-bit data corresponds to any one of the encoding patterns in a 1: 1 ratio. 2. An encoding circuit using the multi-PPM encoding method according to claim 1, wherein: a decoder for decoding 3-bit data into 4-slot ON-OFF signals; and a 4-slot ON-OFF signal. Parallel-
A multi-PPM encoding circuit, comprising: a shift register unit that serially converts and sequentially outputs the output; and a transmission unit that transmits the output as a serial time-series signal. 3. An encoding circuit using the multi-PPM encoding method according to claim 1, wherein: a receiving means for receiving a serial time-series signal; and an ON-OFF signal composed of four slots per frame. A multi-PPM encoding circuit, comprising: a shift register unit that performs serial-parallel conversion; and a decoder unit that converts this parallel data into 3-bit data.