JP2000278180A - Cdma receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a code division multiple access CDMA receiver suitable for RAKE synthesis. SOLUTION: A reception timing detection means 1 detects reception timing for each path with respect to a spread signal denoting the same information via a plurality of efferent paths, and inverse spread means (C1-C3) detect a correlation value between the reception signal and the spread code for each path on the basis of the reception timing. Then storage means (M1-M3) store the correlation values of the same information detected for each path which are mode to correspond to each other, read timing generating means G1-G3 provides a prescribed delay to the reception timing of each path to generate read timing with the correlation value of the same information, path detection means D1-D3, 2 detect a path with fastest reception timing of the same information, a selection means 3 selects the read timing corresponding to the path and a synthesis means 4 synthesize correlation values read from the storage means 3 in the selected read timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CDMA receiver for receiving a spread-modulated signal, and more particularly, to receiving a radio signal of the same information arriving via a plurality of different paths, for each path. The present invention relates to a CDMA receiver suitable for synthesizing a correlation value (despread data) of the same information obtained from a signal and a spreading code.

[0002]

2. Description of the Related Art In mobile communications, for example, a signal wirelessly transmitted from a transmitter is reflected or diffracted by a building or the like and arrives at a receiver via a plurality of different paths (paths) (multipath). In this case, the receiver detects a plurality of reception peaks of the same signal with a delay spread. In such a case, if the receiver combines the same signal arriving via each path, it is possible to substantially increase the reception level of the signal, and such a combining method is known as RAKE. Have been.

In order to realize the RAKE combining as described above, it is necessary that the respective reception peaks of the same signal be separated from each other. For example, CDMA (Code Division Multiple Access) for performing multiple access by spread spectrum.
It is known that, in wireless communication using the “le Access” method, each reception peak can be separated in many cases. Taking advantage of such features of the CDMA system, for example, in W-CDMA that is being developed in recent years, it has been studied to improve the communication quality by performing RAKE combining as described above.

[0004] In the above, the case where the same signal wirelessly transmitted from one transmitter arrives at the receiver via a plurality of different paths has been described. For example, in a CDMA system, a plurality of transmitters (or a plurality of transmitters) are provided. It has been studied to increase the reception level by causing the receiver to perform RAKE combining while intentionally generating the multipath by spreading and modulating the same information from the antenna) and wirelessly transmitting the same information.

FIG. 3 shows, for example, DS-CDMA (Direct
An example of the configuration of a CDMA receiver that receives a signal spread-modulated by the Sequence-Code Division Multiple Access (direct spreading code division multiple access) method and performs the RAKE combining as described above is shown. It should be noted that FIG. 2 shows only the main part of the configuration for performing RAKE combining, and other components of the CDMA receiver are not shown. FIG. 1 shows an example in which a sliding correlator having a multi-finger configuration (a sliding correlator corresponding to a plurality of fingers), which is generally used in a CDMA receiver, is employed. As an example, a configuration in which the number of fingers is three is shown. An example is shown. Here, the number of fingers is RAKE
This is the maximum number of paths that can be combined. That is, in the configuration shown in FIG. 7, it is possible to RAKE combine correlation values (despread data) for up to three paths.

More specifically, FIG. 3 shows three sliding correlators S1 to S3 for performing despreading by detecting a correlation value between a received signal and a spreading code for each path, and a sliding correlator for each path. Three memories R1 to R3 for storing the correlation values obtained by the correlators S1 to S3, and a memory address generation circuit A for generating a memory address for simultaneously outputting the correlation values of the same information from these memories R1 to R3; , A RAKE combining unit 21 that combines the correlation values of the same information output from these memories R1 to R3.
Are shown.

In FIG. 3, each of the processing units S1 to S
3, each processing unit S1 for distinguishing which path the signal processed by R1 to R3, A is related to
~ S3, R1 ~ R3, A with "# 1", "# 2",
Symbols such as “# 3” are attached, which indicate that they are related to different routes. Also, in the same figure, for a dump signal and a correlation value (despread data) to be described later, “finger # 1” and “finger #
2 "and" Finger # 3 ".

An example of the operation performed by the CDMA receiver shown in FIG. 3 will be described. First, for example, when a signal spread and modulated by a CDMA transmitter and wirelessly transmitted arrives at a CDMA receiver via a plurality of different paths, the CDMA
The receiver receives a plurality of radio signals of the same information with a time difference. In this example, for convenience of explanation, the CDM
The number of radio signals of the same information received by the A receiver is 3
And

Next, in the CDMA receiver, for example, a processing circuit (not shown) detects the earliest received signal (hereinafter referred to as a preceding wave) among the above three radio signals of the same information for three paths. FIG. 3 for the path on which the preceding wave is received.
Is allocated to a specific sliding correlator S1 among the three sliding correlators S1 to S3, and the remaining sliding correlators S2 and S3 are arbitrarily allocated to the other two paths.

The reason for assigning a specific sliding correlator S1 to the path on which the preceding wave is received is to output a memory address generated by a memory address generating circuit A described later based on the despread timing of the preceding wave. This will be described in detail later. The above-described detection processing of the preceding wave and the allocation processing of the sliding correlator S1 are mainly performed using software.

Next, in the CDMA receiver, for example, each of the sliding correlators S1 to S
3 and outputs a dump signal and a spread code corresponding to the path respectively assigned to the memory address generation circuit A to the memory address generating circuit A. Here, the dump signal output for each path is a signal for controlling the timing for despreading the received signal for each path (for example, the timing for outputting a correlation value from the sliding correlators S1 to S3 to the memories R1 to R3). For example, it is generated based on the reception timing of the signal for each path.

Next, each of the sliding correlators S1 to S3 of the CDMA receiver detects a correlation value between the input received signal and the spread code at a timing according to the above-described dump signal, and detects the detected correlation value. The data is output to the memories R1 to R3 corresponding to the path and stored in the memories R1 to R3. Here, since the signals of the same information for each path received and processed by the CDMA receiver have a time difference from each other, the correlation values of the same information detected for each path are stored in the respective memories R1 to R3. Are stored in the memory R1 assigned to the path on which the preceding wave is received, and then the correlation values of the signals received via other paths are stored in the memory R1. The data is stored with a delay time in memories R2 and R3 assigned to the path.

Further, the memory address generation circuit A of the CDMA receiver inputs a dump signal corresponding to the path on which the preceding wave was received and a frame timing which is a reference of processing timing in the CDMA receiver, and receives the dump signal. At the read timing based on the above, a memory address for simultaneously reading out the correlation value of the same information for each path from the three memories R1 to R3 is output to each of the memories R1 to R3.

Here, the above-mentioned read timing will be described in detail. As described above, in the CDMA receiver, since the radio signal of the same information is received with a time difference for each path, the correlation value (despread data) of the same information obtained from the received signal for each path is stored in each memory R1 with the time difference. ~
R3, and the correlation value of these same information is stored in RAK.
In order to perform E synthesis, the correlation value is stored in all the memories R1 to R
3 must be simultaneously read out to the RAKE combiner 21.

For this reason, in the configuration shown in FIG. 3, the correlation values obtained for each path are temporarily stored in the memories R1 to R3, and the correlation values of the same information for each path are stored in all the paths. When a time that can be regarded as being stored in the corresponding memories R1 to R3 elapses, the three memories R1 to R3
3, the correlation value of the same information for each path is simultaneously read. Such a point in time (timing) is set as the above-mentioned readout timing, and this readout timing is set based on the processing timing (for example, despreading timing) of the preceding wave as described above.

Specifically, usually, all the memories R1 to R
In order for the correlation value of the same information for each path to be stored in 3, a time period required for signal processing of at least one spreading code has elapsed since the correlation value of the preceding wave was stored in the memory R <b> 1. Need. For this reason, as the read timing, for example, the correlation value of the preceding wave is stored in the memory R
The timing is set to a timing at which the signal processing time for one spreading code has elapsed from the time when the signal processing value is stored in 1.

When a memory address is output from the memory address generation circuit A to each of the memories R1 to R3 at such a read timing, the correlation value stored in the memory address in each of the memories R1 to R3, that is, each path is output. The correlation value of the same information for each is simultaneously output to the RAKE combining unit 21. Then, the RAKE combining unit 21 of the CDMA receiver combines the correlation values of the same information for each path input from the three memories R1 to R3, and the CDMA receiver combines the correlation values of the RAKE.
The synthesis result obtained by the synthesis unit 21 is demodulated by, for example, a demodulation unit (not shown).

[0018]

However, in the CDMA receiver as described above, among the radio signals of the same information arriving via a plurality of different paths, the signal received first (ie, Unless a specific sliding correlator (sliding correlator S1 in FIG. 3) is assigned to the path that has received the preceding wave while detecting the preceding wave, processing for despreading the received signal of each path is performed. Can't do this, but such an assignment process can take a lot of time,
There was a problem that the received data could be missed.

Specifically, for example, a CDMA receiver and a CD
When the communication environment with the MA transmitter fluctuates, each path through which the radio signal of the same information arrives at the CDMA receiver fluctuates. Therefore, the CDMA receiver detects the preceding wave according to the communication environment after the fluctuation. It is necessary to re-perform the processing and the allocation processing of the sliding correlator. In such a case,
In a CDMA receiver, it is necessary to reassign a dump signal or a spreading code corresponding to a path on which a fluctuating preceding wave is received to a specific sliding correlator. Since the despreading process of the signal is stopped, there is a case where received data that cannot be despreaded normally occurs.

The present invention has been made to solve such a conventional problem, and when receiving a radio signal of the same information arriving via a plurality of different paths, the above-described reception data is lost. Without causing
CDM suitable for synthesizing a correlation value (despread data) of the same information obtained from a received signal and a spread code for each path
It is intended to provide an A receiver.

[0021]

In order to achieve the above object, in a CDMA receiver according to the present invention, upon receiving a spread-modulated signal, a received signal and a spread code for each path are received as follows. Are combined with each other to obtain a correlation value (despread data) of the same information. That is, the reception timing detection means detects the reception timing of the signal for each path with respect to the radio signal of the same information arriving via a plurality of different paths, and determines the reception timing of each path based on the reception timing detected by the despreading means. The storage means detects the correlation value between the received signal and the spreading code, and the storage means stores the correlation value of the same information detected for each path in association with each other, and the readout timing generation means stores the correlation value of the same information for each path. The timing of reading the value from the storage means is generated by giving a predetermined delay to the reception timing of each path.

Further, the path detecting means detects the path having the earliest reception timing of the same information based on the reception timing of each path, and the selecting means detects the path from the read timings generated by the read timing generating means. The readout timing corresponding to the path detected by the means is selected, and the synthesizing means synthesizes the correlation value of the same information for each path read from the storage means at the selected readout timing.

Therefore, in the present invention, the read timing generation means generates the read timing based on the reception timing of each path, and the selection means selects the read timing corresponding to the path in which the reception timing of the same information is the earliest. Therefore, for example, even before the path detecting means detects the path in which the reception timing of the same information is the earliest (that is, the path receiving the preceding wave), the despreading means described above Despreading processing and storage processing by storage means can be performed.

For this reason, in the present invention, for example, as described in the above-mentioned conventional example, the despreading processing and the like cannot be performed unless the detection processing of the preceding wave or the predetermined allocation processing is performed. In addition, it is possible to smoothly perform the despreading process and the like of the received signal, and thereby it is possible to synthesize the correlation value of the same information for each path without dropping the received data.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment according to the present invention will be described with reference to the drawings. FIG. 1 shows an example of the configuration of a CDMA receiver according to the present invention. In this CDMA receiver, signals of the same information, which are spread-modulated by a CDMA transmitter and wirelessly transmitted, pass through a plurality of different paths. Suppose it comes through. The main part of the CDMA receiver according to the present invention performs a despreading process on signals received via a plurality of different paths, for example, to obtain a correlation value (despreading value) of the same information obtained from a received signal and a spreading code for each path. Since the configuration is related to the process of synthesizing data), FIG. 1 shows only a configuration example of a portion related to the configuration, and in this example, illustration and description of other components of the CDMA receiver are omitted. I do.

As shown in FIG. 1, the CDM of the present embodiment
The A receiver includes a reception timing detection unit 1 for detecting a reception timing of a signal for each path, and three sliding correlators C1 to C3 for despreading the reception signal for each path.
And three memories M1 to M3 for storing correlation values for each path obtained by despreading, and correlation values of the same information for each path from the three memories M1 to M3 based on the despread timing for each path. Memory address generation circuits G1 to G3 for generating read timings for reading data simultaneously.
And three delay sample counter circuits D1 to D3 for detecting a delay time from a reference timing of a despread timing for each path (a frame timing described later in this example).
And a comparator 2 that compares the delay time detected for each path
And a memory address generation circuit G based on the comparison result.
The selector 3 includes a selector 3 for selecting a read timing generated by the memory cells 1 to G3, and a RAKE combining unit 4 for combining correlation values of the same information for each path simultaneously output from the three memories M1 to M3.

Here, in the CDMA receiver of the present embodiment, as an example, the correlation values (despread data) for a maximum of three paths are stored in RA.
A configuration capable of performing KE combining (that is, a configuration in the case where the number of fingers in the conventional example is 3) is shown, and the above-described sliding correlators C1 to C3 and memories M1 to M3 corresponding to these three paths are shown. M3, three memory address generation circuits G1 to G3, and three delay sample counter circuits D1 to D3 are provided.

In FIG. 1, for example, similarly to FIG. 3, each of the processing units C1 to C3, M1 to M3, G1 to G3,
Each processing unit C1 to C3, in order to distinguish which path the signal processed by D1 to D3 belongs to,
"#" Is added to the names of M1 to M3, G1 to G3, and D1 to D3.
1 ","# 2 ","# 3 ", etc.
This indicates that the routes relate to different routes. Also, in the same figure, regarding the dump signal and correlation value (despread data) described later, “finger #
1 "," finger # 2 ", and" finger # 3 ".

The reception timing detecting section 1 receives a signal (spread signal) received through a plurality of different paths, detects the reception timing of the signal for each path based on the received signal, and based on the reception timing. The dump correlators C1 corresponding to the respective paths
To C3, memory address generation circuits G1 to G3, and delay sample counter circuits D1 to D3.

Here, as a method of detecting the reception timing of the signal for each path, as an example, a plurality of correlation values between the input received signal and the spread code of each path are calculated while shifting the multiplication timing, and calculated. When the correlation value reaches the maximum peak, it is assumed that the multiplication timing of the spread code multiplied by the spread code in the received signal is the same as the multiplication timing, so that the signal reception timing of each path can be detected.

The dump signal for each path is a signal for controlling the timing of despreading the received signal for each path, and the timing of such despreading processing is based on the signal reception timing for each path. Is determined. Specifically, in the sliding correlators C1 to C3 described later, the integrated value of the received signal and the spread code is integrated by a capacitor over one spread code (one symbol), so that the integrated value of the one spread code (one symbol) is obtained. That is, the correlation value between the received signal and the spread code is detected, and the dump signal of the present example notifies the timing at which the capacitor outputs the correlation value for each spread code. That is, the dump signal for each path in the present example controls the timing of outputting the correlation value for each spreading code from the sliding correlators C1 to C3 for each path to the memories M1 to M3 for each path.

In the present embodiment, the above-mentioned reception timing detecting section 1 detects the reception timing of the signal for each path so that the radio signal of the same information arriving via a plurality of different paths can be detected for each path. Reception timing detection means for detecting the reception timing of the signal is configured.

Each of the sliding correlators C1 to C3 is provided corresponding to each path, receives a received signal, a spread code, and a dump signal, and calculates a correlation value (despread data) between the received signal and the spread code. Is output to each of the memories M1 to M3 every one spreading code according to the dump signal. Here, each sliding correlator C
The timing of the spread code input to 1 to C3 is controlled based on, for example, the signal reception timing of each path.

In this embodiment, the above-described sliding correlators C1 to C3 detect the correlation value between the received signal for each path and the spread code in accordance with the dump signal, so that the received signal for each path is detected based on the detected reception timing. Despreading means for detecting a correlation value between the code and the spreading code is configured. In this example, the despreading is performed based on the dump signal. However, since the dump signal for each path is generated based on the reception timing of the signal for each path as described above,
Practically, despreading is performed based on the reception timing.

Each of the memories M1 to M3 is provided corresponding to each path, and each of the sliding correlators C
Correlation values of the same information for each path input from 1 to C3 are temporarily stored in association with each other, and the same information for each path stored according to a memory address input via a selector 3 described later. The correlation value is simultaneously output to the RAKE combiner 4
It has the function of outputting to

In the present embodiment, the memories M1 to M3 store the correlation values of the same information for each path in association with each other so that the correlation values of the same information detected for each path are associated with each other. A storage means for storing is configured.
In this example, separate memories M1 to M3 are provided for each path. However, for example, a configuration in which a storage area of one memory is divided into a plurality of areas and each area is assigned to each path may be adopted.

Each of the memory address generation circuits G1 to G3 is provided corresponding to each path, and
A frame timing, which is a reference of processing timing in the receiver, and a dump signal for each path are input, and the three memories M1 to M3 are read at timings based on the dump signal and the like.
Has the function of outputting to the selector 3 a memory address for reading out the correlation value of the same information for each path.

Here, each of the memory address generation circuits G1 to G1
In G3, the readout timing required when it is assumed that the wireless signal of the same information is received first through the corresponding path (that is, the preceding wave of the information is received through the corresponding path) (in this example, the readout timing is described above). (Timing for outputting the memory address). That is, in this example,
Since the memory address generation circuits G1 to G3 correspond to the read timing when the reception signal of each path is assumed to be the preceding wave, the reception signal of any path is the preceding wave as described later. Even in such a case, an appropriate readout timing can be realized in accordance with the path on which the preceding wave has been received.

As the read timing generated assuming that the received signal of a certain path is a preceding wave, for example, as shown in the above-mentioned conventional example, a correlation value obtained from the received signal of the certain path is stored in a memory. (In this example, any of the memories M1 to M3) (one of the memories M1 to M3 in this example) (one correlation code is output from the sliding correlators C1 to C3 to the memories M1 to M3 in accordance with the dump signal) and one spread code. The timing is set to the timing at which the signal processing time has elapsed. That is, in the present example, if a time required for signal processing for one spreading code elapses from the time when the correlation value of the preceding wave is stored in the memory, all correlation values of the same information as the preceding wave (this example) Three correlation values) are stored in the memories M1 to M3.
Is assumed to be stored in

As described above, the frame timing serves as a reference for the timing of processing performed by the CDMA receiver, and various frame timings may be used. Frame timing (CDM) of a signal received via
A timing synchronized with a delay of several slots from (frame timing used for wireless communication from the A transmitter).

In this embodiment, the memory address generation circuits G1 to G3 generate the read timing for reading the correlation value of the same information for each path from the memories M1 to M3 as described above, so that the same information for each path is obtained. Reading timing generating means for generating a timing for reading the correlation value from the storage means by giving a predetermined delay to the receiving timing of each path. Here, in this example, as described above, the read timing is generated by giving a signal processing time delay of one spread code to the time when the correlation value of each path is stored in the memories M1 to M3. The correlation values of the paths are stored in the memories M1 to M3.
Is determined based on the reception timing of the signal on each path, so that the read timing is generated by giving a predetermined delay to the reception timing of each path.
Note that the predetermined delay may be arbitrarily set according to the usage status of the device or the like.

Each of the delay sample counter circuits D1 to D3 is provided corresponding to each path. The frame timing, the sample clock, and the dump signal for each path are input to the delay sample counter circuits D1 to D3. Has the function of detecting the delay time and outputting it to the comparator 2. Note that the sample clock is a clock signal that measures the time every predetermined unit time (one sample time). In this example, the delay time is detected based on this sample clock.

Here, in this example, the configuration and operation of each of the delay sample counter circuits D1 to D3 are the same.
The configuration and the like of the delay sample counter circuits D1 to D3 will be shown as a representative of the delay sample counter circuit D1. FIG. 2 shows each of the delay sample counter circuits D1 to D3.
An example of the timing of a signal or the like input to is shown,
The sample clock and the frame timing are signals common to all the delay sample counter circuits D1 to D3. This figure will be further described later.

As shown in FIG. 1, the delay sample counter circuit D1 of this embodiment comprises an OR gate 11, a flip-flop 12, and a counter 13 with enable. The OR gate 11 has a function of inputting a frame timing and a counter enable signal from a flip-flop 12, which will be described later, and outputting the result of the OR logic to the flip-flop 12 as an OR signal.

Specifically, in the OR gate 11 of this embodiment,
When both the input frame timing and the counter enable signal are “0” value, an OR signal of “0” value is output to the flip-flop 12, while at least one of the input frame timing and the counter enable signal is “0”. If the value is “1”, an OR signal of “1” value is output to the flip-flop 12. Here, the frame timing having a value of “1” indicates a state where the frame timing is input, for example, whereas a value of “0” indicates a state where the frame timing is not input (no signal input). State).

The flip-flop 12 receives the sample clock, the OR signal from the OR gate 11 and the dump signal on the path corresponding to the delay sample counter circuit D1, and for example, a signal obtained by delaying the input OR signal by one sample time. O as a counter enable signal
It has a function of outputting to the R gate 11 and the counter 13 with enable. In addition, the flip-flop 12 has a function of resetting the above-described counter enable signal to a “0” value in response to the input of the dump signal. In the initial state of the present example, the counter enable signal output from the flip-flop 12 is set to “0”.

The counter 13 with enable receives the frame timing, the sample clock, and the counter enable signal from the flip-flop 12 described above. When the input counter enable signal has the value “1”, the counter value is incremented by 1 every sample time. While the counter enable signal has a function of holding the counter value without increasing when the input counter enable signal has a value of “0”, the input counter enable signal changes from a value of “1” to a value of “0”. And outputs the held counter value to the comparator 2 after the counting operation is completed. The counter with enable 13 has a function of resetting the counter value to “0” in response to the input of the frame timing.

An example of the operation of the delay sample counter circuit D1 will be described with reference to FIG. First, O as an initial state
It is assumed that the frame timing and the counter enable signal input to the R gate 11 are both “0” values, and the count value of the counter with enable 13 is “0”. In this state, when the frame timing input to the OR gate 11 changes from “0” value to “1” value, the OR gate 11
Of the OR signal output from the flip-flop 12 changes from "0" value to "1" value, the counter enable signal output from the flip-flop 12 changes from "0" value to "1" value. The count value of the counter 13 starts to be counted.

In this manner, the counter 13 with enable is provided.
When the count value starts counting, the counter enable signal output from the flip-flop 12 has changed to the "1" value as described above, so that the frame timing input to the OR gate 11 changes to the "0" value. When returning, the count value continues to be increased. When the count value continues to be increased, the dump signal is output to the flip-flop 1.
2, the counter enable signal output from the flip-flop 12 is reset to “0”, thereby terminating the counting operation of the counter 13 with the enable.

As described above, in the delay sample counter circuit D1 of this embodiment, the time from the input of the frame timing to the input of the dump signal of the path corresponding to the delay sample counter circuit D1 (that is, the time of the input of the dump signal) A delay time from the frame timing) can be detected by the above-described counter value, and the counter value with the enable is output from the counter with enable 13 to the comparator 2 as the detected delay time. In FIG. 2, for example, the count value detected for the path corresponding to “finger # 1” is “2”, and the count value detected for the path corresponding to “finger # 2” is “6”. In this case, an example is shown in which the count value detected for the path corresponding to “finger # 3” is “4”.

When the count operation of the count value is completed, the frame timing and the counter enable signal input to the OR gate 11 are both "0" values.
Thereafter, when the frame timing input to the OR gate 11 becomes the value “1” again, the counter 13 with the enable.
Is reset to "0", and the same counting process is repeated again. As described above, the delay sample counter circuit D1 of the present example performs the same operation every time the frame timing is input.

The comparator 2 has a delay sample counter circuit D
The counter values input from 1 to D3 are compared to detect which is the minimum counter value, and the minimum counter value (for example, the counter value corresponding to “finger # 1” in the example shown in FIG. 2). Is output to the selector 3 to specify a path corresponding to the delay sample counter circuit (any one of the delay sample counter circuits D1 to D3) that has output. Here, since the minimum counter value indicates that the delay time of the dump signal from the frame timing is minimum, the same information is transmitted through the paths corresponding to the delay sample counter circuits D1 to D3 that output the minimum counter value. Is considered to have been received. That is, the information output from the comparator 2 to the selector 3 specifies the path on which the preceding wave has been received.

In this embodiment, the delay sample counter circuits D1 to D3 and the comparator 2 detect the paths on which the preceding wave of the same information has been received as described above, so that the same information is detected based on the reception timing of each path. A path detecting unit configured to detect a path having the earliest reception timing (that is, a path that has received the preceding wave) is configured. In this example, the path on which the preceding wave was received is detected based on the dump signal. However, as described above, the dump signal for each path is generated based on the reception timing of the signal for each path. Substantially, the path that has received the preceding wave is detected based on the reception timing.

The selector 3 selects a memory address generation circuit (one of the memory address generation circuits G1 to G3) corresponding to the path specified by the information input from the comparator 2, that is, the path on which the preceding wave has been received. It has a function of outputting memory addresses output from the selected memory address generation circuits G1 to G3 to the memories M1 to M3. Note that, as described above, each memory M is output from the selected memory address generation circuits G1 to G3 via the selector 3.
When the memory address is output to the memory 1 to M3 at the read timing, the correlation value of the same information for each path stored in each of the memories M1 to M3 is simultaneously output to the RAKE combining unit 4.

In this example, the memory address generation circuits G1 to G1 corresponding to the path where the selector 3 has received the preceding wave are described.
By selecting the read timing corresponding to the path by selecting G3, the selecting means for selecting the read timing corresponding to the path detected by the path detecting means from the read timings generated by the read timing generating means is provided. It is configured.

The RAKE combiner 4 has three memories M1 to M
3 has a function of synthesizing correlation values (three correlation values in this example) of the same information for each path, which are input simultaneously from 3 and outputs the synthesis result to, for example, a demodulation unit (not shown). A demodulation unit (not shown) demodulates the synthesis result obtained by the RAKE synthesis unit 4. In this example, the RAKE combining unit 4 combines the correlation values of the same information for each path input from the three memories M1 to M3,
Composing means for composing the correlation value of the same information for each path read from the storage means at the selected read timing is configured.

With the above configuration, in the CDMA receiver of the present embodiment, when receiving a radio signal (spread signal) of the same information arriving via a plurality of different paths, first, the reception timing detection unit 1 firstly sets each of the paths. , And then detects the sliding correlators C1 to C1.
The received signal for each path is despread by C3, and the correlation value (despread data) obtained by the despread is stored in each memory M1.
To M3 temporarily. In addition, the memory address generation circuits G1 to G3 generate the readout timing when the reception signal of each path is assumed to be the preceding wave, and for example, each delay sample counter circuit D1 in parallel with the above despreading processing and the like. ＤD3 and the comparator 2 detect the path on which the preceding wave was actually received. Then, the selector 3 outputs a memory address to each of the memories M1 to M3 at a read timing corresponding to the path on which the preceding wave is actually received, whereby the same information of each path simultaneously read from the three memories M1 to M3 is read. The correlation values are combined by the RAKE combining unit 4.

As described above, the CDMA receiver of the present embodiment can despread the received signal for each path even before detecting the path that has received the preceding wave. As described above, the despreading processing of the received signal for each path and the detection processing of the path receiving the preceding wave can be executed in parallel.

Therefore, in the CDMA receiver of this embodiment, for example, as shown in the above-mentioned conventional example, the despreading processing and the like cannot be performed unless the preceding wave detection processing and predetermined allocation processing are performed. Therefore, it is possible to smoothly perform the despreading process and the like of the received signal for each path, and thereby to RAKE combine the correlation value of the same information for each path without dropping the received data. .

In the CDMA receiver of this embodiment, as a preferred embodiment, the component for detecting the path on which the preceding wave is received is constituted by a hardware circuit such as the above-described delay sample counter circuits D1 to D3. Can reduce the amount of software processing compared to the conventional device that mainly detects the route that received the software using software, thereby reducing the load on the software during communication. Can be. Also,
In the CDMA receiver of this example, for example, it is not necessary to perform the allocation processing as shown in the conventional example.
The burden on software can be reduced.
When the amount of software processing during communication is reduced in this way, for example, noise output from the CPU executing the processing can be reduced, and thus the signal reception sensitivity of the CDMA receiver can be improved. It is.

Here, in the above-described embodiment, a configuration in which the correlation values (despread data) for up to three paths can be synthesized by the CDMA receiver (that is, the number of fingers in the conventional example is three). In the present invention, the number of paths capable of synthesizing the correlation value of the same information may be arbitrary as long as it is plural.

In the above embodiment, one radio signal arrives at the CDMA receiver via a plurality of different paths.
Although a case has been described in which a signal wirelessly transmitted from one CDMA transmitter propagates through a plurality of different paths due to reflection, diffraction, etc. and arrives at a CDMA receiver, the CDMA receiver according to the present invention employs, for example, a plurality of CDMA transmitters. It is also applicable to the case where the same information is intentionally realized by spreading and modulating the same information from a plurality of antennas and from a plurality of antennas, and from a plurality of signals received by such multipath. It is also possible to combine the obtained correlation values of the same information.

Further, the configuration of the CDMA receiver according to the present invention is not necessarily limited to the one described in the above embodiment, but the point is that the read timing is generated based on the signal reception timing of each path and the same information is generated. A path having the earliest reception timing is detected, a read timing corresponding to the path is selected, and a correlation value of the same information for each path read from the storage means at the selected read timing is synthesized. If so, any configuration may be used.

As an example, various processes performed by each functional unit provided in the CDMA receiver according to the present invention include, for example, configuring each functional unit for executing the process as an independent hardware circuit. In addition to this, it is also possible to adopt a configuration in which the processor controls the process by executing a control program in a hardware resource including a processor and a memory.

The CDMA receiver according to the present invention can be applied to, for example, a base station or a mobile station (for example, a portable telephone terminal or the like) adopting the CDMA system and has only a receiving function. The present invention can be applied not only to a receiving device but also to a communication device having both a transmitting function and a receiving function, for example.

[0066]

As described above, the CD according to the present invention is
According to the MA receiver, a radio signal (spread signal) of the same information arriving via a plurality of different paths is received, and a correlation value (despread signal) of the same information obtained by despreading a received signal of each path is obtained. When the data is stored in a memory or the like in association with each other and then read and combined, a readout timing is generated by giving a predetermined delay to the signal reception timing of each path, and the reception timing of the same information is the earliest path. Is detected and the read timing corresponding to the path is selected, and the correlation value of the same information for each path read at the selected read timing is synthesized. For example, as shown in the above conventional example, Since the despreading processing cannot be performed only after the detection processing or the predetermined assignment processing has been performed, the despreading processing of the received signal can be smoothly performed. Can be done, this makes it possible to synthesize a correlation value of the same information for each path without thereby missed the received data.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a CDMA receiver according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a timing of a signal or the like input to a delay sample counter circuit.

FIG. 3 is a diagram for explaining a configuration example of a CDMA receiver according to a conventional example.

[Explanation of reference numerals] 1. reception timing detection section, 2. comparator, 3.
・ Selector, 4 ・ ・ RAKE synthesis unit, C1 to C3 ・ ・
Sliding correlator, M1-M3 memory,
G1 to G3 ··· memory address generation circuit, D1 to D3 ·
・ Delayed sample counter circuit, 11 ・ ・ OR gate,
12. Flip-flop, 13. Counter with enable,

Claims (1)

[Claims] 1. A CDMA receiving a spread-modulated signal.
A receiver for detecting a reception timing of a signal for each path for a radio signal of the same information arriving via a plurality of different paths; a reception for each path based on the detected reception timing; Despreading means for detecting a correlation value between a signal and a spreading code; storage means for storing correlation values of the same information detected for each path in association with each other; and storing a correlation value of the same information for each path. Read timing generation means for generating a timing read from the means by giving a predetermined delay to the reception timing of each path, and path detection means for detecting a path having the earliest reception timing of the same information based on the reception timing of each path And the read timing corresponding to the path detected by the path detecting means is selected from the read timings generated by the read timing generating means. That a selection means, CDMA receiver characterized by comprising synthesizing means for synthesizing the correlation values of the same information for each path read from the storage means at a read timing to the selected and.