JP2000278144A - Error correction decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale of an error correction decoder by decreasing a capacity of a memory without deteriorating decoding arithmetic precision in the case of decoding turbo code. SOLUTION: The error correction decoder has 1st-3rd memories 3-5 that store ya, yb, yc resulting from separating turbo code received data (y) by an S/P conversion section 2, 4th and 5th memories 12, 13 that store a result of backward probability calculated earlier by a 1st D (transition probability) calculation section 9 and a B (backward probability) calculation section 11, a 6th memory 7 that stores preceding reliability information, a 7th memory 21 that stores this reliability information and decoded data, an L (combined probability) calculation section 16 that obtains a combined probability on the basis of the forward probability and the backward probability by a 2nd D calculation section 10 and an A (forward probability) calculation section 15, an L(u) calculation section 17 that calculates decoded data, an Le(u) calculation section 18 that calculates reliability information and a MAP control section (repetitive control section) 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction decoder for receiving encoded data, correcting an error, and decoding the data, and more particularly, converting transmission data into a turbo code combining a convolutional code and an interleave. The present invention relates to an error correction decoder that receives the encoded data, receives the encoded data, and corrects and decodes the error even if the error is included.

[0002]

2. Description of the Related Art In a communication system, various error correction codes are employed to relieve data transmission errors. For example, transmission data is convolutionally encoded and transmitted,
On the receiving side, for example, Viterbi (Viterb) for performing maximum likelihood decoding
i) It is known that error correction decoding is performed by a decoder to restore data. Also, in the case of a communication system including a wireless line, there is a large possibility that a burst error will occur in the wireless line. The above-described convolutional code can perform error correction decoding for a random error, but has a low error correction capability for a burst error.

Therefore, it has been proposed to apply a turbo code which combines a convolutional code and an interleave.
For example, the communication system illustrated in FIG. 13 includes an encoder 51 that turbo-codes transmission data u and a communication path 5 such as a wireless line.
2 and a decoder 53. The transmission side encoder 51 performs turbo encoding of the transmission data u, and generates encoded data xa, xb. xc is transmitted to the communication path 52, and the encoded data ya, yb, yc via the communication path 52 is input to the decoder 53 on the receiving side, and the received data u 'is restored by decoding the turbo code. become.

The encoder 51 on the transmission side includes convolutional encoders (ENC1, ENC2) 54, 55 and an interleaver (π) 56, and is multiplexed by a transmission processor (not shown). Modulate to the transmission frequency and transmit. In this case, the convolutional coding unit 54 performs convolutional coding of the transmission data u, and the convolutional coding unit 55 interleaves the transmission data u in the interleave unit 56 to perform convolution. The encoding is performed. This interleaving is generalized to apply multi-stage interleaving.

That is, turbo coded data is composed of transmission data xa (= u), data xb by convolutional coding, and data xc which is subjected to convolutional coding after interleaving. And send it. Further, by combining multi-stage interleaving and convolutional coding,
By multiplexing and transmitting as xd, xe,..., it is possible to improve the error correction capability.

[0006] The decoder 53 includes decoding sections (DEC1, DE1).
C2) It includes 57, 59, an interleave section (π) 58, and a deinterleave section (π ^-1 ) 60, and demodulates a signal received via the communication path 52 by a reception processing section (not shown), and performs serial-parallel Demultiplexing is performed by conversion, and received data y
a, yb, yc are input to the decoder 53. Then, the decoding unit 57 sets ya, y corresponding to the data xa, xb on the transmission side.
b to perform soft-decision decoding and receive data yc
Corresponds to the data xc obtained by interleaving the original data u and performing convolutional coding. The interleaving unit 58 interleaves the decoded data of the decoding unit 57 so as to correspond to the interleaved data xc. input. Then, soft decision decoding is performed, and the deinterleave unit 60
Is deinterleaved so as to return to the original state, thereby obtaining decoded data u ′. This decrypted data u 'is
"a" is input to the decoding unit 57 again, and the same operation as described above is repeated. By repeating this decryption process multiple times,
Error correction decoding can be performed not only for random errors but also for burst errors.

[0007] As a decoding method of the turbo code, for example, a MAP (maximum posterior probability) decoding method and a SOVA
(Soft-decision Viterbi algorithm) A decoding method is known, and if briefly described, the former MAP decoding method is as follows.
The forward probability α and the backward probability β are calculated using the transition probability of the received data, and are “1” or “0” for each time (bit) using the forward probability α and the backward probability β. "
, And the difference (soft decision value) is determined.

In the SOVA decoding method, hard decision data is obtained in the same manner as in the Viterbi decoder, but the maximum likelihood path (the most probable path) and the counter path (the second most probable path) are used. Is used to obtain a soft decision value. This SOVA decoding method uses a simplified algorithm as compared with the MAP decoding method, so that the amount of calculation is small, but the error correction characteristic is MAP.
It will be inferior to the decoding scheme. Further, the MAP decoding method has better error correction characteristics than the Viterbi decoding method.

The basic decoding method of each of the above-mentioned decoding systems and the basic configuration of the decoder are described in various documents, but the configuration of a conventional decoder using the MAP decoding system is shown in FIG. Shown in In the figure, reference numeral 61 denotes an S / P converter, and 62
Is an input / output inverting unit, 63 to 66 are memories, 67 is a transition probability calculating unit, 68 is a backward probability calculating unit, 69 is a forward probability calculating unit, 70 is a memory, 71 is a joint probability calculating unit, and 72 is reliability. The information calculation unit 73 indicates a memory. A case where the configuration corresponds to the decoder 53 in FIG. 13 and the functions of the decoding units 57 and 59 are put together is shown.

[0010] Received data y (= ya, yb, yc) obtained by turbo coding via a communication path is input to an S / P conversion unit 61, separated into ya, yb, yc by serial / parallel conversion, and input. The data is input to the memories 63 to 65 via the output inverting unit 62. The input / output inverting unit 62 controls whether data corresponding to the information length is input to the memories 63 to 65 in the order of reception or to the memories 63 to 65 in the reverse order of reception.

[0011] The transition probability calculation unit 67 determines the state m (“00”, “0”) of the reception data ya and yb at a certain time k.
1), “10”, and “11”) at time (k−
The probability γ of transition from the state m in 1) is obtained.
In addition, in the state m at the time (k-1), the forward probability calculation unit 69 calculates the forward probability α ₁ that the original data is “1” and the forward probability α ₀ that the original data is “0”. And the transition probability γ at time k, the forward probability α _{1k at} which the original data is “1” and the forward probability α _0k at which the original data is “0” at time _k . Is calculated, and the calculation result is stored in the memory 70.

The backward probability calculating section 68 calculates the time (k +
Using the backward probability β and the transition probability γ of 1), the time (k
Backward probability β in each state m at time k before +1)
Is calculated. That is, the probability that the data is “1” and the probability that the data is “0” are obtained in accordance with the order of reception by the forward probability calculator 69 and stored in the memory 70, and the reverse probability is calculated by the backward probability calculator 68. That is,
The probability that the data is "1" and the probability that the data is "0" are calculated from the rear part to the front part of the reception data of the information length.

The joint probability calculating section 71 obtains joint probabilities λ ₁ and λ ₀ by multiplying the forward probabilities α ₁ and α ₀ of each state m at time k by the backward probability β. In this case, a combined probability of 2 m is obtained from the forward probability and the backward probability according to the number m of states. Also, reliability information calculation unit 7
2 is the sum of the probabilities of “1” in each state m and “0”
, And outputs the reliability L (u).
If (u)> 0, the decoding result u _k is "1", and L
(U) <0, then stores the decoded data "0" to the decoded result u _k to the memory 73. By transferring from the memory 73 to the memory 66, the transition probability to the received data yc, the forward probability, and the backward probability are obtained as described above and input to the joint probability calculation unit 71. That is, the data is transferred from the memory 73 to the memory 66 again, and the decoding process is repeated, and decoded data u ′ obtained as a result of performing this process a predetermined number of times is output.

[0014]

The conventional decoder has a problem in that the required memory capacity is increased. For example, information length N = 100, soft decision quantization bit number n = 5,
When the number of states is m = 4 and the number of states is 11 bits including likelihood information and the like, the memories 63 to 65 each have 100 × 5 = 5
00 (bit), the memory 66 is 100 × 8 = 800
(Bit), the memory 70 is 100 × 11 × (2 × m)
= 100 × 11 × 8 = 8800 (bits), memory 73
Is 100 × 11 = 1100 (bits), for a total of 1
This would require a capacity of 2200 bits.

The turbo code is suitable as an error correction code when the information length N is long. Therefore, if the information length N is 10 to 50 times the above case, the required memory capacity is 10 to 50 times. 50 times is required. Therefore, the circuit scale is increased, and the power consumption is correspondingly increased. In particular, if the number of states of the backward probability is 4, the forward probability from the forward probability calculation unit 69 is twice that of 8
Therefore, the capacity of the memory 70 occupies about 70% of the whole. An object of the present invention is to reduce the required capacity of the memory to reduce the circuit scale.

[0016]

According to the present invention, there is provided an error correction decoder comprising: (1) a memory for serially / parallel conversion of received turbo code data and storing data of at least an information length;
A first transition probability calculation unit (9) and a rear probability calculation unit (11) that calculate from the rear part to the front part of the data of the information length, and from the front part to the rear part of the data of the information length. A second transition probability calculation unit (10) and a forward probability calculation unit (15), and a rear probability calculated by the rear probability calculation unit corresponding to a division unit by dividing the information length into a plurality. (12, 13), a connection probability calculation unit (16) for combining the backward probability and the forward probability from the forward probability calculation unit in the memory, and a connection from the connection probability calculation unit A decoded data calculation unit (17) for obtaining decoded data based on the probability; and a reliability information calculation unit (18) for obtaining current reliability information based on the decoded data from the decoded data calculation unit and the previous reliability information. And the decrypted data or the current reliability information A memory (21) for storing the bets,
A forward probability, a backward probability, and a joint probability are calculated using a memory (7) for storing the previous reliability information and a part of the decoded data and the received turbo code data, and the decoded data and the reliability are calculated. A repetition control unit (25) for repeatedly calculating information a predetermined number of times.

(2) The received turbo code data is subjected to serial / parallel conversion by the serial / parallel conversion unit 2 to obtain the original data y of the systematic code.
a, second and third memories 3, 4, and 5 for storing at least an information length by separating the data into convolutional code data yb and convolutional code data yc after interleaving of the original data. A first RAM control unit 6 for controlling writing and reading of data to and from the first, second, and third memories, and from the rear to the front of the information length via the first RAM control unit. The first transition probability calculation unit 9 and the rear probability calculation unit 11 that calculate the transition probability and the rear probability based on the read data, and the rear probability calculation unit of the division unit length obtained by dividing the information length N. A fourth memory 12 for storing the use probabilities, a fifth memory 13 for storing only the backward probabilities for each division unit length obtained by dividing the information length N, and writing of data to the fourth and fifth memories. And second RAM for controlling reading A control unit 14, the first RAM
A second transition probability calculator 10 and a forward probability calculator 15 that calculate a transition probability and a forward probability based on data read from the front part to the rear part of the information length via the control unit;
A connection probability calculation unit 16 for obtaining a connection probability between the backward and forward probabilities, a decoded data calculation unit 17 for obtaining decoded data based on the connection probabilities from the connection probability calculation unit, A reliability information calculation unit 18 that obtains the current reliability information based on the decoded data, the data stored in the first memory 3, and the previous reliability information; and a sixth storage unit that stores the previous reliability information. A memory 7 and a third R for controlling writing and reading of data to and from the sixth memory.
An AM control unit 8, a seventh memory 21 for storing decoded data or reliability information from a decoded data calculation unit, a write selection unit 22 and a read selection unit for controlling writing and reading of data to and from the seventh memory 23, a repetition control unit 25 that calculates forward probabilities, rear probabilities, and joint probabilities by using a part of the decoded data and the received turbo code data, and repeatedly calculates the decoded data and the reliability information a predetermined number of times. And an interleave control unit 30 for controlling the first RAM control unit, the write selection unit and the read selection unit according to the interleave pattern.

The interleave control unit 30 is a memory for writing interleave pattern data from an external memory or a host device, a read-only memory in which interleave pattern data is written, or a digital signal processor (DSP) capable of generating interleave pattern data.
Can be configured.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining an embodiment of the present invention. In the decoding process of a turbo code, the backward probability β from the rear of the information length N to the front is calculated first. At the same time, the information length N is changed to L (= N ^1/2 , where the decimal point is carried up and a section of the remainder value M smaller than the L value may be included).
In each division, storing only the rear probability for each division unit length, reading the rear probability for each L when calculating the forward probability α, and calculating the rear probability from the position, It has a configuration for calculating the connection probability.

In FIG. 1, the received turbo code data y is composed of system-coded data ya, yb and data ya.
And the data yc convolutionally coded by interleaving the
Demultiplexed by serial-to-parallel conversion by ya,
yb and yc are input to the first RAM control unit 6. In this case, the data y, ya, yb, yc are based on soft decisions, and may have a 5-bit configuration, for example.

Reference numeral 1 denotes a main unit, and reference numerals 3 to 5 denote first, second, and third memories (RAMs). A first RMA control unit 6 controls reading and writing of ya, yb, and yc. .
Reference numeral 7 denotes a sixth memory (RA) for storing reliability information and the like.
M) and 8 are third RAM control units, 9 and 10 are first and second RAM control units.
D (transition probability) calculation unit, 11 is a B (rear probability) calculation unit, 12 and 13 are fourth and fifth memories (RAM) for storing the rear probability, 14 is a second RAM control unit, 15 is A
(Forward probability) calculator, 16 is an L (joint probability) calculator,
17 is an L (u) (decoded data) calculation unit, 18 is Le
(U) (reliability information) calculation unit, 19 and 20 are timing adjustment FFs (flip-flops), and 21 is a seventh memory (RA) for storing decoded data or current reliability information.
M), 22 is a write selector, 23 is a read selector, 24
Is an enable generation unit, 25 is a MAP (repetition) control unit, 26 is a write circuit, 27 is an MIL (multi-stage interleave) table memory, 28 is an external ROM
(Read only memory), 29 indicates a repetition operation group, and 30 indicates an interleave control unit.

The main section 1 manages and controls each section. The first to third memories 3 to 5 are each constituted by a random access memory (RAM), and together with the first RAM control section 6, For example, it has a configuration corresponding to the functions of the input / output inverting unit 62 and the memories 63 to 65 in FIG. Each of the memories 3 to 5 has a capacity corresponding to the information length N and the number n of soft decision quantization bits. The RAM control unit 6 includes the S / P conversion unit 2
Ya, yb, yc separated by
5 and the control of reading out ya, yb, yc used in the calculation of the forward probability α, the backward probability β, and the transition probability γ.

The memories 3 to 5 can be dual port memories, in which case, ya, y
The writing of b and yc and the calculation of the transition probability γ performed at the time of calculating the forward probability α are performed by using one of the ports. And the other port is controlled by the RAM control unit 6. When the number of times of the decoding process is odd, the normal reading of ya and yb is performed.
Control is performed so that reading corresponding to interleaving (MIL) of a (corresponding to pattern information of multistage interleaving from the MIL table memory 27) and normal reading of yc are performed.

The RAM control unit 8 writes the previous reliability information into the memory 7 and calculates the previous reliability required for calculating the transition probability γ when calculating the forward probability α and the backward probability β. This is for controlling the reading of information and the memory 7.
Can be a dual-port memory, in which case the reliability information is written and the forward probability α
One port is used when performing the transition probability γ operation at the time of calculation, and the other port is used when performing the transition probability γ operation during the backward probability β operation.

The first and second D calculation for calculating the transition probability γ are respectively provided before the B calculation unit 11 for calculating the backward probability β and before the A calculation unit 15 for calculating the forward probability α. Parts 9 and 10 are provided. The B calculation unit 11 has a function of calculating the backward probability β using the transition probability γ from the first D calculation unit 9 and preventing overflow in the calculation process. After calculating the backward probability from the rear part of the information length N to the front part by the B calculating part 11, the A calculating part 15 uses the transition probability γ from the second D calculating part 10 to calculate the forward probability α. Is started, and has a function of preventing overflow in the calculation process.

Further, the second RAM control unit 14 includes the B calculation unit 1
1 to control the writing of the backward probability β to the memory 12 and to control the reading of the backward probability β during the calculation of the joint probability performed simultaneously with the calculation of the forward probability α.
3, the backward probabilities of the calculation results for each L are sequentially written from the start address when calculating the initial backward probabilities, and are read from the last address when the initial back probabilities are calculated for each L when calculating the joint probabilities. This is to control the output. As a result, it is possible to reduce the memory capacity for storing the backward probability and to improve the accuracy in the case where the backward probability calculation is performed from the middle.

The L calculating section 16 calculates a joint probability using the forward probability α calculated by the A calculating section 15 and the backward probability β read from the memory 13 by the RAM control section 14. , L (u) calculation unit 17. This L
The (u) calculation unit 17 calculates reliability information using the connection probability and inputs the information to the Le (u) calculation unit 18 and the light selection unit 22. The Le (u) calculation unit 18 calculates the current reliability information from ya stored in the first memory 3 and the previous reliability information stored in the sixth memory 7, The decrypted data is calculated based on the reliability information and input to the write selector 22.

The write selection section 22 selects write data for the seventh memory 21, performs write control on the write data, and controls maximum value detection. The data and the reliability information are selected and stored in the memory 21, and in the case of other times, the current reliability information is selected and stored in the memory 21. In the write control, MIL (multi-stage interleave) writing is performed when the number of repetitions is, for example, an odd number, and normal writing is performed when the number of repetitions is an even number. The maximum value detection control is for detecting the most significant bit of the current reliability information.

The read selection unit 23 controls reading of the reliability information stored in the memory 21. When the number of times of the decoding process is the last, the read selection unit 23 reads the reliability information from the memory 21 as decoded data, and It is sent to the omitted circuit. The main functions of the read selection unit 23 are read control and bit extraction control. In the read control, if the number of repetitions of the decoding process is, for example, an odd number, the memory 21
Normal reading is performed, and in the case of an even number of times, MIL reading is performed. In the bit extraction control, the memory 2
Bit extraction is performed to match, for example, 11-bit reliability information stored in 1 with 8-bit reliability information based on the maximum value of reliability information in one frame.

The interleave control unit 30 also has an external R that stores a multistage interleave pattern externally.
An OM 28 is provided, and the MIL pattern memory read from the external ROM 28 by the write circuit 26 is stored in the MIL table memory 27 when the power is turned on. In accordance with the data from the MIL table memory 27, the RAM control unit 6 performs MIL reading from the memory 3, and performs MIL writing and M writing in the write selection unit 22 and the read selection unit 23.
Control with IL reading is performed. Therefore, external ROM2
By exchanging 8, the decoding process corresponding to an arbitrary MIL pattern can be performed.

The MAP control unit 25 is provided with the
9 to control the respective units by managing the number of repetitions of the decoding process and the like. The enable generation unit 24 has a function of supplying an enable signal to each unit in response to the repetition of the decoding process. Timing adjustment FF
Reference numerals 19 and 20 are for performing time adjustment of operation data and the like in consideration of the processing time.

Comparing the above configuration with the configuration of the conventional example shown in FIG. 14, in the conventional example, the forward probability is calculated first and stored in the memory 70, and then the backward probability is calculated and combined. According to the present invention, the backward probability is calculated first, the backward probability for each L for the information length N is stored in the memory 13, and then the forward probability is calculated. Assuming that the information length is N bits, the number of soft decision quantization bits is 5 bits, and the forward and backward probabilities are 11 bits, the received data is stored as shown in FIG. The memory has a capacity of N.times.5 (bits), and a memory for storing forward probabilities in the prior art (α calculation memory).
Is N × 1 because the forward probability includes 8 states
This would require a capacity of 1 × 8 (bits).

According to the present invention, the memory for α calculation is omitted,
This corresponds to the case of providing a β operation memory for storing the backward probabilities. Simply, the number of states is half of the forward probabilities, so that the capacity becomes N × 11 × 4 (bits), and the memory capacity is reduced by half. can do. Further, according to the present invention, for each L (= N ^1/2 , where the decimal point is a carry value) obtained by dividing the information length N into a plurality, the fifth memory 13 for storing the backward probability at that time. And the fourth memory 12 that stores the backward probabilities in the L section, the lower β in FIG.
As shown in the calculation memory, the capacity of 11 × [(N / L) −2] × 4 (bits) (memory 13) for storing the backward probability for each L and 11 × L × 4 (bits) ( Memory 1
It can be realized by the capacity of 2). Therefore, the memory capacity can be significantly reduced as compared with the conventional example, and the circuit scale and power consumption can be reduced.

FIG. 3 is an explanatory diagram of the decoding process according to the embodiment of the present invention. The received data having the information length N is subjected to a B (rear probability) operation, and the L (= N ^1/2 ) As shown as B memory write, the calculated backward probability is stored in memory 1
3 and the backward probabilities in the last section from 1 to L are all stored in the memory 12, and the A (forward probability) operation and the L (joint probability) operation are performed as indicated by arrows. Do.

In the next section from L to 2L, the backward probability at the time of 2L is read from the memory 13, and using this as an initial value, a B operation is performed on 2L to L, and an A operation and an L operation are performed on L to 2L. Is performed, and in the next 2L to 3L section, the backward probability at the time of 3L is read from the memory 13, and
Using this as an initial value, a B operation is performed on 3L to 2L, and an A operation and an L operation are performed on 2L to 3L,
In the next section from 3L to 4L and the section from 4L to N,
Similarly, the L operation is performed.

Accordingly, the rear probability is calculated from the rear part to the front part of the information length N, and the calculated rear probability for each division unit L is stored in the fifth memory 13.
Is stored in the fourth memory 12, the forward probability is calculated together with the forward probability, and the joint probability is calculated using the forward probability and the backward probability. Calculation can be performed.

FIG. 4 is an explanatory view of a main part of another embodiment of the present invention, and relates to an interleave control unit 30 for the RAM control unit 6, the write selection unit 22, and the read selection unit 23 in FIG. Only the configuration is shown. (A) of FIG.
Is a MIL table memory (RAM) 3 from a host device (not shown) via a bus 33 via a write circuit 32.
1 shows a configuration in which MIL pattern data is written. Even after the MIL pattern data is incorporated in the receiving apparatus as an error correction decoder, data corresponding to the MIL pattern in the communication system is written in the MIL table memory 31. A turbo code decoding process can be performed.

FIG. 4B shows a case where an MIL table memory (ROM) 34 is provided, and a case where a read only memory (ROM) in which MIL pattern data is written is used. FIG. 3C shows a case in which a digital signal processor (DSP) 35 is provided, and it is possible to easily calculate MIL pattern data according to a program. It is possible to easily perform the turbo code decoding process even for a communication system that performs the processing.

FIG. 5 is a flowchart of the embodiment of the present invention, in which the number of executions T is set to 0 as initialization (A1),
The received data is subjected to S / P conversion and written into RAM1-3. That is, the serial / parallel conversion is performed by the S / P converter 2 and ya, yb,
yc, and write to the first to third memories 3 to 5, respectively (A2). Then, T = T + 1 is set (A3), and it is determined whether the number of executions T is 1 or not (A4).

When T = 1, the input data 3 (prior likelihood) for D (transition probability) calculation is all “0” (A
5) It is determined whether the number of executions T is the final number N (A6). If T ≠ 1 in step (A4), D (transition probability) calculation input data 3 (prior likelihood) is set as output data of the MIL-RAM (memory 21) (A
8). If T = N in step (A6), MI
L (u) of write data to L-RAM (memory 21)
(A7), and if T ≠ N, the MIL-RAM
Le (u) is set in the write data to the (memory 21) (A9).

Then, it is determined whether the number of executions T is an odd number (A10). If the number is an odd number, the reading of the RAM 1 (first memory 3) is set to a normal read (A11).
D calculation input data 2 (yb or yc) is set as output data of RAM 2 (second memory 4) (A12), and M
The writing to the IL-RAM (memory 21) is set to the MIL write (A13), and the MIL-RAM (memory 21) is set.
Is set to the MIL read (A14).

If T = even in step (A10), the reading of the RAM 1 (first memory 3) is set to the MIL read (A17), and the D-calculating input data 2 (y
b or yc) is set in the output data of the RAM 3 (third memory 5) (A18), and the MIL-RAM (memory 2
Set the writing to 1) to normal write (A1
9), the reading of the MIL-RAM (memory 21) is set to normal reading (A20), and the process proceeds to MAP (maximum posterior probability decoding) processing (A15).

When the MAP processing is completed, T = N
It is determined whether or not (A16). If T ≠ N, the process proceeds to step (A3). If T = N, L (u) is set to MI.
Normal read from L-RAM (memory 21) (A2
1) Output as decoded data.

FIG. 6 is a flowchart for calculating the initial backward probability according to the embodiment of the present invention.
Perform 1). In this case, L = N ^1/2 (the decimal point is a carry), and the remainder value M = L ² −N is obtained. Then, the processing counter X and the data counter Y are initialized (X =
0, Y = 0) (B2). Then, B calculation, that is, the calculation of the backward probability in the B calculation unit 11 is performed (B3), and it is determined whether or not the remainder value M = 0 (B4).
It is determined whether or not Y ≦ M (B5). When the data counter Y is equal to or smaller than the remainder value M, it is determined whether or not X = M (B6).
In the case of 判定 M, it is determined whether or not Y = N (B7).
N, that is, when the data counter Y becomes equal to the information length bit number N, the processing shifts to the Le (u) calculation operation (B14), and when Y ≠ N, the processing counter X and the data counter Y are each incremented by +1. (B8), and then proceed to step (B3).

If M = 0 in step (B4) and if Y> M in step (B5),
It is determined whether or not Y ≧ P (B9). This P indicates a pointer value writing period. If Y ≧ P, the B (rear probability) calculation result is written to the RAM 4 (fourth memory 12) (B13), and the process proceeds to step (B7). Also Y ≧
If not P, it is determined whether X = L (B10), and X
If ≠ L, the process proceeds to step (B7).

If X = L or X = M in step (B6), the calculation result of B (probability for backward) is calculated as RA
Write to M5 (fifth memory 13) (B11), X = 0
(B12), and the process proceeds to step (B7).

FIG. 7 is a flowchart for calculating the connection probability according to the embodiment of the present invention. The same reference numerals as in FIG. 5 denote different parts, where N = number of information length bits and L =
N ^1/2 , I = data bit counter, J = read counter of RAM1 (first memory 3), X = processing counter for backward probability calculation, Y = read counter of RAM5 (fifth memory 13) .

First, L is determined (C1). this is,
The L obtained in the above step (B1) can be used. As initialization, I = 0, J = 0, X =
0, Y = 0 (C2). Then, J = I + 2L is set (C3), X = 0 is set (C4), and it is determined whether J <N (C5).

If J <N is not satisfied, it means that the value of the read counter J is larger than the information length N, so that J = N (C6), and the process proceeds to step (C7). If J <N, the process directly proceeds to step (C7). And X
= 0 is determined (C7), and if X = 0, the RAM
5 (fifth memory 13), the data of the address value “Y” is read, and the B calculation data is stored in RAM 4 (fourth memory 1).
Write to 2) (C8). If X ≠ 0, RAM1
The data of the address value "J" is read from the (first memory 3), and the B calculation result is written to the RAM 4 (fourth memory 12) (C9).

Then, the forward probability A is calculated (C1
0), the B (backward probability) data of the address value “X” is read from the RAM 4 (the fourth memory 12) (C1
1), L, L (u) and Le (u) are calculated (C1
2). Then, it is determined whether or not I = N (C13). When the data bit counter I is equal to the number of data bits N, the process is terminated. When I ≠ N, I = I + 1, J =
J-1, X = X + 1 (C14), and it is determined whether or not X = L (C15).

If X ≠ L, the process proceeds to step (C7). If X = L, Y = Y + 1 is set (C16).
The surface of the RAM 4 (fourth memory 12) having the surface configuration is switched (C17), and the process proceeds to step (C3).

FIG. 8 is an explanatory view of the state transition of the main part according to the embodiment of the present invention. When the input data enable signal ENB becomes "1" from the initial state Idle, the S / S
From P conversion to RAMs 1 to 3 (first to third memories 3 to 5)
The state is changed to the state Write until the write to the memory is performed, and then the enable signal ENB is set to “0”, thereby setting the state of the decoding process to Step. This state Step corresponds to the decoding process (Stepping-Stone-Sub-Lo) shown in FIG.
g-MAP processing).

Then, the end signal Ste in the state Step
When p_End becomes “1”, the decoding process ends, and when the decoded data request signal REQ becomes “1”, the decoded data output state Rea.
d. When the decoded data request signal REQ becomes "0", the state returns to the initial state Idle.

FIG. 9 is an explanatory diagram showing the state transition of the MAP control unit according to the embodiment of the present invention. The MPA control unit 2 shown in FIG.
5 shows a state transition in the repetition control of the MAP processing start signal MAP_ST from the initial state Idle.
When the ART becomes “1”, the state becomes Init in which the B calculation unit 11 operates, and when the calculation of the backward probability from the rear part to the front part of the information length N is completed, the end signal Init of the state Init When End becomes “1”, the B calculation unit 1
1 and the A calculation unit 15 operate at the same time Cal A, and the calculation of the connection probability is performed. And this state C
al A end signal CalA of A When End becomes “1”, the state Cal in which only the A calculation unit 15 operates L.

Then, the last decoding signal LAST becomes "0".
And the end signal CalL of the state CalL When End becomes “1”, the state In in which only the B calculator 11 operates.
it. That is, when the last decoding signal LAST continues to be “0”, the repetitive operation is performed. Also, the last decoding signal LAST is "1", and the end signal CalL in the state CalL. When the End becomes “1”, the MAP process ends. Then, the turbo decoding end signal TU
RBO When END becomes “1”, the state shifts to the initial state Idle, and decoding of the information length N of the next received turbo code is started.

FIG. 10 is a diagram for explaining the operation of the RAM control unit according to the embodiment of the present invention, in which the memories 3 to 5, 7 are constituted by dual port memories having a first port and a second port. Is shown. (A) and (b) of FIG.
To (c), (d), and (e) show the load signal and the enable signal of the first ports of the third memories 3 to 5, respectively.
5 shows a load signal, a load select signal, and an enable signal of the second ports of the third to third memories 3 to 5. (F) and (g) show a load signal and an enable signal of the first port of the sixth memory 7, and (h), (i),
(J) and (k) show the load signal, load select signal, enable signal, and write / read signal of the second port.

The enable generation unit 24 (see FIG. 1) generates an enable signal and a load signal, and
It is distributed to the control units 6, 8, and 14, and the main unit 1
INIT from When the START signal is asserted, a read enable signal having a continuous data bit length for reading the memories 3 to 5 is generated as shown in FIG. CALA output from the main unit 1 S
When the TART signal is asserted, as shown in (c), a 1-bit load signal for each L for calculating B and as shown in (e), a continuous read of (L-1) length. An enable signal is generated, and an L-length continuous read enable signal for A calculation is generated.

The load signals and enable signals (f) to (j) for the first port and the second port of the sixth memory 7 are the same as those of the first to third memories 3 to 5 described above. (A) to (e) for the first port and the second port
And the same case as the load signal and the enable signal.

FIG. 11 is a diagram for explaining the operation of the RAM control unit for storing the backward probability according to the embodiment of the present invention.
Memories 12 and 13 are constituted by a dual-port memory having a first port and a second port.
2 shows the case of having a two-sided configuration. 6A and 6B show a load signal and an enable signal for the first port of the memory 12, and FIGS.
Indicates a load signal and an enable signal for the second port. (E) and (f) show a load signal and an enable signal for the first port of the memory 13,
(G) and (h) show a load signal and an enable signal for the second port.

As B calculation from the main unit 1, INIT
When the START signal is asserted, the memory 1
For L, a write enable signal for the memory 13 having a 1-bit length is generated for each L, and a continuous write enable signal having an L length is generated for the memory 12. Also CALA S
When the TART signal is asserted, a read enable signal for the memory 13 having a length of 1 bit for each L is generated,
A write enable signal for the memory 12 having the L length is generated. In addition, a read enable signal for the memory 12 having a continuous data bit length is generated for calculating the connection probability. Thus, the backward probability for each L is stored in the memory 13, and the backward probability in the L section is stored in the memory 12.

FIG. 12 shows an operation timing chart of the embodiment of the present invention. RAM4 and RAM5 show the fourth and fifth memories 12 and 13 of FIG.
2) shows a two-surface configuration of (surface) and (two surfaces). Also MIL-
The RAM refers to the memory 21 of FIG. W indicates writing to the memory, and R indicates reading from the memory.

First, B (rear probability) is calculated, and the information length N is divided for each L, and for each L (L, 2L,... [(N /
L) -2] L, [(N / L) -1] L), write the backward probabilities into the RAM 5 (fifth memory 13), and write backward probabilities for L to 0 corresponding to the head of the received data. R
Write to (one side) of AM4 (fourth memory 12).

Then, B calculation, A calculation, L calculation, L calculation
(U) calculation, Le (u) calculation, and MIL-RAM writing are performed. First, the backward probability between 2L and L is calculated by reading from the RAM 5 (fifth memory 13).
The backward probabilities in the sections 1 to L are read from (one surface) of the RAM 4 (the fourth memory 12), and the RAM 4 (the fourth memory 1) is read.
In (2) of (2), the calculated rear probability between 2L and L is written.

Further, based on the forward and backward probabilities by A calculation, L (combination probability) is calculated, then L (u) is calculated, then Le (u) is calculated, and MIL- RAM
By writing to the (seventh memory 21), a
After the period of + b + c + d + e, the first bit decoded is MIL−
The data is written to the RAM (seventh memory 21). After this,
Decoding is performed sequentially in an overlapping manner in terms of time.

The backward probability is 3L to 2L based on the backward probability stored for each L from the RAM 5 (fifth memory 13).
The backward probabilities of L, 4L to 3L,... Are calculated. Therefore, as compared with the case where the rear probability is calculated from the rear part of the information length N to the front part for each division unit, the rear probability in the division unit is stored based on the stored rear probability. Since the probability is calculated, the calculation time can be reduced without lowering the accuracy.

The present invention is not limited to the above-described embodiment, but can be variously modified. For example, a case is shown where multi-stage interleaving is applied as a turbo code, but other interleaving patterns can be applied.

[0067]

As described above, according to the present invention, ya, yb, and ya are separated by serial-to-parallel conversion of received turbo code data.
first to third memories 3 to 5 for storing yc at least for the information length N, and a first transition probability calculating unit (D calculating unit) 9 for calculating from the rear to the front of data of the information length N And a rear probability calculating section (B calculating section) 11, a second transition probability calculating section (D calculating section) 10 for calculating from the front to the rear of data of the information length N, and a forward probability calculating section ( A calculation unit) 15, fourth and fifth memories 12 and 13 for dividing the information length N into a plurality and storing the rear probability calculated by the rear probability calculation unit 11 corresponding to the division unit L, respectively. The backward probability and forward probability calculation unit 10 from the memory 12
A connection probability calculation unit (L calculation unit) 16 for obtaining a connection probability based on the forward probabilities from, a decoded data calculation unit (L (u) calculation unit) 17 for obtaining decoded data based on the connection probability, A reliability information calculation unit (Le (u) calculation unit) 18 for obtaining the current reliability information using the data, the data ya stored in the first memory 3, and the previous reliability information; A seventh memory 21 for storing degree information;
Sixth memory 7 for storing previous reliability information, and repetition control unit (MAP control unit) 25 for controlling repetition calculation
And the backward probability is calculated first,
And the information length N is L (= N ^1/2 , where the decimal point is a carry)
The backward probability for each of the divided units is stored in the fifth memory 1
3, the required memory capacity can be significantly reduced as compared with the conventional example, and the accuracy of the backward probability can be prevented from lowering. There is an advantage that the error correction capability can be increased as compared with the SOVA decoding method, and the circuit scale can be reduced to reduce power consumption.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of one embodiment of the present invention.

FIG. 2 is an explanatory diagram of memory reduction.

FIG. 3 is an explanatory diagram of a decoding process according to the embodiment of the present invention.

FIG. 4 is an explanatory view of a main part of another embodiment of the present invention.

FIG. 5 is a flowchart of the embodiment of the present invention.

FIG. 6 is a flowchart for calculating an initial rear probability according to the embodiment of the present invention.

FIG. 7 is a flowchart for calculating a joint probability according to the embodiment of the present invention;

FIG. 8 is an explanatory diagram of state transition of a main unit according to the embodiment of the present invention.

FIG. 9 is an explanatory diagram illustrating state transition of a MAP control unit according to the embodiment of this invention.

FIG. 10 is an explanatory diagram of an operation of a RAM control unit according to the embodiment of the present invention.

FIG. 11 is a diagram illustrating an R for storing a backward probability according to the embodiment of this invention;
FIG. 7 is an explanatory diagram of the operation of the AM control unit.

FIG. 12 is an operation timing chart according to the embodiment of the present invention.

FIG. 13 is a schematic explanatory diagram of a communication system.

FIG. 14 is an explanatory diagram of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main part 2 S / P conversion part 3-5 First to third memory 6 First RAM control part 7 Sixth memory 8 Third RAM control part 9,10 First and second D calculation part 11 B calculation unit 12, 13 Fourth and fifth memories 14 Second RAM control unit 15 A calculation unit 16 L calculation unit 17 L (u) calculation unit 18 Le (u) calculation unit 21 Seventh memory (RAM 22) write selection unit 23 read selection unit 24 enable generation unit 25 MAP control unit 26 write circuit 27 MIL table memory 28 external ROM 29 repetitive operation group 30 interleave control unit

 ──────────────────────────────────────────────────の Continued on the front page F term (reference) 5B001 AA10 AB02 AC01 AC05 AD06 AE04 5J065 AD10 AF02 AF03 AG06 AH06 AH09 AH14 AH17 5K014 AA01 BA11 EA01 FA16

Claims (5)

[Claims] 1. A memory for serially / parallel converting received turbo code data and storing data of at least an information length, and a first transition probability calculating unit for calculating from the rear to the front of the information length data And a rear probability calculator, a second transition probability calculator and a forward probability calculator that calculate from the front to the rear of the data of the information length, and divide the information length into a plurality of pieces and divide the information length into a plurality of pieces. A memory for storing the backward probability calculated by the backward probability calculating unit corresponding to the unit; and a combining probability calculating unit for combining the backward probability in the memory and the forward probability from the forward probability calculating unit. A decoded data calculation unit for obtaining decoded data based on the connection probability from the connection probability calculation unit; and a reliability for obtaining current reliability information based on the decoded data from the decoded data calculation unit and previous reliability information. Information calculation unit And a memory for storing the decoded data or the current reliability information; a memory for storing the previous reliability information; and a part of the decoded data and the received turbo code data, wherein the forward probability and the backward are used. An error correction decoder that calculates a use probability and a joint probability and that repeatedly calculates the decoded data and the reliability information a predetermined number of times. 2. The received turbo code data is subjected to serial-to-parallel conversion to be separated into original data of a systematic code, convolutional code data, and convolutional code data after interleaving of the original data. A first, a second, and a third memory for storing; a first RAM control unit for controlling writing and reading of data to and from the first, second, and third memories; and a first RAM control unit. A first transition probability calculation unit and a rear probability calculation unit that calculate a transition probability and a rear probability based on data read from the rear part to the front part of the information length via the information length; A fourth memory for storing the rearward probability of the divided unit length calculated by the rearward probability calculator, and a fifth memory for storing only the rearward probability for each of the divided unit lengths obtained by dividing the information length N. In the fourth and fifth memories A second RAM control unit that controls writing and reading of data to be read, and a transition probability and a forward probability based on the data read from the front to the rear of the information length via the first RAM control unit. A second transition probability calculation unit and a forward probability calculation unit for calculating a probability, a connection probability calculation unit for obtaining a connection probability between the rear probability and the forward probability, and a connection probability from the connection probability calculation unit. A decoded data calculation unit for obtaining the decoded data based on the decoded data from the decoded data calculation unit, the data stored in the first memory, and the previous reliability information. A reliability information calculation unit to be obtained; a sixth memory for storing the previous reliability information; a third RAM control unit for controlling writing and reading of data to and from the sixth memory; A seventh memory for storing reliability information, a write selector and a read selector for controlling writing and reading of data to and from the seventh memory; and a part of the decoded data and the received turbo code data. The first RAM control unit and the write selection unit according to an interleave pattern and a repetition control unit that calculates the forward probability, the backward probability, and the joint probability, and repeatedly calculates the decoded data and reliability information a predetermined number of times. And an interleave control unit for controlling the read selection unit. 3. The error correction decoder according to claim 1, wherein said interleave control unit includes a memory for writing interleave pattern data from outside. 4. The error correction decoder according to claim 1, wherein said interleave control unit is constituted by a read-only memory storing interleave pattern data. 5. An interleave control unit comprising: a digital signal generator for generating interleave pattern data by calculation;
3. The error correction decoder according to claim 1, wherein the error correction decoder comprises a signal processor.