JP2000277720A - Solid-state image sensing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce influence of a dark-time output upon a signal charge by providing a charge storing means which temporarily holds a signal charge from a light receiving means shaded from the outside light during the interval to its transfer. SOLUTION: A photoelectric converting sensor 11 forms a photodiode of pnp construction 18, 19, 25, and a received light signal is converted into electrons when light is received, and a signal charge converted photoelectrically according to the intensity of light and storage time is stored in the capacity of a pn junction 19, 25. A first read gate electrode 14 is caused to exist adjoining the converting sensor 11. Furthermore, a storing sensor 12 is caused to exist next to the gate electrode 14, and the potential of the pn junction 22, 25 of the storing sensor 12 is made deeper than that of the pn junction 18, 19 of the conveting sensor 11. When the voltage of a second read gate electrode 15 lowers, the potential of the first electrode 14 is raised, and the charge is transferred to the capacity of the pn junction 22, 25 of the storing sensor 12, stored and held here.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device capable of reducing noise due to dark output.
One-dimensional CCD solid-state imaging device.

[0002]

2. Description of the Related Art A solid-state imaging device has a photoelectric conversion function of converting an optical video signal into a charge image and a scanning function of reading the converted charge image from an output terminal as an electric signal. In a solid-state imaging device using a two-dimensional CCD (Charge Coupled Device), it is necessary to convert a two-dimensional charge image into one-dimensional information according to a certain rule and read it out during scanning. For example, simply
By arranging a plurality of two-dimensional CCD solid-state imaging devices in parallel and sequentially scanning the output, a two-dimensional CCD solid-state imaging device can be configured.

FIG. 4 (a) shows a conventional 2
FIG. 4B is a schematic cross-sectional view of a sensor unit and a register unit of the two-dimensional CCD solid-state imaging device, and FIG. 4B shows a corresponding potential level diagram. In FIG. 4A, the sensor 11
Form photodiodes (18, 19, 25) having a pnp structure, and convert received light signals into electrons. The signal charges photoelectrically converted by the photodiodes (18, 19, 25) are accumulated in the capacitance of the pn junction (19, 25). For reading signal charges, read gate (ROG: Read Out)
Gate) 14 and apply a voltage to read gate ROG1.
The signal charge stored in the photodiode is transferred below the n-buried channel 23 below the channel 4. By changing the conditions of ion implantation in each part below the electrodes 14, 15, and 16 to control the depth of the potential well at the time of applying a voltage, and further applying a voltage to the transfer gate 15 on the register side, The signal charges can be transferred below the 13 n-buried channels 24.

FIG. 5 schematically shows a plan view of a sensor section and a register section of a conventional two-dimensional CCD solid-state imaging device. In such a CCD solid-state imaging device, a first-stage sensor array 2-1 is used.
, The signal charges accumulated in the sensors of the sensor rows 2-1 to 2-n are first transferred vertically to sequentially output the signal charges of the N-th sensor row 2-n. The signal charges are accumulated in the registers 1-1 to 1-n, and thereafter, the signal charges are horizontally transferred from the register 1-1 of the first stage and output while the output switching unit 4 switches the output.
Therefore, after the electric charge of the N-th sensor row 2-n is read out to the register 1-n, the electric charge of the register
n, which is greatly affected by noise from the substrate surface. Under the influence of this noise, the output image looks rough, so-called background noise.

The cause of this noise is what is called dark output. Even in a state where light is blocked, electric charges are accumulated in a semiconductor element over time. The charge accumulated in this way regardless of light is called dark output. In most cases, the dark output is caused by electrons and holes that are thermally excited in the depletion layer of the pn junction. Since the influence of noise due to dark output is related to the accumulation time of signal charges, the conventional two-dimensional CCD solid-state imaging device as shown in FIG. Have difficulty. In addition, the effect increases as the ambient temperature increases.

[0006]

As described above, in the conventional two-dimensional CCD solid-state imaging device, there is a difference in the time required to read the signal charges stored under the register for each pixel, and therefore, the data is held for a long time. There is a problem that the signal charge is more affected by noise from the substrate surface and the dark output is larger. It is an object of the present invention to solve this problem and to realize an image pickup device having a relatively simple configuration and having a small influence of the dark output on the signal charge even when the signal charge is held for a long time.

[0007]

In order to achieve the above object, the present invention comprises light receiving means for performing photoelectric conversion, and register means comprising a CCD for transferring signal charges generated by the light receiving means. In the solid-state imaging device, provided for each of the light receiving means, has the same configuration as the light receiving means, and temporarily holds signal charges generated by the light receiving means, which are shielded from external light, until transfer. It is characterized by comprising charge storage means.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a CCD solid-state imaging device according to the present invention will be described in detail with reference to the accompanying drawings. FIG.
FIG. 1 is a schematic plan view showing a configuration of an embodiment of a CCD solid-state imaging device according to the present invention. In FIG.
Symbol 1-n is a CCD register, symbols 2-1 to 2-n
Denotes a sensor array, reference numerals 3-1 to 3-n denote sensor arrays for accumulation, and reference numeral 4 denotes an output switching circuit.

In this embodiment, each of the sensor rows 2-1 to 2
The light-shielded storage sensor arrays 3-1 to 3-n are arranged between the -n and the CCD registers 1-1 to 1-n.
When reading out the signal charges, each of the sensor rows 2-1 to 2
-N signal charges are simultaneously stored in the sensor rows 3-1 to 3-
n. Since the accumulation sensor rows 3-1 to 3-n are shielded from light, the signal charge does not increase here. Further, as described later, since the substrate surface in this portion is P-type, Of dark output noise
It is extremely small compared to the register section.

In this embodiment, the first-stage sensor row 2-
When the signal charges are sequentially output from 1 to the N-th sensor row 2-n, the signal charges of the sensor rows at the respective stages are stored in the storage sensor rows 3-1 to 3-n until the order comes. Yes,
When the order comes, CC from the accumulation sensor row 3-1 to 3-n
After being read out by the D registers 1-1 to 1-n, they are sequentially transferred and output on the CCD registers 1-1 to 1-n.

FIG. 2A shows a two-dimensional CCD of the present embodiment.
FIG. 2B is a schematic cross-sectional view of a sensor unit and a register unit of the solid-state imaging device, and FIG. 2B shows a corresponding potential level diagram. In FIG. 2, reference numeral 11 denotes a photoelectric conversion sensor, reference numeral 12 denotes a storage sensor, reference numeral 13 denotes a CCD register, reference numeral 14 denotes a first readout gate electrode, reference numeral 15 denotes a second readout gate electrode, and reference numeral 16 denotes a transfer electrode. , Symbol 17
Is a register gate electrode, and reference numerals 18 and 21 are p
Reference numerals 19 and 22 denote n layers, reference numerals 20 and 23 denote n-embedded channels, reference numeral 24 denotes an n-embedded channel, reference numeral 25 denotes a p-type impurity layer (p-well),
Reference numeral 26 denotes an n-type semiconductor substrate (n-sub).

FIG. 3 shows the first read gate electrode 14.
, A signal φROG1 applied to the second read gate electrode 15, and a signal φ1 applied to the transfer electrode 16 and the register gate electrode 17 are shown in the timing chart.

The photoelectric conversion sensor 11 has a pnp structure (1
8, 19, and 25), converts a received optical signal into an electron at the time of light reception, and converts a signal charge photoelectrically converted according to light intensity and accumulation time into a pn junction (1).
9, 25). Photoelectric conversion sensor 11
, There is a first read gate electrode 14.
When the light reception by the photoelectric conversion sensor 11 is terminated, the signal φRO applied to the first readout gate electrode 14
The voltage of G1 is simultaneously increased in each pixel (t1 in FIG. 3).
As a result, the potential well below the first readout gate electrode 14 becomes deep, and the signal charge is reduced to the pn junction (19, 2).
5) and transferred to the n- buried channel 20 under the first read gate electrode 14.

Further adjacent to the first readout gate electrode 14, a storage sensor 12 includes a light-shielding film (not shown) and a pn.
There is a p-structure (21, 22, 25). The potential of the pn junction (22, 25) of the accumulation sensor 12 is equal to the potential of the pn junction (18, 1, 1) of the photoelectric conversion sensor 11.
It is deeper than the potential of 9). For this reason,
When the signal φROG1 changes and the voltage of the first readout gate electrode 15 decreases again, the potential under the first readout gate electrode 14 increases, and the signal charge is reduced to the pn junction (22, 25) of the storage sensor 12 having a lower potential. ), And is stored and held here.

The pnp structures of the photoelectric conversion sensor 11 and the storage sensor 12 (18, 19, 25) and (21,
22, 25) indicate that p-type
A layer is provided, and it is considered that holes are always present in the p layer. As a result, the influence of floating charges on the surface is shielded by the hole layer, and the effect of noise on the stored signal charges is greatly reduced even if the storage is performed for a long time. Furthermore, the capacitances of the photodiodes of the photoelectric conversion sensor 11 and the storage sensor 12 can be increased.

When transferring the signal charge stored in the storage sensor 12, first, the voltage of the signal ROG2 applied to the second read gate electrode 15 is increased (t in FIG. 3).
2). As a result, a potential well is created below the second read gate electrode 15, and the second read gate electrode 15
The signal charge is transferred under the n-buried channel 23 below. When the drive signal φ1 applied to the transfer electrode 16 and the register gate electrode 17 is further increased, a potential well is formed below the transfer electrode 16 and the register gate electrode 17.
As shown in FIG. 2B, the potential well under the second read gate electrode 15 and the transfer electrode 16 at the time of applying a voltage by a method such as changing the thickness of the insulating layer below each electrode.
If the depth of the lower potential well and the depth of the potential well below the register gate electrode 17 are given a gradient in advance, signal charges can be finally transferred below the n-buried channel 24 in the register section. In the register section, a CCD register is formed in a direction perpendicular to the plane of FIG. 2A. The electrodes are alternately arranged in this direction. For example, in the case of two-phase driving, the electrodes are transferred by the drive signal φ1 and the drive signal φ2.

As described above, in the present invention, the signal charge read from the photoelectric conversion sensor 11 is sent to the storage sensor 12 under the first read gate electrode 14 and is stored in the storage sensor 12. It will be accumulated for a long time by the sensor 12. Since the surface of the accumulation sensor 12 is p-type and holes are always present, the influence of the dark output from the surface is much smaller than that of the CCD register. After the sensor output signal charges up to the (N-1) th stage are sequentially output, the signal charges accumulated in the accumulation sensor 12 at the Nth stage are sent to the CCD register 13 through the second readout gate electrode 15. Are transferred on the CCD register 13 and output.

In the above embodiment, the present invention is applied to the parallel type 2
Although the dimensional CCD solid-state imaging device has been described, it is needless to say that the present invention is not limited to this embodiment, and can be applied to other types of imaging devices.
Also, the transfer method of the CCD register has been described in the case of two-phase drive, but the same can be applied to the case of three-phase drive and four-phase drive.

[0019]

As described above, the first aspect of the present invention comprises a light receiving means for performing photoelectric conversion and a register means comprising a CCD for transferring signal charges generated by the light receiving means. In the solid-state imaging device, for each of the light receiving means, a charge storage means having the same configuration as the light receiving means and temporarily holding signal charges generated by the light receiving means, which is shielded from external light, until transfer is provided. It is characterized by having. As a result, the signal charge can be stored in a position where the influence of the dark output or external noise is relatively small, and an image pickup device that is less affected by the noise even when the signal charge is held for a long time can be realized.

According to a second aspect of the present invention, the light receiving means and the charge storage means have a pnp structure. Thereby, the hole is always present in the p-layer on the surface, the influence of the stray charge on the surface is shielded, and even if the accumulation is performed for a long time, the influence of the noise on the accumulated signal charge is small. Can be realized. Further, the capacities of the light receiving means and the charge storage means can be increased.

According to a third aspect of the present invention, there is provided a signal charge transfer means for transferring a signal charge between the light receiving means and the charge storage means and between the charge storage means and the register means. I do. This makes it possible to transfer the signal charge easily and steadily.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing the configuration of an embodiment of a CCD solid-state imaging device according to the present invention.

FIG. 2 is a schematic cross-sectional view of a sensor section and a register section of the CCD solid-state imaging device according to the embodiment shown in FIG. 1, and a corresponding potential level diagram.

FIG. 3 is a timing chart of signals applied to each electrode of the embodiment shown in FIG.

FIG. 4 is a schematic cross-sectional view of a sensor unit and a register unit of a conventional CCD solid-state imaging device and a corresponding potential level diagram.

FIG. 5 is a schematic plan view showing a configuration of a conventional CCD solid-state imaging device.

[Explanation of symbols]

1-1 to 1-n: CCD register; 2-1 to 2-n: sensor row; 3-1 to 3-n: storage sensor row; 4: output switching circuit; 11: photoelectric conversion sensor; Accumulation sensor, 13: CCD register, 14: first read gate electrode, 15: second read gate electrode, 16: transfer electrode, 17: register gate electrode, 18, 21: p layer, 1
9, 22,... N layers, 20, 23,.
24 ... n buried channel, 25 ... p-type impurity layer, 26
... n-type semiconductor substrate.

Claims (3)

[Claims] 1. A solid-state imaging device comprising: a light receiving means for performing photoelectric conversion; and a register means comprising a CCD for transferring a signal charge generated by the light receiving means, provided for each of the light receiving means. A solid-state imaging device having the same structure as the light receiving means, and further comprising a charge storage means for temporarily holding signal charges generated by the light receiving means, which are shielded from external light, until transfer. 2. The solid-state imaging device according to claim 1, wherein said light receiving means and said charge storage means have a pnp structure. 3. A signal charge transfer means for transferring a signal charge between the light receiving means and the charge storage means and between the charge storage means and the register means, respectively. 3. The solid-state imaging device according to item 1.