JP2000276588A - Cache memory device and processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the cache hit rate and the processing speed of image data by efficiently storing image data being large scale two-dimensional data in a cache. SOLUTION: This device is provided with a cache memory 1 storing a part of data on a main memory, an address conversion circuit 2 which converts a part of an address field used to access the memory 1, a write controlling part 5 which uses a converted address obtained by converting a part of the address field outputted from the circuit 2 and stores a part of data stored in the main memory in the cache memory and a read controlling part 5 that reads data when data designated by an address whose address field outputted from the circuit 2 is converted partially exists on the cache memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cache memory device used for high-speed image processing and a processor having the cache memory device. In particular, in a cache memory device for improving the memory access processing speed of a processor and a processor equipped with the cache memory device, a cache hit rate is improved by efficiently storing image data in a cache, and high-speed image data processing is performed. Related to the technology to realize.

[0002]

2. Description of the Related Art With the advance of processor technology, a special processor called a media processor for performing image processing conventionally performed by a dedicated LSI has appeared. However, in these processors, due to the specialty of image processing, the cache memory technology, which is a major pillar of the conventional high performance technology of the microprocessor, cannot be applied.

[0003] A description will now be given of a conventional technique of using a cache memory in image processing.

FIG. 7 shows image data composed of 1024 × 1024 pixels. One pixel is represented by one byte.

[0005] Like the two-dimensional filter processing, the normal image processing can process the entire image data by dividing it into small two-dimensional data (partitioned data) 110. As shown in FIG. 7, assuming that the entire image data is handled by being divided into 32 × 32 pixel data, the size of the entire image data is 1 Mbyte, and the divided small data (32 × 32 The size of a pixel) is 1 Kbyte.
The segment data 110 is data having high spatial locality.

FIG. 8 is a block diagram showing an example of the configuration of a conventional cache memory device of 16 Kbytes (line size 16 bytes × 1024 lines). Address 10
It is assumed that 0 is represented by 32 bits. When accessing the cache memory, the entry number of the line is specified by the middle 10 bits of the address 100, that is, [13... 4], tag data as data discrimination information is read from the tag unit 11 to the multiplier 13, and Data is read from the unit 12 to the selector 14.

Next, the upper 18 bits of the address 100,
That is, the multiplier 13 compares [31... 14] with the read tag data to determine a cache hit or miss. In the case of a hit, the selector 14 selects and outputs the data at a specific offset position among the data of the line read from the data section 12 using the lower 4 bits of the address 100, that is, [3 ... 0].

[0008]

Next, a case where the cache memory device shown in FIG. 8 is used for processing 1024 × 1024 pixel image data shown in FIG. 7 will be described. The memory address of each pixel of the entire image data is allocated as shown in FIG. That is, the address is sequentially assigned to each pixel in the X direction, and when the assignment is completed to 1024 pixels for one row, the process proceeds to the next row, and the addresses successive to the pixels on the second row and thereafter are assigned sequentially. For this reason, 32 × shown by hatching in FIG.
When processing 1K-byte partitioned data 110 composed of 32 pixels as one processing unit, 3K of the same row in the partitioned data
Two pixels have consecutive addresses, but if the rows are different, 1
The address of 024 bytes is skipped and discontinuous.

FIG. 10 is a view showing a certain division data 110 (3) in the whole image data to which an address is given as shown in FIG.
4 shows a memory map on the cache memory when (2 × 32 pixels) is stored in the cache memory. As shown in FIG. 9, discontinuous addresses are assigned to the end data of one row of the section data and the start data of the next row. For this reason, as shown by the hatched portion in FIG.
The line (32 bytes) is stored in two consecutive lines in the cache, but the next line (32 bytes) of the partitioned data is stored from the address skipped by 62 lines in the cache. Become. That is, as shown in FIG. 10, when storing one piece of partitioned data, fragmentation occurs in the cache memory.

For this reason, although the size of one section data is smaller than the cache memory size, for example, 1 Kbyte, it is not possible to store all the section data with high locality in the cache memory device. That is,
One of the 1K byte partitioned data (for 32 lines) consisting of 32 × 32 pixels is stored in the 16K byte cache memory device.
Only 6 lines can be stored. Every time new pixel data belonging to the partition data of the remaining rows that cannot be stored is fetched, it is necessary to evict old data from the cache memory device. As a result, there is a problem that the cache memory device cannot be used efficiently, the original effect of using the cache memory device cannot be enjoyed, and the processing efficiency decreases.

Further, the problem of fragmentation of the partitioned data in the cache memory is such that even if a cache memory device having a size larger than 16 Kbytes is prepared, the 1K-byte partitioned data (32 ×
In many cases, it is not possible to hold the entirety of (32 pixels), so it is not a problem that can be solved simply by increasing the size of the cache memory. Such problems generally occur when handling large-scale two-dimensional data such as image processing.
Media processor and DSP (Digital Signal Processor)
In r), this is a major reason why cache technology is not used.

The present invention has been made to solve the above-mentioned conventional problems. An object of the present invention is to provide a cache memory device capable of improving the cache hit rate and improving the processing speed of image data by efficiently storing image data as large-scale two-dimensional data in a cache. An object of the present invention is to provide a processor equipped with this cache memory device.

[0013]

A feature of the present invention for achieving the above object is that an address field is converted so that addresses of divided data as processing units become continuous addresses in a cache memory. . This eliminates fragmentation of the partitioned data in the cache memory and realizes efficient storage of the partitioned data.

According to a first feature of the present invention, a part of data stored in a main memory is stored in a cache memory, and when data requested to be accessed exists in the cache memory, the data is stored in the cache memory. A cache memory device that outputs from a cache memory, a cache memory that stores a part of data in a main memory, an address translation circuit that translates a part of an address field used to access the cache memory, A write control unit that outputs a part of the data stored in the main memory in the cache memory using a converted address obtained by converting a part of the address field, which is output by an address conversion circuit,
A read control unit that reads out the data from the cache memory when data specified by an address obtained by converting a part of the address field and output by the address conversion circuit exists in the cache memory; The present invention provides a cache memory device characterized by the following.

According to a second feature of the present invention, the address conversion circuit converts one piece of data, which is a processing unit, into pieces of partitioned data having continuous addresses so that the pieces of data become continuous in the cache memory. , A part of the address field is replaced.

A third feature of the present invention is that the cache memory device further comprises a replacement amount control unit for controlling a replacement amount of a part of the address field to be replaced by the address conversion circuit.

A fourth feature of the present invention resides in that the replacement amount control unit sets the replacement amount using a ratio of the pixels of the divided data and the image data including the divided data per line. is there.

A fifth feature of the present invention is that the address conversion circuit is constituted by a rotation circuit for shifting a part of a bit field of an address field and adding the shifted bit field part before the bit field. It is in a point.

A sixth feature of the present invention is that the address conversion circuit comprises a selector circuit for replacing a part of the address field by a preset replacement amount.

A seventh feature of the present invention is that the address conversion circuit does not replace the cache address field when the replacement amount set by the replacement amount control unit is 0.

An eighth feature of the present invention resides in that the address conversion circuit converts a part of the address field by swapping some different bits of the address field.

According to a ninth feature of the present invention, a part of data stored in a main memory is stored in a cache memory, and when data requested to be accessed exists in the cache memory, the data is stored in the cache memory. A processor for reading and processing data from a high-speed memory, comprising: a main memory for storing data; a cache memory device for storing a part of data stored in the main memory; and desired data stored in the cache memory device. A central processing unit that reads the data from the cache memory and processes the data, wherein the cache memory device accesses the cache memory that stores a part of the data on the main memory; Address translation circuit that translates part of the address field used to A write control unit that stores a part of the data stored in the main memory in the cache memory by using a converted address obtained by converting a part of the address field, which is output by the address conversion circuit. And a read control unit that reads out the data from the cache memory when data specified by an address obtained by converting a part of an address field and output by the address conversion circuit is present in the cache memory. Another object of the present invention is to provide a processor characterized by:

A tenth feature of the present invention is that the address conversion circuit converts one piece of data, which is a processing unit, into piece data having continuous addresses so that the piece of data becomes continuous in the cache memory. , A part of the address field is replaced.

An eleventh feature of the present invention is that the cache memory device further includes a replacement amount control unit for controlling a replacement amount of a part of the address field to be replaced by the address conversion circuit.

A twelfth feature of the present invention resides in that the replacement amount control unit sets the replacement amount using a ratio of the divided data per line to the pixels of the image data including the divided data. is there.

A thirteenth feature of the present invention is that the address conversion circuit is constituted by a rotation circuit for shifting a part of a bit field of an address field and adding the shifted bit field part before the bit field. It is in a point.

A fourteenth feature of the present invention resides in that the address conversion circuit comprises a selector that replaces a part of the address field by a preset replacement amount.

A fifteenth feature of the present invention resides in that the address conversion circuit does not replace the cache address field when the replacement amount set by the replacement amount control unit is 0.

A sixteenth feature of the present invention resides in that the address conversion circuit converts a part of the address field by swapping some different bits of the address field.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
An embodiment of a cache memory device used for high-speed image processing according to the present invention and a processor equipped with the cache memory device will be described in detail.

First Embodiment Hereinafter, an embodiment of a cache memory device according to a first embodiment of the present invention and a processor equipped with the cache memory device will be described in detail with reference to FIGS. . In the first embodiment,
A function is provided for converting the address of the section data as a processing unit in the image data so that the section data is stored continuously in the cache memory.

FIG. 1 is a block diagram showing the configuration of the cache memory device according to the first embodiment of the present invention. The cache memory device according to the first embodiment includes a cache memory 1 that stores a part of data stored in a main memory (not shown) and a part of a bit field of an address 100 input to the cache memory 1. An address field replacement circuit 2 for switching, a mode control register 3 for controlling the address field replacement circuit 2, and a cache access circuit 4 are provided. The capacity of the cache memory 1 is, for example, 16 Kbytes.
Note that the cache memory 1 can be a direct map cache memory configured by, for example, a direct map method.

FIG. 2A shows an example of the layout of the address field 100 described above. FIG. 2 (a)
In the layout shown in FIG. 7, the bit positions of the address field that change when accessing the above-described partitioned image data of 32 × 32 pixel data are indicated by oblique lines. In order to access 32 bytes (32 pixels) in each pixel row of the division data, different pixel rows (32 rows) in the division data are designated using the lower 5 bits of the address [4 ... 0] (2 ⁵ = 32 bits). Therefore, 5 bits (2 ⁵ = 32 bits) of the address [14... 10] indicated by A are used. On the other hand, the address [9 ... 5] indicated by B is a bit necessary to access another section data of the same pixel row in the whole image data, and is accessing the section data currently being processed. As long as it does not change.

Next, the operation of the first embodiment will be described.

In the first embodiment, for the sake of explanation, for example, image data of 1024.times.1024 pixels are handled, and the entire image data is divided into small two-dimensional data of 32.times.32 pixel data. . However, one pixel is represented by one byte. Therefore, the size of the image data in the main memory is 1 Mbyte, and the size of the divided data 110 (32 × 32 pixels) divided in this image data is 1 Kbyte.

First, the address 100 given to the cache memory device is the address map area replacement circuit 2
Is input to In the address field replacement circuit 2, a part of the bit field of the address 100 is replaced and applied to the direct map cache memory 1.

The direct map cache memory 1
Since it is a 16K byte direct map, address 10
Even if the bit field [14] of 0 has a different address, if the other bits up to [13 ... 0] are the same,
Maps to the same entry in the cache memory.
For this reason, as described above, when the address 100 shown in FIG. 2A is directly given to the direct map cache memory, the addressed partitioned data 110 is fragmented in the direct map cache memory 1, and
3 bytes in the K-byte direct map cache memory 1
Only half of the 1 Kbyte data of 2 × 32 pixels can be stored.

On the other hand, the cache memory device of the first embodiment has a normal direct map cache memory 1.
Field replacement circuit 2 on the address input side of
Is added. The address field replacement circuit 2 replaces the bit positions of the portions indicated by the bit fields B and A of the address field 100 shown in FIG. 2A, and converts the bit fields shown in FIG. It is converted into an address field 101. That is, one section data 110 (for example, 32
The converted address field 101 is configured so that bits in the address field required to access (pixel × 32 pixel rows) are continuous.

The replacement is determined by the bit shift amount set in the mode control register 3. For example, in the first embodiment, the bit field B indicated by the address bits [9... 5] is replaced with the bit field A of the address bits [14. A quantity of 5 has been set. The bit shift amount is set according to the size of the section data to be stored in the cache memory 1, for example, according to the ratio of the section data 110 and the entire image data per pixel row (pixel row).

As shown in FIG. 2 (a), the address bits in the B section of the address field 100 are 0 as long as a certain piece of data 110 having 32 × 32 pixels is accessed. This 0 portion is used to store the 32 × 32 pixel small section data in the direct map cache memory 1.
This is a reason that data cannot be continuously stored when the data is stored in the direct map cache memory 1 of 16 Kbytes.

In the first embodiment, the address field replacement circuit 2 uses the address field 10
Data is written to and read from the direct cache memory 1 using the address field 101 in which the bit field A and bit field B of 0 are replaced. Since the B part of 0 is higher,
The addresses of the divided data 110 of 32 × 32 pixels are made continuous. Therefore, all the 1K byte 32 × 32 pixel section data 110 can be stored in the direct map cache memory 1.

FIG. 3 shows a state where the partitioned data 110 in the cache memory 1 is stored in the cache memory device according to the first embodiment. It is understood that the divided data is not fragmented and is stored in the cache memory 1 continuously as compared with the conventional cache memory shown in FIG.

Here, the above address conversion will be specifically described using decimal numbers. For example, 1000, 2000,
Suppose there is an address 3000. This is 10
The addresses are skipped by 00, and the addresses are discontinuous. By replacing the bit fields of these addresses, 0001,
By converting the addresses to 0002 and 0003, continuous addresses can be obtained.

Thereafter, when accessing the small section data stored in the direct map cache memory 1, the cache memory device according to the first embodiment uses the address map replacement circuit 2 to store the address field 100.
Is accessed using the address field 101 in which a part of the bit field is replaced, and when a cache hit occurs, the corresponding data is read from the direct map cache memory 1.

FIG. 4 is a block diagram showing an example of a detailed configuration of the address field replacement circuit 2 shown in FIG. The address field replacement circuit 2 according to the first embodiment includes a rotation circuit 21 that shifts the bits of the address 100 to the right according to the bit shift amount supplied from the mode control register 3 and prefixes the shifted bits. ing.

The address field 100 is converted into an address field 101 by the rotation circuit 21 in which the bit field A and the bit field B are replaced. At this time, 5 bits are set in the mode control register 3 as the bit shift amount of the rotation circuit 21 in the case of the above-described 1-Kbyte partitioned data.
In the case of 2K bytes of partitioned data, 6 bits are set. That is, the mode control register 3 controls the shift amount of the address field replacement circuit 2 according to the size of the small section data to be stored in the direct map cache memory 1. By using the mode control register 3 and the rotation circuit 21, the bit shift amount can be variably set according to the size of the divided data and the size of the entire image data.

When the bit shift amount set in the mode control register 3 is 0, the address field 100 passes through the rotation circuit 21 and is not converted at all. The data is stored in the memory 1. For this reason, it is possible to control whether or not to convert addresses used for cache memory access in accordance with the properties and locality of data to be processed. As described above, if the conversion of the address field 100 by the address field replacement circuit 2 is not performed, the address field 1 of the direct map cache memory 1 can be changed.
The data can be stored according to 00, and when handling normal data, the conventional method of using the cache memory can be realized.

In the first embodiment, the address used to access the cache memory is small two-dimensional image data (partition data 1) obtained by dividing two-dimensional image data.
In the case of the address of 10), by replacing a part of the bit field of this address, all the addresses of the divided data can be made continuous. Therefore, by writing the section data into the high-speed memory (cache memory) using the address in which a part of the bit field is replaced, all the section data can be written into the cache memory. In addition, a data read request is issued to the cache memory using the address in which a part of the bit field is replaced, and when the desired data is present in the cache memory, the data is read at a high speed and a large- Also in the case of handling image data, the function as a cache memory can be sufficiently performed, and the speed of image data processing can be increased.

According to the first embodiment, the following effects can be obtained. That is, when large-scale two-dimensional image data is divided into small two-dimensional data (partitioned data 110) and sequentially processed, a part of the bit field of the address field 100 requested to be written to the direct map cache memory 1 To the address field 101 having a continuous bit field. By storing the converted address field 101 in the cache memory 1 using the converted address field 101, it is possible to continuously store the divided data, which is small two-dimensional data, in the direct map cache memory 1. Thereafter, the cache memory device according to the first embodiment makes a smooth readout of the cache hit data from the direct map cache memory 1 by making a read request to the direct map cache memory 1 using the converted address field 101. it can. Therefore, even in image processing for large-scale image data, all of the divided data, which is a processing unit, can be stored in the cache, and the effect of high-speed access by the cache memory can be enjoyed.

Second Embodiment Hereinafter, a second embodiment of a cache memory device according to the present invention and a processor equipped with the cache memory device will be different from the first embodiment with reference to FIGS. Only the points will be described.

FIG. 5 is a block diagram showing a main part of a cache memory device according to the second embodiment of the present invention.

The second embodiment differs from the first embodiment shown in FIGS. 1 and 4 in that the rotation circuit 31 and the mode control register 3 forming the address field replacement circuit 2 are replaced by the selector circuit shown in FIG. 22 is a modification of the first embodiment in that it is replaced by 22. The other configuration of the second embodiment is the same as that of the first embodiment, and the description is omitted.

In the second embodiment, a part of the bit field of the address field 100 is replaced with a part A and a part B shown in FIG. Converting. Since the selector circuit 22 is used, the replacement amount is fixed.

Therefore, for example, when the size of the section data 110 of the image data to be handled is fixed, the replacement amount is fixed, so that even if the selector circuit 22 is used as the address field replacing circuit 2, the first The same effect as that of the embodiment can be obtained. In addition, since the selector circuit 22 has a simple configuration, the cost of the device can be further reduced.

FIG. 6 is a block diagram showing an example of a configuration of a processor equipped with the cache memory device according to the above embodiment. The processor 10 including the cache memory device according to the present invention includes a main memory 50 and a processor chip 60 including the cache memory device 20. The processor chip 60 includes an instruction fetch control circuit 61, an instruction cache 62 for storing fetched instructions, a D stage control circuit 63 for controlling a decode stage of pipeline processing, and an E stage control circuit 64 for controlling an execution stage. , An M stage control circuit 65 for controlling the memory access stage, a W stage control circuit 66 for controlling the write back stage, and a plurality of registers 62R, 63R,..., 72R. The processor chip further includes a register file 67,
Bypass circuit 68, ALU 69, sign extension circuit 70
, An address generation adder 72, and the cache memory device 20. The cache memory device 20 includes an address field replacement circuit 2 (that is, an address conversion circuit) and a data cache 1. The data address output from the address generation adder 72 is used for accessing the main memory, and is input to the address field replacement circuit 2 and converted. Data storage and access to the data cache 1 are executed by the converted address.

[0056]

According to the present invention, by replacing a part of the bit field of the address for accessing the cache memory to make it continuous, the division data as a processing unit is converted into data having a continuous address in the cache. I do. Therefore, even when dealing with large-scale two-dimensional image data, the entire partitioned data can be stored in the cache memory without fragmenting the partitioned data to be stored. Therefore, the cache memory, which is a high-speed memory, can be effectively used, and the image data processing speed of the processor can be greatly improved. By using the cache memory device of the present invention and the processor equipped with the cache memory device, the image data processing speed of the media processor and the DSP is greatly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a cache memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a layout of addresses for accessing the cache memory device shown in FIG. 1;

FIG. 3 is a diagram illustrating a state of storing partitioned data in a cache memory in the cache memory device according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a detailed configuration example of an address map replacement circuit in the cache memory device shown in FIG. 1;

FIG. 5 is a block diagram showing a main part of a cache memory device according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration example of a processor equipped with a cache memory device according to an embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration example of a conventional cache memory.

FIG. 8 is a diagram illustrating a method of dividing large-scale image data stored in a main memory into small-segmented data in order to perform processing using a cache memory.

FIG. 9 is a diagram illustrating an example of address assignment of small section image data in the large-scale image data illustrated in FIG. 7;

FIG. 10 is a diagram illustrating fragmentation on a cache memory according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Direct map cache memory 2 Address field replacement circuit 3 Mode control register 20 Cache memory device 21 Rotate circuit 22 Selector circuit 100 Address field 101 Address field after conversion

Claims (16)

[Claims] 1. A cache memory for storing a part of data stored in a main memory in a cache memory and outputting the data from the cache memory when data requested to be accessed exists in the cache memory. A cache memory that stores a part of data on a main memory; an address conversion circuit that converts a part of an address field used to access the cache memory; and an output from the address conversion circuit. A write control unit that stores a part of the data stored in the main memory in the cache memory using the converted address obtained by converting a part of the address field, and is output by the address conversion circuit. , Part of the address field is If the data to be constant is on the cache memory, the cache memory apparatus characterized by comprising a read control unit for reading the data from the cache memory. 2. The method according to claim 1, wherein the address conversion circuit converts one piece of data, which is a processing unit, into a piece of data having a continuous address so as to be continuous in the cache memory. 2. The cache memory device according to claim 1, wherein 3. The cache memory device according to claim 1, further comprising a replacement amount control unit that controls a replacement amount of a part of the address field replaced by the address conversion circuit. Cache memory device. 4. The replacement amount control unit according to claim 3, wherein the replacement amount control unit sets the replacement amount using a ratio of pixels of the divided data and image data including the divided data per line. A cache memory device according to claim 1. 5. The address conversion circuit according to claim 1, further comprising a rotation circuit for shifting a part of the bit field of the address field and adding the shifted bit field part before the bit field. Item 5. The cache memory device according to item 1, 2, 3, or 4. 6. The cache memory device according to claim 1, wherein the address conversion circuit includes a selector circuit that replaces a part of the address field by a preset replacement amount. 7. The address conversion circuit, wherein the replacement amount set by the replacement amount control unit is 0.
4. The cache memory device according to claim 3, wherein the replacement of the cache address field is not performed in the case of. 8. The address conversion circuit according to claim 1, wherein said address conversion circuit performs conversion of a part of said address field by swapping some different bits of said address field. ,
8. The cache memory device according to 4, 5, 6, or 7. 9. A part of data stored in a main memory is stored in a cache memory, and when data requested to be accessed exists in the cache memory, the data is read from the high-speed memory and processed. A processor, a main memory for storing data, a cache memory device for storing a part of the data stored in the main memory, and, when desired data is stored in the cache memory device, A central processing unit for reading and processing the data from a cache memory, the cache memory device comprising: a cache memory for storing a part of data on a main memory; and an address field used for accessing the cache memory. An address conversion circuit for partially converting the address; A write control unit that stores a part of the data stored in the main memory in the cache memory using a converted address obtained by converting a part of the address field, which is output by a conversion circuit; and A read control unit that reads out the data from the cache memory when data specified by an address obtained by converting a part of the address field and output by the conversion circuit is present in the cache memory. And processor. 10. The address conversion circuit according to claim 1, wherein one of the divisional data, which is a processing unit, is converted into divisional data having a continuous address, so that the division is made continuous in the cache memory. 10. The processor of claim 9, wherein 11. The cache memory device according to claim 9, further comprising a replacement amount control unit that controls a replacement amount of a part of the address field to be replaced by the address conversion circuit. Processor. 12. The method according to claim 11, wherein the replacement amount control unit sets the replacement amount using a ratio of pixels of the divided data and image data including the divided data per line. Processor as described. 13. The address conversion circuit according to claim 1, further comprising a rotation circuit for shifting a part of the bit field of the address field and adding the shifted bit field part before the bit field. Item 13. The processor according to item 9, 10, 11 or 12. 14. The processor according to claim 9, wherein the address conversion circuit includes a selector that replaces a part of the address field by a preset replacement amount. 15. The address conversion circuit, wherein the replacement amount set by the replacement amount control unit is 0.
12. The processor according to claim 11, wherein the cache address field is not replaced when. 16. The address conversion circuit according to claim 9, wherein said address conversion circuit performs conversion of a part of said address field by swapping some different bits of said address field.
16. The processor according to 1, 12, 13, 14 or 15.