JP2000272996A - Silicon wafer and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To produce a silicon single crystal wafer suitable for annealing, by adjusting the concentration of oxygen dissolved in a single crystal ingot pulled from a silicon melt by CZ method and further adjusting a rate for cooling the pulled ingot in a defect-forming temperature zone, thus controlling the connected or non-connected states of voids present in the cooled ingot. SOLUTION: Conditions for generating the forms of plural voids to obtain a silicon wafer giving a high annealing effect are expressed by the formulas, wherein Co is the concentration (atoms/cc) of oxygen; Coeq is an equilibrium concentration of oxygen, for example, 5.4×1017 (atoms/cc) at the time of 1,100 deg.C; and R is a cooling rate ( deg.C/min) in the defect-forming temperature zone. R is preferably >=2 on a law learned by experience. R is preferably >=4 in order to obtain a high annealing effect, even when void-like defects are present in the form of single voids.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a silicon single crystal ingot and a silicon wafer manufactured by the Czochralski method (CZ method) and a method of manufacturing the same, particularly a silicon wafer suitable for annealing and a method of manufacturing the same. .

[0002]

2. Description of the Related Art Voids are introduced into a silicon single crystal produced by a CZ method from a solid-liquid interface during crystal growth. The vacancies in the crystal become supersaturated as the crystal cools, but they precipitate in the crystal and form void-like defects in the CZ silicon ingot. This void-like defect is one in which octahedral voids exist alone or are aggregated, and if these voids exist near the wafer surface layer, they adversely affect the leak characteristics and the like. In addition, the gate oxide film breakdown voltage characteristic which is one of the device characteristics is deteriorated.

As described above, void-like defects generated during crystal growth adversely affect the reliability of a gate oxide film of a MOS device, PN junction leak characteristics, and the like. It needs to be extinguished. For this reason, at present, a silicon wafer is subjected to a hydrogen annealing treatment to eliminate void-like defects and oxygen precipitates in the surface layer portion (Japanese Patent Laid-Open No. 61-193456).

[0004]

Here, in hydrogen annealing or argon annealing, it is known that the smaller the size of a void-like defect is, the more easily it disappears and the larger the defect-free region is. However, in order to perform an appropriate annealing process, it is sometimes insufficient to reduce the defect size.

The present invention has been made in view of the above-mentioned problems, and has as its object to provide a method suitable for producing a silicon single crystal wafer suitable for annealing,
An object of the present invention is to provide a new method other than the reduction of the defect size or a new method that can coexist well with the reduction of the defect size.

[0006]

Means for Solving the Problems To solve the above problems, the present invention controls the concentration of dissolved oxygen in a silicon single crystal ingot pulled up from a silicon melt by the CZ method, and By controlling the cooling rate of the growing silicon single crystal ingot in the growth defect forming temperature region, void-like defects are formed in a state where a plurality of voids are connected, thereby improving the suitability as a silicon single crystal wafer for annealing. I have to do that.

According to the present invention, a void-like defect is formed in a state where a plurality of voids are connected, and a new crystal growth condition for realizing the void-like defect is presented.

[0008] More specifically, the present invention provides a method and a wafer as described below.

(1) The concentration of dissolved oxygen in the silicon single crystal ingot pulled up from the silicon melt by the Czochralski method (CZ method) is adjusted, and the temperature of the silicon single crystal ingot during the pulling is adjusted to the defect formation temperature range. A method of controlling the connection / non-connection state of voids present in a cooled silicon single crystal ingot by adjusting a cooling rate.

(2) The concentration of dissolved oxygen in the silicon single crystal ingot pulled up from the silicon melt by the Czochralski method (CZ method) is increased, or the defect forming temperature of the silicon single crystal ingot being pulled up. A method of promoting the formation of void-like defects existing in a cooled silicon single crystal ingot in a state where a plurality of voids are connected by slowing a cooling rate in a band.

(3) A method of pulling a silicon single crystal ingot from a silicon melt by controlling the Czochralski method (CZ method) within a range satisfying the following equation.

[0012]

(Equation 3)

(4) A method of improving the suitability as a silicon single crystal wafer for annealing by increasing the ratio of void-like defects in a state where a plurality of voids are connected.

(5) An annealing silicon single crystal wafer in which the ratio of void-like defects in a state where a plurality of voids are connected is increased.

(6) By pulling a silicon single crystal ingot out of a silicon melt by controlling the Czochralski method (CZ method) within a range satisfying the following equation,
A method of increasing the ratio of void-like defects in a state where a plurality of voids are connected in a cooled silicon single crystal ingot.

[0016]

(Equation 4)

[Definition of terms and the like] In this specification,
“Ingot” means a single crystal grown from a silicon melt, and is cut from the ingot to produce a “wafer”.

The term "void-like defect" refers to a case where a single void exists in a crystal to constitute a crystal defect, and a case where a plurality of voids exist in the crystal to constitute a crystal defect. This is a concept that includes both cases where Regarding the “void-like defect”, whether it is contained in the ingot or in the wafer, it is not necessary to treat them separately in the present invention. So, in any case, simply "void defects"
It is not distinguished in terms of expression.

The term “defect formation temperature zone” particularly relates to the formation of a grown-in defect (grown-in defect) in an ingot, particularly a void-like defect, in which an axial temperature gradient (° C./mm) exists. Temperature range near 1120 ° C. (approximately 1080 ° C. to 115 ° C.) of the pulled silicon single crystal ingot.
0 ° C. temperature range).

As described above, the void is formed of an octahedral cavity. And the void-like defect is
As shown in FIG. 2 (A), a single void exists in a silicon single crystal, and as shown in FIG. 2 (B), a plurality of voids are connected to each other in a silicon single crystal. 2 (for example, in FIG. 2B, two void-like defects α and β are connected to each other). Is promoted, and void-like defects can be formed in a state where a plurality of voids are connected.
As will be demonstrated in a later example, void-shaped defects composed of a plurality of voids are more easily eliminated by annealing than void-shaped defects composed of a single void. The silicon single crystal thus obtained has improved suitability as a silicon single crystal wafer for annealing.

The dissolved oxygen concentration in the silicon single crystal ingot is adjusted by changing the rotation speed of the silicon single crystal ingot being pulled or the rotation speed of the crucible, adjusting the furnace pressure, and controlling the inert gas passed through the furnace. It can be performed by adjusting the flow rate, changing the structure of the hot zone, and the like.

Further, the cooling rate in the defect forming temperature zone of the silicon single crystal ingot being pulled is adjusted by changing the pulling rate of the silicon single crystal ingot being pulled and by heat for shielding radiant heat from the silicon melt. Changing the shape and the like of a shield (for example, Japanese Patent Application No. 10-330713), a cooler installed in a furnace (for example, JP-A-63-256593, Patent No. 2562245)
No.) can be performed by adjusting the temperature.

[0023]

EXAMPLE A wafer having substantially the same defect density and size before hydrogen heat treatment was subjected to hydrogen heat treatment and then polished to 3 μm to test the effect of eliminating defects in the depth direction. Table 1 shows the results.

[0024]

[Table 1]

From Table 1, it can be seen that the oxide film withstand voltage decreases when polishing is performed when the void-like defect is composed of a single void, but the withstand voltage decreases almost after polishing when a plurality of voids are formed. (That is, the effect of the hydrogen heat treatment appears deeper, and the crystal is advantageous for increasing the defect-free region) (4 to 6 steps in Table 1, after 3 μm polishing). Also, the oxide film breakdown voltage non-defective rate exceeds 90% in all cases). From this fact, it can also be seen that when the same hydrogen heat treatment (hydrogen annealing treatment) is performed, void-shaped defects having a plurality of voids are more likely to disappear than void-shaped defects having a single void.

Here, Table 2 shows the test results when the cooling rate was higher than in the case of Table 1.

[0027]

[Table 2]

From Table 2, when the cooling rate is high,
It can be seen that the effect of annealing is high (that is, the void-like defect is formed of a single void) (that is, the void-like defect is easily eliminated by the annealing treatment), and a sufficient defect free zone can be formed. Therefore, in order to find a boundary speed that is effective even when the void-like defect is formed of a single void, a test was performed by changing the cooling rate as shown in Table 3.

[0029]

[Table 3]

From Table 3, it is recognized that the boundary of the cooling rate at which a high annealing effect can be obtained even when the void-like defect is in the form of a single void is about 4 ° C./min.

FIG. 1 is a plot of the results of Tables 1-3. In FIG. 1, a white circle plot indicates a form of a plurality of voids, and a black circle plot indicates a form of a single void. From FIG. 1, when a function related to a curve (curve indicated by a broken line in FIG. 1) serving as a boundary between a white circle plot and a black circle plot is produced, it is represented by the following equation.

[0032]

(Equation 5)

Therefore, in order to obtain a silicon wafer capable of obtaining a high annealing effect, it is necessary to satisfy the condition of the following expression in order to generate a plurality of voids.

[0034]

(Equation 6)

Next, from the results shown in Table 2, it is understood that when the cooling rate is sufficiently high, a high annealing effect can be obtained even when the void-like defect is in the form of a single void. From this, it is recognized that the cooling rate at the boundary will be about 4 ° C./min. Therefore, even if the void-like defect is in the form of a single void, the condition for obtaining a high annealing effect is “4.0 ≦ R”. Is added to the following equation.

[0036]

(Equation 7)

As a rule of thumb, in order to produce a crystal having a high annealing effect, it is necessary to produce the crystal at a cooling rate of at least 2 ° C./min. When the condition of “2.0 ≦ R” is put,
It becomes like the following formula.

[0038]

(Equation 8)

Therefore, from Equations (7) and (8), if the void-like defect has a single void form, regardless of whether it has a plurality of void forms, it is necessary to produce a crystal having a high annealing effect. It is necessary to satisfy the condition of the following equation (the range on the right side of the thick line in FIG. 1).

[0040]

(Equation 9)

In summary, the broken line and the solid line in FIG. 1 indicate a portion. In FIG. 1, a portion above the broken line is a region where a void-like defect formed by connecting a plurality of voids is formed. This means that the lower part is a region where a void-like defect composed of a single void is formed. Therefore, considering at least the rule of thumb of 2 ° C./min or more, the region on the right side of the thick line above the broken line in FIG. 1 is a region where a crystal having a high annealing effect can be manufactured. In addition, the range on the right side of the thick line below the broken line is a region where a crystal having a high annealing effect can be manufactured even in the case of a single void, and in any case, the effect of the oxygen concentration is taken into consideration. The crystal is manufactured in the range on the right side of the bold line 1 (the range of the above “Equation 9”) (that is, the defect formation temperature range (110
By controlling the cooling rate (at around 0 ° C.) and the oxygen concentration under the conditions above the broken line), a crystal having a high annealing effect can be manufactured.

[0042]

As described above, according to the present invention,
The form of the void-like defect can be constituted by a form in which a plurality of voids are connected. By doing so, when performing annealing with hydrogen, argon, or the like, a higher effect can be obtained.
It is possible to manufacture a crystal that can easily enlarge the defect-free region.

[Brief description of the drawings]

FIG. 1 is a diagram showing a graph in which the existence form of a void-like defect is plotted with respect to a cooling rate and an oxygen concentration in a defect formation temperature zone.

2A and 2B are diagrams for explaining the form of a void defect, and FIG. 2A is a diagram showing a state in which a single void directly forms a void defect, and FIG. FIG. 4 is a diagram showing a state in which a plurality of voids are connected to form a void defect.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Kozo Nakamura 2612 Yonomiya, Hiratsuka-shi, Kanagawa F-term in Komatsu Electronic Metals Co., Ltd. 4G077 AA02 AB01 BA04 CF10 EG17 EH07 EH09 FE05 HA12 5F053 AA12 AA13 BB08 DD01 FF04 GG01 PP03 PP05 RR03

Claims (6)

[Claims] 1. A method for adjusting the concentration of dissolved oxygen in a silicon single crystal ingot pulled up from a silicon melt by a Czochralski method (CZ method) and cooling the silicon single crystal ingot during the pulling in a defect formation temperature zone. A method for controlling the connection / non-connection state of voids existing in a cooled silicon single crystal ingot by adjusting the speed. 2. A method for increasing the concentration of dissolved oxygen in a silicon single crystal ingot pulled up from a silicon melt by the Czochralski method (CZ method), or a temperature range for forming defects in a silicon single crystal ingot being pulled up. A method of accelerating the formation of void-like defects existing in the cooled silicon single crystal ingot in a state where a plurality of voids are connected by slowing down the cooling rate in the method. 3. A method of pulling a silicon single crystal ingot from a silicon melt by controlling the Czochralski method (CZ method) within a range satisfying the following equation. (Equation 1) 4. A method for improving suitability as a silicon single crystal wafer for annealing by increasing the ratio of void-like defects in a state where a plurality of voids are connected. 5. An annealing silicon single crystal wafer in which the ratio of void-like defects in a state where a plurality of voids are connected is increased. 6. By pulling up a silicon single crystal ingot from a silicon melt by controlling it by a Czochralski method (CZ method) within a range satisfying the following equation, a plurality of silicon single crystal ingots are cooled. A method of increasing the ratio of void-like defects in a state where voids are connected. (Equation 2)