JP2000269783A - Fet balun circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a device having an FET balun circuit small in size by providing the FET balun circuit using only a positive power source. SOLUTION: The voltage of a positive power supply 5 in an FET balun circuit is divided by a ratio of the resistance of two voltage division resistors 13, 14. The gate of a 1st FET 1 is biased by a positive voltage via a resistor 15, resulting from the resistance division. A gate of a 2nd FET 2 is connected to ground via an AC grounding capacitor 11 and receives a positive voltage as a bias voltage by the resistance division via a resistor 16. Thus, it is not required to set a negative level to a gate and a source of a 3rd FET 7, the gate is connected to ground and the source is connected to ground via a bias resistor 12. Thus, a negative power supply for the 3rd FET is not required, and by using only the positive power supply 5, a single-phase signal received by an input terminal 6 is converted into differential signals at two output terminals 9, 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an FET balun circuit.

[0002]

2. Description of the Related Art In recent years, communication systems of higher frequencies and wider bands have been promoted for the purpose of increasing the capacity of communication.
In order to realize higher frequency and wider bandwidth of this communication system,
A balun circuit is required to convert a single-phase signal into a differential signal composed of two signals having a phase difference of 180 ° from each other. Generally, a high frequency circuit uses a passive balun circuit composed of a combination of coils. In addition, due to demands for a wider band and higher integration of signals, a field effect transistor (hereinafter referred to as FET) is currently used. A known FET balun circuit is known. In particular, for signals exceeding 1 GHz called microwaves or quasi-microwaves, the FET balun circuit is an effective circuit from the viewpoint of miniaturization of the device.

Further, in order to realize a high-performance balun circuit, a balun circuit using a gallium arsenide (GaAs) Schottky gate field effect transistor (MESFET) having a low current consumption and excellent high frequency characteristics and low distortion characteristics. Is widely used.

Hereinafter, a conventional FET balun circuit will be described with reference to FIG.

FIG. 6 shows a conventional FET balun circuit.
The balun circuit of FIG. 1 has three FETs 31, 32, and 33. The drains of the first FET 31 and the second FET 32 are connected to a positive power supply 36 via a load resistor 34 and a load resistor 35, respectively.

The gate of the first FET 31 is connected to the input terminal 37.
, And the gate of the second FET 32 is grounded. Further, the sources of the first FET 31 and the second FET 32 are connected to the drain of the third FET 33, respectively. The third FET 33 operates as a constant current source. The source of the third FET 33 is connected to a negative power source VSS of, for example, -1 V via a bias resistor 38, and the third F
The gate of ET33 is directly connected to the negative power supply VSS. The drain of the first FET 31 is connected to the first output terminal 39, and the drain of the second FET 32 is connected to the second output terminal 39.
Is connected to the output terminal 40.

Here, the reason why the gate and source of the third FET 33 are connected to the negative power supply VSS will be described. In the MESFET, in order to use a Schottky gate, it is necessary to make the voltage between the gate and the source a negative voltage. This is because when the gate bias of each of the first FET 31 and the second FET 32 is set to, for example, 0 V, the gate and source of the third FET 33 need to be set to less than 0 V.

Next, the operation of the conventional FET balun circuit will be described. A single-phase RF signal is input to the input terminal 37. In this case, the current flowing through the first FET 31 changes, but the current flowing through the load resistor 34 and the current flowing through the load resistor 34 are fixed because the gate of the second FET 32 is grounded and the current flowing through the third FET 33 is constant. The potential of the drain of the third FET 33 changes without changing the total current value with the current flowing through 35.

Therefore, as long as the single-phase signal input to the input terminal 37 is in the linear region of the first FET 31, the drain voltage of the third FET 33 will be equal to the first FET 3
As a result, the first output terminal 39 and the second output terminal 40 output signals whose phases are inverted from each other.

[0010]

However, in the conventional FET balun circuit, since the gate and the source of the third FET 33 need to be set to a negative potential, respectively, the first FET 31 and the second FET 32 A negative power supply VSS is required in addition to the positive power supply 36 that supplies a positive potential to the drains. The provision of the negative power supply VSS makes the device complicated and large, and is not suitable for IC circuits.

An object of the present invention is to provide an F-type power supply using only a positive power supply.
An object of the present invention is to provide an ET balun circuit and thereby reduce the size of a device having the FET balun circuit.

[0012]

In order to achieve the above object, according to the present invention, there is provided a second FE in which the gate is conventionally grounded.
At T, a configuration is adopted in which a positive bias voltage is applied to the gate of the third FET, whereby each of the gate voltage and the source voltage of the third FET can be a positive voltage.

That is, the FET balun circuit of the present invention converts a single-phase signal input to an input terminal into a differential signal and outputs the differential signal from the first and second output terminals. An FET balun circuit, wherein a drain is connected to a positive power supply and the first output terminal and a gate is connected to the input terminal, and a drain is connected to the positive power supply and the second output terminal. A connected second FET, an AC grounding capacitor having one end connected to the gate of the second FET and the other end grounded, and a drain connected to the source of the first FET and the second FET. A third FET connected to the source and having a gate grounded.

According to a second aspect of the present invention, there is provided the FET balun circuit according to the first aspect, further comprising a bias circuit for biasing the gates of the first FET and the second FET to a predetermined positive potential. And

According to a third aspect of the present invention, in the FET balun circuit according to the second aspect, the bias circuit includes two voltage dividing resistors for dividing the voltage of the positive power supply, A first resistor connected to a gate and a connection point of the two voltage-dividing resistors, and a second FET
A second resistor connected between a gate and the AC grounding capacitor and a connection point of the two voltage dividing resistors.

According to a fourth aspect of the present invention, in the FET balun circuit according to the second aspect, at least one of a bias voltage of a gate of the first FET and a bias voltage of a gate of the second FET is adjusted. A bias adjusting circuit is provided.

According to a fifth aspect of the present invention, in the FET balun circuit according to the fourth aspect, the bias adjustment circuit has one end connected to the positive power supply and the other end connected to the first F.
A resistor connected to the gate of the ET;
A variable resistor connected to the gate of the ET and having the other end grounded.

According to a sixth aspect of the present invention, in the FET balun circuit according to the first, second, or fifth aspect,
The frequency of the single-phase signal input to the input terminal, which is arranged between the first output terminal and the second output terminal, is 2
A series resonance circuit that performs series resonance at twice the frequency is provided.

According to a seventh aspect of the present invention, in the FET balun circuit according to the sixth aspect, the series resonance circuit includes a resonance coil, a resonance capacitor, and a resonance resistor connected in series. It is characterized by that.

According to an eighth aspect of the present invention, in the FET balun circuit according to the first, second, third, fourth, fifth, sixth or seventh aspect, the AC
The grounding capacitor has a capacitive insulating film, and the capacitive insulating film is formed of a high dielectric film. The AC grounding capacitor, the first FET, the second FET, and the third FET are It is characterized by being integrated on the same substrate.

As described above, in the FET balun circuit according to the first to eighth aspects of the present invention, since the AC grounding capacitor is arranged at the gate of the second FET, the gates of both the first and second FETs are connected. Each is biased to a positive potential. Therefore, it is not necessary to set the gate and the source of the third FET to a negative potential, and a negative power supply is not required.
The ET balun circuit is downsized.

In particular, in the invention according to claim 4, the first F
Even when a phase error occurs between output signals obtained at the first and second output terminals due to distortion or characteristic variation of harmonics generated in the ET or the second FET, the bias adjustment circuit can control the phase error. By absorbing the distortion of harmonics and the variation in characteristics, the phase error between the output signals can be reduced or minimized.

According to the sixth aspect of the present invention, the impedance between the first and second output terminals is reduced by the series resonance circuit at twice the frequency of the single-phase signal input to the input terminal. , The output signals of the first and second output terminals have no second harmonics, and output signals whose phases are accurately inverted with respect to each other are obtained.

Further, in the invention according to claim 8, since the AC grounding capacitor is miniaturized and integrated with the first, second and third FETs on the same substrate, the FET balun circuit is further miniaturized. Be transformed into

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, an FE according to an embodiment of the present invention will be described.
The T balun circuit will be described with reference to the drawings.

(First Embodiment) FIG. 1 shows an FET balun circuit according to a first embodiment of the present invention. The FET balun circuit of FIG.
2 and 7 are provided. The drains of the first FET 1 and the second FET 2 are connected to a positive power supply 5 of, for example, 3 to 5 V via a load resistor 3 and a load resistor 4, respectively. The first
Of the FET 1 is connected to the input terminal 6, and the first
Of the FET 1 is connected to the first output terminal 9. On the other hand, the drain of the second FET 2 is connected to the second output terminal 10. Further, the sources of the first FET 1 and the second FET 2 are each connected to the drain of the third FET 7.

The gate of the second FET 2 is connected to A
It is grounded via a C grounding capacitor 11. This AC
The grounding capacitor 11 is made of BiSrTi
(Bismuth strontium titanium) or SrTiO
(Strontium titanate) or the like having a high dielectric constant (hereinafter, referred to as a high dielectric).

Further, a bias circuit 8 is provided. This bias circuit 8 is for applying a positive bias voltage to each gate of the first and second FETs 1 and 2. The bias circuit 8 includes two voltage dividing resistors 1.
3 and 14 and first and second resistors 15 and 16. The two voltage dividing resistors 13 and 14 are connected in series between the positive power supply 5 and ground. The first resistor 1
5 has one end connected to the gate of the first FET 1 and the other end connected to a connection point between the voltage dividing resistors 13 and 14. The second resistor 16 has one end connected to the gate of the second FET 2 and the other end connected to a connection point between the voltage dividing resistors 13 and 14. Now, the voltage of the positive power supply 5 is divided by the two voltage dividing resistors 13 and 14, and the voltage at the connection point between the two voltage dividing resistors 13 and 14 is set to, for example, + 1.5V. Then,
The gate voltages of the first and second FETs 1 and 2 are +1.
Biased to a positive potential of 5V.

The gate of the third FET 7 is grounded, and the source of the third FET 7 is grounded via a bias resistor 12. Now, the drain-source voltage of the third FET 7 is set to, for example, +1.5 V, and the third FET 7 is operated as a constant current source. In other words, with respect to the drain-source voltage of the third FET 7, To keep the flowing current at a constant value, the second FET
Assuming that the gate-source voltage of No. 2 is +0.5 V, the third
The drain voltage of the FET 7 (= source voltage of the second FET 2) is +2.0 V, and the source voltage of the third FET 7 is set to +0.5 V by the bias resistor 12. At this time, the gate of the third FET 7 is grounded and its gate voltage is 0 V.
Is biased to a negative potential of -0.5V.

Next, the operation of the FET balun circuit according to the embodiment of the present invention will be described.

First, a single-phase RF signal is input to the input terminal 6. At this time, although the current of the first FET 1 changes, the AC component of the gate of the second FET 2 is grounded through the AC grounding capacitor 11 and the third FE
Since the current flowing through T7 is a constant value, the drain potential of the third FET 7 changes without changing the total value of the current flowing through the load resistor 3 and the current flowing through the load resistor 4.

Therefore, as long as the single-phase signal input to the input terminal 6 is in the linear region of the first FET 1, the third F
The voltage at the drain of ET7 becomes equal to the gate voltage of the first FET1. As a result, signals whose phases are inverted from each other are obtained at the first output terminal 9 and the second output terminal 10. Therefore, the single-phase signal input to the input terminal 6 is converted into a differential signal by the balun circuit, and the differential signal is obtained as the output of the output terminals 9 and 10.

As described above, in the FET balun circuit of the present embodiment, the function of converting a single-phase input signal into a differential signal is ensured as in the conventional balun circuit, and the AC ground is connected to the gate of the second FET 2. For the first F
Since the gates of the ET1 and the second FET 2 are each biased to a positive potential, it is not necessary to set the gate and the source of the third FET 7 to a negative potential, respectively. The power supply VSS becomes unnecessary. Therefore, in the FET balun circuit of the present embodiment, downsizing can be achieved.

Moreover, since the insulating film of the AC grounding capacitor 11 is formed of a high dielectric material such as BiSrTi or SrTiO, the AC grounding capacitor 11 can be formed very small. As a result, the AC grounding capacitor 11 is connected to the first FET as shown in FIG.
1, the second FET 2 and the third FET 7 can be integrated on the same substrate Sub.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
An embodiment will be described.

FIG. 3 shows an FET balun circuit according to the present embodiment. The balun circuit shown in the figure is obtained by adding a bias adjusting circuit to the FET balun circuit shown in FIG. In this embodiment, the distortion of the harmonics generated in the first FET 1 and the second FET 2 and the variation in the characteristics between the FETs 1 and 2 are further improved.
It is intended to effectively suppress the occurrence of a phase error between the output signals of the first and second output terminals 9 and 10 due to the difference in distance from the first and second output terminals 9 and 10. The FE shown in FIG.
Description of the components of the T-balun circuit is omitted.

In FIG. 3, reference numeral 20 denotes a bias adjustment circuit. The bias adjustment circuit 20 includes a resistor 17 and a variable resistor 18 connected in series. One end of the resistor 17 is connected to the positive power supply 5 and the other end is a first FE.
Connected to the gate of T1. One end of the variable resistor 18 is connected to the gate of the first FET 1, and the other end is grounded. Therefore, the gate of the first FET 1
It is biased to a positive potential determined by the variable resistor 18.

FIG. 4 shows the relationship between the bias voltage of the gate of the first FET 1 and the phase error between the output signals of the first and second output terminals 9 and 10. When the bias voltage of the gate of the second FET 2 is +1.5 V and the bias voltage of the gate of the first FET 1 is also +1.5 V (in the case of the first embodiment), it can be seen from FIG. In addition, the phase error is 0.73 degrees. On the other hand, by adjusting the resistance value of the variable resistor 18 of the bias adjustment circuit 20, the first FET
When the bias voltage of the gate of No. 1 is set to +1.62 V, the phase error becomes extremely small (about 0.3 degrees). As described above, according to the present embodiment, the phase error between the output signals of the two output terminals 9 and 10 can be improved by using the bias adjustment circuit 20.

(Third Embodiment) Next, a third embodiment of the present invention will be described.

FIG. 5 shows an FET balun circuit according to the present embodiment. The balun circuit shown in the figure is obtained by adding a series resonance circuit to the FET balun circuit shown in FIG. In the present embodiment, the second FET generated in the first FET 1 and the second FET 2
The next harmonic is to be suppressed. The description of the components of the FET balun circuit already described is omitted.

In FIG. 5, reference numeral 24 denotes a series resonance circuit. This series resonance circuit 24 is connected to the first output terminal 9 and the second output terminal 9.
And a series circuit in which a resonance coil 21, a resonance resistor 22, and a resonance capacitor 23 are connected in series. In the series resonance circuit 24, constants of these three elements are set so as to show the same impedance as the resonance circuit resistor 22 at twice the frequency of the single-phase signal input to the input terminal 6. You.

Therefore, in this embodiment, at a frequency twice the frequency of the single-phase input signal, the potential difference between the first output terminal 9 and the second output terminal 10 is reduced by the series resonance circuit 24. The first FET 1 and the second FE
Since the second harmonic of T2 is suppressed, a signal whose phase has been inverted more accurately is output to the first output terminal 9 and the second output terminal 10.

[0043]

As described above, according to the FET balun circuit of the first to eighth aspects of the present invention, an AC grounding capacitor is arranged at the gate of the second FET, so that the first and second FETs can be connected. Since the gates of both FETs can be biased to a positive potential, a negative power supply for setting the gate and source of the third FET to a negative potential can be eliminated, and the size of the FET balun circuit can be reduced. .

In particular, according to the fourth aspect of the present invention, since the bias adjusting circuit is provided, the first FET or the second FET is provided.
Even if there is distortion or characteristic variation of the harmonics generated by ET, the phase error between the output signals obtained at the first and second output terminals can be reduced or minimized.

According to the sixth aspect of the present invention, the series resonance circuit is provided to prevent the output signals of the first and second output terminals from including the second harmonic, so that it is more accurate. An output signal whose phase has been inverted can be obtained.

Further, according to the invention described in claim 8, AC
Since the grounding capacitor is miniaturized and integrated with the first, second and third FETs on the same substrate, the FET balun circuit can be further miniaturized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an FET balun circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a state in which an AC grounding capacitor is integrated on a same substrate as first, second and third FETs.

FIG. 3 is a diagram illustrating an FET balun circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a relationship between a bias voltage value of a gate of a first FET and a phase error between two output signals.

FIG. 5 is a diagram illustrating an FET balun circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a conventional FET balun circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first FET 2 second FET 3 load resistance 4 load resistance 5 positive power supply 6 input terminal 7 third FET 8 bias circuit 9 first output terminal 10 second output terminal 11 AC grounding capacitor 12 for bias Resistors 13, 14 Voltage dividing resistor 15 First resistor 16 Second resistor 17 Resistor 18 Variable resistor 20 Bias adjustment circuit 21 Resonant coil 22 Resonant resistor 23 Resonant capacitor 24 Series resonant circuit

Claims (8)

[Claims] 1. A FET balun circuit for converting a single-phase signal input to an input terminal into a differential signal, and outputting the differential signal from first and second output terminals, wherein a drain is a positive power supply and Connected to the first output terminal,
A first FET having a gate connected to the input terminal; a second FET having a drain connected to the positive power supply and the second output terminal; one end connected to a gate of the second FET; An AC grounding capacitor having the other end grounded, a drain connected to the source of the first FET and the second F
A third F connected to the source of ET and having a gate grounded
An FET balun circuit comprising ET. 2. The FET balun circuit according to claim 1, further comprising a bias circuit for biasing the gates of said first FET and said second FET to a predetermined positive potential. 3. The bias circuit is connected to two voltage dividing resistors for dividing the voltage of the positive power supply, and to a connection point between the gate of the first FET and the two voltage dividing resistors. A first resistor, a second resistor connected between the second FET gate and the AC grounding capacitor, and a connection point of the two voltage dividing resistors. 3. The FET balun circuit according to claim 2, wherein: 4. The FET according to claim 2, further comprising a bias adjustment circuit for adjusting at least one of a bias voltage of a gate of the first FET and a bias voltage of a gate of the second FET. Balun circuit. 5. The bias adjustment circuit has one end connected to the positive power supply and the other end connected to the first FET.
And a variable resistor having one end connected to the gate of the first FET and the other end grounded.
An FET balun circuit as described. 6. A series resonance circuit disposed between the first output terminal and the second output terminal and performing series resonance at a frequency twice as high as a frequency of a single-phase signal input to the input terminal. 6. The FET balun circuit according to claim 1, wherein the FET balun circuit is provided. 7. The series resonance circuit according to claim 6, wherein a resonance coil, a resonance capacitor, and a resonance resistor are connected in series.
An FET balun circuit as described. 8. The AC grounding capacitor has a capacitor insulating film, the capacitor insulating film is formed of a high dielectric film, the AC grounding capacitor, the first FET, the second FET, 8. The method according to claim 1, wherein the third FET is integrated on the same substrate. FET balun circuit.