JP2000269324A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to prevent the area of a chip from being increased in the case where a plurality of integrated circuit boards, which are respectively formed with an integrated circuit, are laminated and are electrically connected with each other, and to enable formation of a multitude of connection parts in a high density. SOLUTION: This manufacturing method is a manufacturing method of a semiconductor device of a structure, wherein a plurality of circuit boards, which are respectively formed with a circuit pattern constituting an integrated circuit or a wiring part of the integrated circuit, are respectively laminated on semiconductor substrates 11 and 31. The manufacturing method has a process for forming a metal pillar 19 on the region formed with the circuit pattern on the side of the connection surface of the circuit board on the side of the laminated circuit board by patterning; a process for forming a recessed part 37, which can be inserted with at least one part of the pillar 19 and is provided with the bottom which is formed as a metal conductive part 34a, on the side of the connection surface of the other laminated circuit board; and a process, wherein the pillar 19 is inserted in the recessed part 37 to connect the pillar 19 with the metal conductive part 34a by pressure bonding.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique for laminating a plurality of semiconductor substrates.

[0002]

2. Description of the Related Art In an electronic circuit system, it is necessary to minimize connection wiring between a plurality of integrated circuits for high-speed operation. For this reason, a technique of stacking a plurality of semiconductor integrated circuit boards to minimize wiring resistance between the boards has been studied.

[0003] This technique of stacking integrated circuit boards is called a vertical stacked integrated circuit technique (eg, Stefa).
nA. Kuhn et al., "Technical di
guest of international ele
ctron devicesmeeting p. p.
249-252 (1995) "). Further, by using this vertical laminated integrated circuit, different types of integrated circuit substrates having different manufacturing processes are laminated to form one mixed-type integrated circuit board. For example, by stacking a substrate on which a memory element is integrated and a substrate on which a high-speed logic element is integrated, a semiconductor device including a memory and a logic can be easily manufactured. It is thought to be possible.

In this vertical stacked integrated circuit, it is necessary to electrically connect integrated circuit boards stacked one above another. Such a method of electrically connecting the upper and lower integrated circuit substrates is described in, for example, Japanese Patent Application No. 60-160645, and the method will be briefly described below with reference to FIG.

[0005] First, as shown in FIG. 6A, a metal hard mask 52 is formed on a silicon substrate 51. Next, as shown in FIG. 6B, the silicon substrate 51 is etched using the hard mask 52 to form an opening 53. Subsequently, as shown in FIG. 6C, a predetermined material film 54 is formed on the bottom of the opening 53 and the opening 53 is formed.
The insulating film 55 is formed on the side of the substrate. Further, as shown in FIG. 6D, polycrystalline silicon is embedded in the opening 53 as a connection plug 56 between chips. After this stage, an integrated circuit pattern (not shown) such as a semiconductor element and a wiring is formed on the silicon substrate 51. After the integrated circuit pattern is formed, as shown in FIG. 6E, the back surface of the silicon substrate 51 is ground using a dry etching method or a mechanical polishing method to expose the bottom of the connection plug 56. Thereby, the connection plug 56 penetrating through the silicon substrate 51 is obtained.

By vertically laminating and connecting a plurality of integrated circuit boards manufactured as described above via connection plugs 56, a vertically laminated integrated circuit is obtained.

However, when fabricating a vertical stacked integrated circuit by the above-described method, it is necessary to provide a connection plug penetrating through the silicon substrate in a region other than the region where the integrated circuit pattern is formed. However, there is a problem that the area increases. In addition, since polycrystalline silicon is used as the connection plug, there is a problem that the connection resistance between the chips is increased.

On the other hand, as a method of stacking and connecting a plurality of integrated circuit boards, a method of forming solder bumps on one of the boards and electrically connecting the boards by the solder bumps can be considered. However, it is difficult to form fine solder bumps, and therefore, there is a problem that a large number of solder bumps cannot be formed on a substrate at high density.

[0009]

As described above, when a plurality of integrated circuit boards on which integrated circuits are formed are stacked and electrically connected, the problem is that the area of each integrated circuit chip increases. In addition, there is a problem that a large number of connection portions cannot be formed at a high density on an integrated circuit chip.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described conventional problems, and can prevent an increase in chip area when a plurality of integrated circuit boards on which integrated circuits are formed are electrically connected. It is an object of the present invention to provide a semiconductor device capable of forming a large number of connection portions at high density and a method of manufacturing the same.

[0011]

SUMMARY OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device in which a plurality of circuit boards on which an integrated circuit or a circuit pattern constituting a wiring portion of an integrated circuit is formed on a semiconductor substrate, Forming a metal pillar by pattern processing on a region where a circuit pattern on a connection surface side of one of the circuit boards to be laminated is formed; and at least one of the metal pillars on a connection surface side of the other circuit board to be laminated. Forming a concave portion in which a portion can be inserted and a bottom portion of which is a metal conductive portion, and inserting the metal pillar into the concave portion and crimp-connecting the metal pillar and the metal conductive portion to form the one portion. Electrically connecting the circuit pattern of the circuit board to the circuit pattern of the other circuit board.

The present invention also relates to a semiconductor device in which a plurality of circuit boards on which an integrated circuit or a circuit pattern constituting a wiring portion of an integrated circuit is formed on a semiconductor substrate, wherein one of the stacked circuit boards is provided. A patterned metal pillar is formed on the region where the circuit pattern on the connection surface side is formed, and at least a part of the metal pillar is inserted and connected to the connection surface side of the other circuit board stacked. A concave portion in which the metal pillar is connected to the bottom metal conductive portion is formed, and the circuit pattern of the one circuit board and the circuit pattern of the other circuit board are electrically connected by the metal pillar connected to the metal conductive portion. It is characterized by being electrically connected.

According to the present invention, since the metal pillar is formed on the area where the circuit pattern is formed, there is no need to provide a connection plug that penetrates the semiconductor substrate unlike the related art. Therefore, the metal pillar can be formed at an arbitrary position on the substrate without increasing the area of the integrated circuit chip. In addition, since the patterned metal pillars are used instead of the solder bumps, the connection region can be miniaturized, and a large number of metal pillars can be formed at a high density.

It is preferable that at least a portion of the metal pillar other than the upper part of the pillar is formed of aluminum or a material containing aluminum as a main component (a material obtained by adding at least one of copper and silicon to aluminum or the like).

As described above, by using aluminum or a low-resistance material containing aluminum as a main component as the metal pillar, the resistance between the substrates can be greatly reduced.

A material layer made of a material that contracts or evaporates by heat treatment or plasma treatment is formed on a surface of the other circuit board facing the one circuit board (particularly, on the outermost surface of the facing surface). When performing the step of pressing the metal pillar and the metal conductive portion, a heat treatment or a plasma treatment may be performed.

Specifically, an organic silicon insulating film is used as a material contracted by the heat treatment, and the heat treatment is performed simultaneously when the metal pillar and the metal conductive portion are pressed, so that the organic silicon insulating film is formed in the thickness direction. There is a method of shrinking.

As described above, since the material layer made of a material which contracts by the heat treatment is formed, the material layer contracts in the film thickness direction by the heat treatment at the time of the pressure contact step. At the same time, excessive concentration of pressure is prevented, and variations in height between the metal pillars are suppressed, so that highly reliable connection can be performed.

There is also a method of vaporizing the carbon film by using a carbon film as a material to be vaporized by the plasma treatment and simultaneously performing the plasma treatment when the metal pillar and the metal conductive portion are pressed.

As described above, by forming a material layer made of a material which is vaporized by the plasma processing, the material layer is gradually vaporized by the plasma processing at the time of the pressure bonding step. Excessive pressure concentration is prevented, and variations in height between the metal pillars are suppressed, so that highly reliable connection can be performed.

It is preferable that the main component of the constituent material above the pillar of the metal pillar is the same as the main component of the constituent material of the metal conductive part. As described above, by using the same material as the constituent material of the metal conductive portion on the pillar upper portion, bonding with the metal conductive portion can be easily performed by pressure bonding, and good electrical characteristics at the bonded portion can be obtained. it can.

In particular, it is preferable to use copper or a material containing copper as a main component for the pillar upper part and the metal conductive part. Copper can easily reduce the natural oxide film formed on the surface thereof in a hydrogen atmosphere, so that good electrical connection can be obtained between the metal pillar and the metal conductive portion. In addition, since copper has excellent malleability, it is possible to prevent excessive pressure concentration during pressure bonding. Further, when the pillar body of the metal pillar is patterned into a vertical shape by RIE, copper or a material containing copper as a main component can be used as a hard mask, and a pillar having a high aspect ratio can be formed.

The upper portion of the metal pillar is preferably formed of a noble metal such as gold or platinum or a material containing a noble metal as a main component.

Since a noble metal is unlikely to form a natural oxide film on its surface, a good electrical connection can be obtained between the metal pillar and the metal conductive portion. In addition, since the noble metal has excellent malleability, it is possible to prevent excessive pressure concentration during pressure bonding. Furthermore, the pillar body of the metal pillar is
When patterning into a vertical shape by IE, a noble metal or a material containing a noble metal as a main component can be used as a hard mask, and a pillar having a high aspect ratio can be formed.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) A first embodiment of the present invention will be described with reference to FIGS. In the present embodiment, a metal pillar is formed on one substrate, a connection hole is formed on the other substrate, and both substrates are connected by pressure bonding.

First, a method of forming metal pillars on one substrate will be described with reference to FIGS.

First, as shown in FIG. 1A, on a semiconductor substrate (silicon substrate or the like) 11, an active element region 12 (details not shown) made of a MOS transistor or the like and a multilayer wiring region 13 (wiring ( (Including plugs and electrodes) 14, and an interlayer insulating film 15) are sequentially formed in the same manner as in a normal method. Next, a protective insulating film 16 is formed on the entire surface, and a part of the protective insulating film 16 is removed.
The opening 17 is formed on the electrode 14a provided on the uppermost layer side of.

Next, as shown in FIG. 1B, a metal film 18 serving as a metal pillar is deposited on the entire surface by a sputtering method or the like. As the metal film 18, it is desirable to use Al having a low electric resistivity, and a material in which a small amount of Cu or Si or a small amount of Cu and Si is added to Al may be used.

Next, as shown in FIG. 1C, a resist pattern (not shown) is formed by photolithography on the portion where the metal pillar is to be formed. Subsequently, the metal film 18 is patterned by a reactive ion etching (RIE) method using the resist pattern as a mask, thereby forming a metal pillar 19 patterned into a vertical shape.
To form When the metal film 18 is Al or a material containing Al as a main component, the opening 17 is formed by performing RIE until the protective insulating film 16 is exposed using a mixed gas of BCl ₃ and Cl ₂ as a main etching gas. , The lower region of the metal pillar 19 can be embedded in a self-aligned manner.

When patterning the metal pillars 19, instead of using a photoresist as an etching mask, a film having high etching resistance to a chlorine-based etching gas such as a SiN film can be used as a hard mask. It is. That is, after depositing a metal film 18 of Al or the like, a SiN film is successively deposited by a plasma CVD method or the like, and a resist pattern (not shown) is formed by photolithography at a portion where a metal pillar is to be formed. Subsequently, using this resist pattern as a mask, S is etched with a fluorine-based etching gas such as fluorocarbon.
Etch the iN film. Then, using this patterned SiN film as a hard mask, BCl ₃ and C
By performing RIE using a mixed gas of l ₂ as a main etching gas, a metal pillar 19 patterned into a vertical shape is formed. The hard mask can be selectively removed by dry etching or the like after forming the metal pillar.

As described above, when a hard mask is used,
Since the etching resistance to the Al etching gas is higher than when a photoresist mask is used, a metal pillar having a higher height can be formed.

Although only one metal pillar is shown in the drawing, many metal pillars are actually formed on the same substrate.

Next, a method of forming a connection hole for inserting a metal pillar in the other substrate will be described with reference to FIGS.
This will be described with reference to FIG.

First, as shown in FIG. 2A, on a semiconductor substrate (silicon substrate or the like) 31, an active element region 32 (details are not shown) made of a MOS transistor or the like and a multilayer wiring region 33 (wiring ( (Including a plug and an electrode) 34 and an interlayer insulating film 35) are sequentially formed in the same manner as in a normal method. Subsequently, a protective insulating film 36 is formed on the entire surface.

Next, as shown in FIG. 2B, a resist pattern (not shown) is formed by photolithography in which a portion where a connection hole is to be formed is an opening. continue,
By using the resist pattern as a mask to pattern the protective insulating film 36 by RIE, a connection hole 37 is formed on the electrode 34 a provided on the uppermost layer side of the multilayer wiring region 33. The diameter of the connection hole 37 is set to be larger than the diameter of the metal pillar 19 shown in FIG. Further, as shown in the figure, it is desirable that at least the upper side of the connection hole 37 has a tapered shape. The taper shape is
It can be formed by changing the RIE condition during the formation of the connection hole 37 or by performing etching with a diluted hydrofluoric acid solution after the RIE.

Although only one connection hole is shown in the drawing, a large number of connection holes are actually formed on the same substrate in correspondence with a large number of metal pillars formed on the opposing substrate. Will be.

Next, a method of connecting one substrate having metal pillars formed by the method shown in FIG. 1 and the other substrate having connection holes formed by the method shown in FIG. 2 will be described with reference to FIG. This will be described with reference to FIGS.

First, as shown in FIG. 3A, the connection surfaces of the one substrate on which the metal pillars 19 are formed and the other substrate on which the connection holes 37 are formed are opposed to each other to perform alignment. .

Next, as shown in FIG. 3B, the metal pillar 19 is fitted into the opposing connection hole 37.

Next, as shown in FIG. 3C, the metal pillar 19 is connected to the electrode 34 at the bottom of the connection hole 37 while heating.
a. Thereby, the substrates are physically connected to each other via the metal pillars 19, and the electrodes 14a formed on one substrate are electrically connected to the electrodes 34a formed on the other substrate. At this time, by deforming a part of the metal pillar 19, it is possible to absorb a variation in height between the plurality of metal pillars 19, and all the metal pillars 19 formed at an arbitrary position on the substrate surface are good. Connection can be obtained.

According to the present embodiment, there is no need to form a connection plug that penetrates the semiconductor substrate as in the related art, so that a metal pillar can be formed on a region where elements and wirings are formed. Therefore, the metal pillar can be formed at an arbitrary position on the substrate without increasing the area of the integrated circuit chip.

Since the metal pillars are formed by patterning based on photolithography instead of solder bumps, individual connection regions can be miniaturized.
Many metal pillars can be formed on the same chip at high density. In addition, since the metal pillar is formed of a low-resistance metal such as Al, the resistance of the metal pillar can be significantly reduced.

Therefore, different types of integrated circuit substrates having different manufacturing processes, for example, a substrate on which a memory portion is formed and a substrate on which a logic portion is formed are laminated, and the uppermost wiring is connected via metal pillars. This makes it possible to manufacture a multifunctional hybrid LSI having a memory function and a logic function with a high degree of integration.

For an LSI having a multilayer wiring structure having a large number of wiring layers typified by a logic LSI, a semiconductor element and a wiring below the multilayer wiring are formed on one substrate, and the other substrate is formed on the other substrate. It is also possible to form a wiring on the upper layer side of the multilayer wiring. That is, only the wiring among the elements and the wiring which are the main components of the integrated circuit is formed on the other substrate. By using such a configuration, the number of wiring layers of the multilayer wiring can be increased as compared with the conventional case, and the signal delay of the circuit can be reduced as compared with the conventional case.

Furthermore, according to the present embodiment, by managing the non-defective products of the respective substrates to be laminated separately and connecting the non-defective products, a high non-defective product yield can be obtained, and at the same time, the manufacturing time as a whole can be improved. Can also be shortened.

(Embodiment 2) Next, a second embodiment of the present invention will be described with reference to FIGS. This embodiment is a modification of the first embodiment described above, and the same or corresponding components as those shown in FIGS. 1 to 3 are denoted by the same reference numerals.

FIG. 4A shows a process of aligning the respective connection surfaces of the one substrate on which the metal pillars 19 are formed and the other substrate on which the connection holes 37 are formed, and performing alignment. It is. The configuration and manufacturing process of one of the substrates on which the metal pillars 19 are formed are the same as in the first embodiment.

In this embodiment, the structure of the other substrate on which the connection holes 37 are formed is different from that of the first embodiment.
In the present embodiment, after the protective insulating film 36 is formed by the same process as in the first embodiment, the spacer insulating film 38 is formed on the protective insulating film 36. The spacer insulating film 38 is made of a material that shrinks by the heat treatment, for example, an organic silicon insulating film such as SOG, and the organic silicon insulating film is applied on the protective insulating film 36. After forming the spacer insulating film 38, a connection hole 37 penetrating through the spacer insulating film 38 and the protective insulating film 36 is formed.

Next, as shown in FIG. 4B, the metal pillar 19 is fitted into the opposing connection hole 37. At this time, the depth of the connection hole 37 including the thickness of the spacer insulating film 38 is:
It is desirable to make the depth deeper than the height of the metal pillar 19. Thus, when the metal pillar 19 is fitted into the connection hole 37, the upper surface of the metal pillar 19 can be prevented from contacting the bottom of the connection hole 37, so that excessive pressure concentration at the connection portion can be prevented.

Next, as shown in FIG. 4C, the metal pillar 19 is connected to the electrode 34 at the bottom of the connection hole 37 while heating.
a. Thereby, the substrates are physically connected to each other via the metal pillars 19, and the electrodes 14a formed on one substrate are electrically connected to the electrodes 34a formed on the other substrate. At this time, the spacer insulating film 38 shrinks in the thickness direction due to the heat treatment.
Excessive pressure concentration at each connection portion is prevented, and variations in height between the metal pillars 19 are absorbed, so that good connection can be obtained with all of the metal pillars 19 formed at an arbitrary position on the substrate surface. It becomes possible.

In the above-described example, the material that shrinks by the heat treatment is used as the spacer insulating film. However, a material that evaporates by the plasma treatment may be used. Specifically, a carbon film is used as the spacer insulating film, and the carbon film is ashed and removed by performing a plasma treatment in an oxygen atmosphere at the time of performing the pressure bonding in the step of FIG. In this case, the spacer insulating film is gradually removed, and as in the above-described example, excessive pressure concentration at each connection portion is prevented, and variations in the height between the metal pillars 19 are absorbed, so that an arbitrary surface of the substrate is removed. A good connection can be obtained with all of the metal pillars 19 formed at the location.

(Embodiment 3) Next, a third embodiment of the present invention will be described with reference to FIG. This embodiment is a modification of the first embodiment described above, and the same or corresponding components as those shown in FIGS. 1 to 3 are denoted by the same reference numerals.

FIG. 5 shows the configuration of one substrate on which the metal pillars 19 are formed. The configuration and manufacturing steps of the other substrate on which the connection holes are formed are the same as in the first embodiment. is there.

In the present embodiment, as shown in the figure, an upper metal film 2 made of a constituent material different from the constituent material of the pillar main body is formed on the upper part of the pillar on the pillar main body of the metal pillar 19.
0 is formed. There are several examples of the upper metal film 20 as described below.

In the first example, Au is used as the upper metal film 20.
A noble metal such as Pt or Pt or a material containing a noble metal as a main component is used. Since a natural oxide film is hardly formed on the surface of the noble metal, good electrical connection can be obtained between the metal pillar and the electrode at the bottom of the connection hole by using the noble metal film as the upper metal film 20. In addition, since the noble metal is rich in malleability, it is possible to prevent excessive pressure concentration at the connection portion when the metal pillar is pressed against the electrode at the bottom of the connection hole. Further, when the pillar-forming material mainly composed of Al or Al is vertically processed by RIE using a chlorine-based gas, the upper electrode 20 using a noble metal can be used as a hard mask for RIE. Pillars having a higher aspect ratio can be formed as compared with the case where RIE is performed as a mask.

In the second example, as the upper metal film 20, the same material as the material of the electrode (electrode 14a shown in FIGS. 1 to 3) at the bottom of the connection hole of the other substrate is used. By using the same type of material as described above, good bonding can be easily obtained by pressure bonding, and good electrical characteristics at the bonded portion can be obtained.

In particular, it is preferable to use Cu or a material containing Cu as a main component as the constituent material of the connection hole bottom, and also use Cu or a material containing Cu as a main component for the upper metal film 20. When Cu is used, a natural oxide film on the Cu surface can be easily reduced in a hydrogen atmosphere, so that good electrical contact can be obtained. Moreover, since Cu is rich in malleability, it is possible to prevent excessive pressure concentration at the connection portion during crimping. Further, when the pillar-forming material mainly composed of Al or Al is vertically processed by RIE using a chlorine-based gas, the upper electrode 20 using Cu can be used as a hard mask for RIE. Pillars having a higher aspect ratio can be formed as compared with the case where RIE is performed as a mask.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment.
For example, the technique described in the second embodiment and the technique described in the third embodiment can be combined. In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[0060]

According to the present invention, since the metal pillar is formed on the region where the circuit pattern is formed, it is possible to suppress an increase in the area of the integrated circuit chip. Further, a large number of connection portions can be formed at high density by the fine metal pillars subjected to the pattern processing.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, and is a process sectional view showing a process when forming a metal pillar on one substrate.

FIG. 2 is a view showing the first embodiment of the present invention, and is a cross-sectional view showing a step in forming a connection hole in the other substrate.

FIG. 3 is a diagram showing the first embodiment of the present invention, and is a process cross-sectional view showing a process of pressing a metal pillar formed on one substrate to the other substrate.

FIG. 4 is a diagram showing a second embodiment of the present invention, and is a process cross-sectional view showing a process of pressing a metal pillar formed on one substrate to another substrate.

FIG. 5 is a view showing a third embodiment of the present invention, and is a cross-sectional view showing a modification of a metal pillar formed on one substrate.

FIG. 6 is a process cross-sectional view showing an example of a manufacturing process of a semiconductor device according to a conventional technique.

[Explanation of symbols]

 11, 31 ... semiconductor substrate 12, 32 ... active element region 13, 33 ... multilayer wiring region 14, 34 ... wiring 15, 35 ... interlayer insulating film 16, 36 ... protective insulating film 17 ... opening 18 ... metal film 19 ... metal pillar 20: Upper metal film 37: Connection hole 38: Spacer insulating film

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Noriaki Matsunaga, Inventor, 8-8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Eiji Shibata, 8-8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa, Japan (72) Katsuya Okumura, Inventor Katsuya Okumura 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Toshiba Yokohama Office (reference) QQ28 QQ37 QQ73 QQ99 RR01 RR06 RR25 SS15 SS22 UU03 VV07 XX03 XX09 XX10 XX19

Claims (11)

[Claims] 1. A method of manufacturing a semiconductor device comprising a plurality of circuit boards on which a circuit pattern forming an integrated circuit or a wiring portion of an integrated circuit is formed on a semiconductor substrate, the method comprising the steps of: Forming a metal pillar by pattern processing on a region where the circuit pattern on the connection surface side is formed; and at least a part of the metal pillar can be inserted into the connection surface side of the other circuit board to be laminated, and the bottom thereof can be inserted. Forming a concave portion serving as a metal conductive portion; and inserting the metal pillar into the concave portion and crimp-connecting the metal pillar and the metal conductive portion, thereby forming a circuit pattern on the one circuit board and Electrically connecting a circuit pattern of the other circuit board to a circuit pattern of the other circuit board. 2. The method according to claim 1, wherein at least a portion other than the upper portion of the metal pillar is formed of aluminum or a material containing aluminum as a main component. 3. A material layer made of a material that shrinks or vaporizes by heat treatment or plasma treatment is formed on a surface of the other circuit board facing the one circuit board, and the metal pillar and the metal conductive portion are formed. 2. The method according to claim 1, wherein a heat treatment or a plasma treatment is performed when the step of pressure-bonding is performed. 4. The method of manufacturing a semiconductor device according to claim 1, wherein a main component of a constituent material of an upper portion of the metal pillar is the same as a main component of a constituent material of the metal conductive portion. . 5. The method according to claim 1, wherein an upper portion of said metal pillar is formed of copper or a material containing copper as a main component. 6. The method according to claim 1, wherein an upper portion of the pillar of the metal pillar is formed of a noble metal or a material containing a noble metal as a main component. 7. A semiconductor device comprising a plurality of circuit boards on which an integrated circuit or a circuit pattern constituting a wiring portion of an integrated circuit is formed on a semiconductor substrate, wherein the connection side of one of the stacked circuit boards is provided. A patterned metal pillar is formed on the area where the circuit pattern is formed, and at least a part of the metal pillar is inserted into the connection surface side of the other laminated circuit board, and the metal conductive layer at the bottom thereof is inserted. A concave portion connected to the metal pillar is formed in the portion, and the circuit pattern of the one circuit board and the circuit pattern of the other circuit board are electrically connected by the metal pillar connected to the metal conductive portion. A semiconductor device characterized in that: 8. The semiconductor device according to claim 7, wherein at least a portion other than the upper portion of said metal pillar is formed of aluminum or a material containing aluminum as a main component. 9. The semiconductor device according to claim 7, wherein a main component of a constituent material of a pillar upper portion of said metal pillar is the same as a main component of a constituent material of said metal conductive portion. 10. The semiconductor device according to claim 7, wherein upper portions of said metal pillars are formed of copper or a material containing copper as a main component. 11. The semiconductor device according to claim 7, wherein an upper portion of the pillar of the metal pillar is formed of a noble metal or a material containing a noble metal as a main component.