JP2000269276A - Method and system for analyzing defect - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a defect analyzing system for comprehensive defect analysis of a semiconductor wafer and improved yield in a semiconductor manufacturing process. SOLUTION: A defect inspection means 143 which detects defects on a semiconductor wafer and generates a defect data representing defect position, defect classification data generating means 144 which references the defect data to classify the defects by size, color, and form, etc., for generating a defect classification data, tester means 153 which measures a fail bit map data representing electrical failure of the chip on a semiconductor wafer, fail bit map data processing means 151 which classifies the fail bit map data into several defective modes comprising a plurality of bits to generate a defective mode classification data before the coordinate system of the defective mode classification data is coordinate-converted into a defective data coordinate system by defective mode unit, and a matching process means 120 for defect analysis which uses the defective data, defective classification data, and coordinate-converted defective mode classification data, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect which becomes an electrical defect by comparing defect data on a semiconductor wafer with electrical defect data of a chip on the semiconductor wafer and specifying a position where the two coincide with each other. The present invention relates to a defect analysis system and method for identifying a killer defect, and more particularly to a technique for improving the yield of a semiconductor device manufacturing process.

[0002]

2. Description of the Related Art With the rapid progress of semiconductor integrated circuit technology in recent years, millions to tens of millions of semiconductor chips have been mounted on one semiconductor wafer. Against this background, detailed analysis of defects and electrical defects occurring in a semiconductor integrated circuit has become a very important task in a semiconductor device manufacturing process, and defect analysis techniques are also rapidly evolving.

[0003] There are many defect analysis techniques. Defect data indicating the location of foreign matter or defects on a semiconductor wafer, which is measured by a defect inspection device or the like, and semiconductor memory such as a tester device. FBM indicating the location of an electrical defect on a semiconductor chip, measured by an electrical test device
(Fail BitMap, fail bitmap) The most common method is to perform a matching process to match data and identify a defect (Killer defect) on a semiconductor wafer that becomes a truly electrical failure. It is known to be a powerful technique.

Generally, when performing this matching process, coordinate conversion is performed so that the coordinate system of the defect data and the coordinate system of the FBM data are the same. FB to match that of
The defective address of the M data is subjected to coordinate conversion for each bit, and then a matching process is performed.

[0005]

As described above, in the conventional defect analysis, the defect address of the FBM data is coordinate-converted bit by bit so that the coordinate system of the FBM data matches that of the defect data. The Killer defect is identified by performing a matching process. However, such a conventional defect analyzer and its method have the following technical problems.

That is, in the coordinate conversion in the conventional defect analysis apparatus and method, the defective address of the FBM data is converted into the coordinate system of the defect data for each bit, so that the number of bits increases due to the large capacity of the memory device. Further, in recent years, the number of generated defects is enormous, and the time required for defect analysis is enormous.

In general, an electrical defect caused by one defect on a semiconductor wafer is caused not only at the location where the defect exists but also at the defect position in the word line direction or bit line direction. However, since the conventional defect analyzer and the conventional method simply match the defect data with the FBM data, it is necessary to identify what defect the defect is electrically causing. Can not.

Further, in general, defects on a semiconductor wafer have various sizes, colors, and shapes.
Creating defect classification data by classifying defects by color, shape, etc., and performing statistical analysis of the defects is a very important task in understanding the causes of the defects. In the analysis device and its method, matching processing between the defect classification data and the electrical failure mode cannot be performed.

Furthermore, in-line monitoring for defects is performed by monitoring the number of defects, the number of defects per defect mode, the number of defective chips, and the like. However, all defects in the defect mode recognized as Killer defects are true. It is not defective, and the conventional defect analyzer and its method use Ki
Even if the number of ller defect modes can be monitored, a defect leading to an electrical failure cannot be monitored.

The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a defect analysis system that performs comprehensive defect analysis on a semiconductor wafer and realizes improvement in the yield of a semiconductor manufacturing process. To provide.

Another object of the present invention is to provide a defect analysis method for performing a comprehensive defect analysis on a semiconductor wafer and improving the yield of a semiconductor manufacturing process.

[0012]

Means for Solving the Problems To solve the above problems, the inventor has classified the FBM data into several failure modes which are a set of a plurality of bits, and performed coordinate conversion in data units of the failure mode. And performs a matching process with the defect data. ・ Classifies the defect data according to its size, color, shape, etc.
A defect analysis system and a method for performing a matching process with FBM data using defect classification data have been proposed.

A first feature of the present invention is that a defect inspection means for detecting a defect on a semiconductor wafer and generating defect data indicating the position of the defect, and referring to the defect data to determine the size and color of the defect. A defect classification data generating means for generating defect classification data by classifying according to shape, shape, etc .; a tester means for measuring fail bit map data indicating an electrical failure of a chip on a semiconductor wafer; Fail bit map data processing means for creating failure mode classification data by classifying the defect mode classification data into several FBMs, and converting the coordinate system of the failure mode classification data into the defect data coordinate system in units of failure mode; Matching processing means for performing defect analysis using the defect data, the defect classification data, and the coordinate-transformed FBM data. Lies in a defect analysis system.

As a result, Killer becomes a truly electrical failure.
Correlation data between defect classification data and electrical failure mode data can be collected and analyzed.Furthermore, by analyzing the correlation data in detail, measures against the causes of defects can be taken, and the yield of the semiconductor manufacturing process can be improved. Can be realized.

A second feature of the present invention is a defect inspection step of detecting a defect on a semiconductor wafer and generating defect data indicating a position of the defect, and referring to the defect data to determine the size and color of the defect. A defect classification data generating step of generating defect classification data by classifying according to a shape, a shape, etc .; a fail bit map data measuring step of measuring fail bit map data indicating an electrical failure of a chip on a semiconductor wafer; and a fail bit map data. A failure mode classification step of creating failure mode classification data by classifying the failure mode into a plurality of failure modes, which is a set of a plurality of bits, and setting the coordinate system of the failure mode classification data to the coordinate system of the defect data in units of failure mode. A coordinate conversion step for converting, the defect data, the defect classification data, and the coordinate-converted FBM defect mode. Lies in a defect analysis method and a butt analyzing step performs defect analysis using the classification data.

[0016] As a result, Killer becomes a truly electrical failure.
Correlation data between defect classification data and electrical failure mode data can be collected and analyzed.Furthermore, by analyzing the correlation data in detail, measures against the causes of defects can be taken, and the yield of the semiconductor manufacturing process can be improved. Can be realized.

Here, it is provided with an administrator terminal, a technician terminal, and an electronic mail transmitting / receiving means, and when defect classification data is obtained, it is determined whether or not a defect of a predetermined condition or more exists on the semiconductor wafer. An abnormality determination may be performed, and if it is determined that the semiconductor wafer is abnormal, the fact may be notified to the administrator terminal and the technician terminal using an electronic mail transmitting / receiving means.

Incidentally, the abnormality determination may be performed using the number of defective chips on the semiconductor wafer.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a defect analysis system and method according to an embodiment of the present invention will be described in detail with reference to FIGS.

First, the configuration of a defect analysis system according to an embodiment of the present invention will be described.

As shown in FIG. 1, a defect analysis system 100 according to an embodiment of the present invention includes a data analyzer 110 for controlling an analysis process, defect data and defect classification data, and FBM (Fail BitMap) failure. A matching processing device 120 for performing matching processing with mode classification data, a defect data management device 140 for collecting and storing defect data and defect classification data, and an F for collecting and storing FBM data and FBM failure mode classification data.
The matching processing device 120 includes a BM data management device 150 and performs a matching process between the defect data and the FBM failure mode classification data.
21, a database 122 for storing various data related to the matching process, and a defect data management device 140,
Defect inspection apparatus 1 for collecting defect data on a semiconductor wafer
43. Defect review + ADC (Auto Defect Classification) means 144 for classifying defects by size, color, shape, etc. with reference to the defect data and collecting defect classification data;
The defect data management server 141 that manages defect data and defect classification data, the database 142 that stores defect data and defect classification data, and the FBM data management device 150
Tester device 153 for collecting FBM data of chip, F
Create FBM failure mode classification data from BM data,
Test data management server 151 for performing coordinate transformation, FBM
It has a database 152 for storing data and FBM failure mode classification data.

Next, a defect analysis method according to an embodiment of the present invention will be described with reference to FIGS.
The description is divided into three stages of 2) FBM data processing and 3) matching processing.

1) Defect Data Processing When defect data is analyzed by the defect analysis method according to the embodiment of the present invention, first, as shown in the flowchart of FIG. 2, 1-1 (defect measurement, step S101),
Defect data is measured by the defect inspection device 143, and 1-
2 (Defect Data Transmission (I), Step S102) Next, defect data is transmitted to the defect data management server 141, and 1-3 (Defect Data Transmission (II), Step S1
03) Next, in order to review the size, color shape, etc. of the defect, the coordinate information of the defect data is transmitted to the defect review + ADC means 144, and 1-4 (defect classification processing, step S104). The + ADC means 144 classifies defects according to size, color, shape, etc., creates defect classification data, and performs 1-5 (defect classification data transmission,
Step S105) Subsequently, the defect classification data is transmitted to the defect data management server 141, and 1-6 (data storage,
Step S106) Finally, by storing the defect data and the defect classification data in the database 142,
The defect data and defect classification data used for the matching process are created.

2) FBM Data Processing When analyzing the FBM data by the defect analysis method according to the embodiment of the present invention, as shown in the flowchart of FIG. 3, 2-1 (FBM data measurement, step S20)
1) First, the FBM data of the chip on the semiconductor wafer is measured by the tester device 153, and 2-2 (FBM data transmission, step S202). Then, the FBM data is transmitted to the test data management server 151, and 2-3 (Failure Mode Classification, Step S203) Next, the FBM data is classified for each of several failure modes which are a set of a plurality of bits, and failure mode classification data is created. Then, the failure mode classification data is stored in the database 152, and 2-5 (coordinate conversion processing, step S205), the coordinate system of each failure mode classification data is converted into the coordinate system of the defect data, and 2-6 (coordinate conversion data Transmission, step S206) After performing the coordinate conversion processing for one wafer, the failure mode classification data subjected to the coordinate conversion is stored in the database 152. Stored in the further processing server 1 abutting the failure mode classification data coordinate transformation
21 to be used for the matching process.
Create BM failure mode classification data.

Here, the above coordinate conversion processing will be briefly described with reference to FIG.

In the coordinate conversion processing according to the embodiment of the present invention, first, a certain subset of bits constituting the FBM data is defined as a failure mode of the FBM data, and the subset is represented by a rectangular range. start from. That is, the addresses of the start point P1 and the end point P2 of the rectangle covering the entire set of bits 1 shown in FIG. When the FBM failure mode data is subjected to coordinate conversion into the coordinate system of the defect data, the address description of the rectangular area is made to correspond to the center coordinate (x, y) and the size (W) of the rectangular area so as to match the coordinate description of the defect. ,
Described in D). At this time, the origin B of the FBM coordinate system
Since the origin A of the defect coordinate system is generally different from that of the defect coordinate system as shown in FIG. 5B, correction is performed so that the origins of the two coincide with each other. By performing this process for all the failure modes on the semiconductor wafer, the coordinate system of the FBM failure mode classification data is converted to the coordinate system of the defect data.

3) Matching Process The matching process according to the defect analysis method according to the embodiment of the present invention is performed as shown in the flowchart of FIG.
1 (Defect mode classification data reception, step S301)
First, FBM failure mode classification data for one wafer to be analyzed is received from the test data management server 151, and
-2 (Defect Classification Data Search, Step S302) Next, the wafer 142 is searched for defect classification data corresponding to the FBM failure mode classification data from the database 142, and
3 (matching analysis, step S303)
Using the BM failure mode classification data, the defect data and the defect classification data, a matching process is performed to perform defect analysis. 3-4 (data storage, step S304) Finally, the defect analysis result is stored in the database 122. Done.

Here, the above matching process will be briefly described with reference to FIGS.

In the matching process according to the embodiment of the present invention, the tolerance areas 6, 9 according to the shape and size of the FBM failure mode classification such as the bit failure 4 and the line failure 7 are provided. Defects 5 and 8 entering tolerance regions 6 and 9 are regarded as having a relationship with the FBM failure by matching the data with the FBM failure mode classification data (here, the size of the tolerance region is determined by the user. Can be set arbitrarily). Then, as shown in FIG. 7, for example, as shown in FIG. 7, the result of the matching process is compared with the FBM failure mode classification data for each defect classification. The data is put together as an aggregation table and stored in the database 122.

As described above, according to the defect analysis system and method according to the embodiment of the present invention, defect analysis can be performed while observing the relationship between defect data and defect classification data and FBM failure mode classification data. So
It becomes possible to collect and analyze the correlation data of the Killer defect classification and the electrical failure mode, which are truly electrical failures.Furthermore, by analyzing the correlation data in detail, it is possible to take countermeasures against the causes of defects Thus, it is possible to improve the yield of the semiconductor manufacturing process.

In the defect analysis apparatus and method according to the embodiment of the present invention, Killing Ra is used for each defect classification.
te is calculated, and based on the value of the Killing Rate, a weighting factor is set for each defect classification for abnormality determination and yield prediction (see FIG. 9A), and the number of defects in consideration of the weighting factor is monitored. By providing a means such as performing a defect analysis, it is possible to construct a defect analysis apparatus and method for detecting an abnormality on a semiconductor wafer at an early stage and removing a defective wafer by predicting a yield.

That is, as an application example of the defect analysis system according to the embodiment of the present invention, for example, as shown in FIG. 8, a data analysis device 110 is composed of a manager terminal 111 and a technician terminal 112. The defect data management server 151 is provided with the e-mail transmitting / receiving means 145, and when the defect classification data is transmitted from the defect review + ADC means 144 to the defect data management server 151, a defect exceeding a predetermined condition is found on the semiconductor wafer. An abnormality determination (monitoring) as to whether or not the semiconductor wafer is present is performed, and when it is determined that the semiconductor wafer is abnormal, the fact is notified to the administrator terminal 111 and the technician terminal 112 using the electronic mail transmitting / receiving means 145. To do.

Several methods can be considered as a method of determining the above-described abnormality. Here, a method of determining the number of defects on the semiconductor wafer and a method of determining the number of defective chips will be described as examples. Judgment method is this 2
It is not limited to one method.

First, as an example of the abnormality determination method according to the embodiment of the present invention, a case where the abnormality determination is performed based on the number of wafer defects will be described. When making an abnormality judgment based on the number of defects,
First, as shown in, for example, FIG. 9B, the number of abnormality determination defects for determining that the wafer is abnormal is set for each defect classification. FIG. 9 shows the number of defects in each collected defect classification.
The weighting coefficient as set in (a) is multiplied, and when the value is equal to or larger than the value set as the number of abnormal determination defects, a notification that the wafer is abnormal is given. For example, FIG.
In the case where the number of defects for abnormality determination shown in FIG. 7 is set, when the number of defects of the defect classification name A is measured to be 1050 on the wafer, the weighting coefficient of the defect classification name A for the defect number 1050 is set to 0.
By multiplying by 1, the calculated value 150 is obtained. However, since the number of abnormality determination defects of the defect classification name A is set to 100, the wafer is determined to be abnormal, and an abnormality warning is issued by the administrator or technical staff. Will be notified.

As another example of the abnormality determination method according to the embodiment of the present invention, a case where the abnormality determination is performed based on the number of defective chips will be described. When the abnormality is determined based on the number of defective chips, it is determined whether or not a certain chip becomes defective based on the number of defects, and the reference yield of the wafer is set in advance.
That is, first, as shown in FIG. 9C, the number of abnormality determination defects per chip for each defect classification is set in advance. At this time, the number of defects with a defect classification name A in a certain chip is 12
If the number of defects is 12, the number of defects is multiplied by the weighting coefficient 0.1 of the defect classification name A to obtain a calculated value of 1.2. Since the calculated value 1.2 is larger than the defect determination number 1 of the defect classification name A, it is determined that this chip is likely to be defective (the same processing is performed for other defect classifications). If an abnormality is determined in any one of the defect classifications, the chip is determined to be an abnormal chip.) Then, this chip abnormality determination processing
The process is performed on all the chips on the wafer, and the yield of the wafer is predicted by extracting the number of defective chips in one wafer. At this time, by providing an abnormality determination criterion also for the value of the yield, it is possible to construct a defect analysis apparatus and a method for issuing a warning when the yield falls below a certain yield.

Thus, it should be appreciated that the present invention covers various embodiments not described herein. Therefore, the present invention must be limited only by the matters specifying the invention according to the claims that are reasonable from this disclosure.

[0037]

As described above, according to the defect analysis system of the present invention, the defect analysis can be performed while observing the relationship between the defect data and the defect classification data and the FBM failure mode classification data. It is possible to collect and analyze the correlation data of the Killer defect classification and the electrical failure mode that are truly electrical failures.Furthermore, by analyzing the correlation data in detail, it is possible to take countermeasures against the causes of defects, It is possible to improve the yield of the manufacturing process.

Further, according to the defect analysis method of the present invention, the defect analysis can be performed while observing the relationship between the defect data and the defect classification data and the FBM failure mode classification data. It is possible to collect and analyze the correlation data of Killer defect classification and electrical failure mode, and by analyzing the correlation data in detail, take measures against the causes of defects and improve the yield of the semiconductor manufacturing process. It can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a defect analysis system according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a defect analysis method according to the embodiment of the present invention.

FIG. 3 is a flowchart illustrating a defect analysis method according to the embodiment of the present invention.

FIG. 4 is a schematic diagram illustrating a coordinate conversion method according to an embodiment of the present invention.

FIG. 5 is a flowchart illustrating a defect analysis method according to the embodiment of the present invention.

FIG. 6 is a schematic diagram for explaining a matching process according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a result of a matching process according to the embodiment of the present invention.

FIG. 8 is a block diagram showing an application example of the defect analysis system according to the embodiment of the present invention.

FIG. 9 is a diagram illustrating an example of an abnormality determination method according to the embodiment of the present invention.

[Explanation of symbols]

 1 bit 2 chip area 3 FBM area 4 bit defect 5,8 defect 6,9 tolerance 7 line defect 100 defect analysis system 110 data analyzer 111 administrator terminal 112 technician terminal 120 matching processing device 121 matching processing server 122, 131, 142, 152 Database 130 Semiconductor CIM system 140 Defect data management device 141 Defect data management server 143 Defect inspection device 144 Defect review + ADC means 145 E-mail transmission / reception means 150 FBM data management device 151 Test data management server 153 Tester device A Defect coordinates Origin of system B Origin of FBM coordinate system

Claims (2)

[Claims] 1. A defect inspection means for detecting a defect on a semiconductor wafer and generating defect data indicating a position of the defect; and referring to the defect data to determine a defect size,
Defect classification data generating means for classifying by color, shape, etc. and generating defect classification data; tester means for measuring fail bit map data indicating an electrical failure of a chip on the semiconductor wafer; and A fail bit map for creating failure mode classification data by classifying into several failure modes that are a set of a plurality of bits, and performing coordinate conversion of the coordinate system of the failure mode classification data to the coordinate system of the defect data in units of failure mode. A defect analysis system, comprising: data processing means; and matching processing means for performing a defect analysis using the defect data, the defect classification data, and the coordinate-converted failure mode classification data. 2. A defect inspection step of detecting a defect on a semiconductor wafer and generating defect data indicating a position of the defect; and referring to the defect data to determine a defect size,
A defect classification data generation step of generating defect classification data by classifying by color, shape, and the like; a fail bitmap data measurement step of measuring fail bitmap data indicating an electrical failure of a chip on the semiconductor wafer; A failure mode classification step of creating failure mode classification data by classifying the bitmap data into several failure modes that are a set of a plurality of bits; and a coordinate system of the failure mode classification data for the defect mode unit in the failure mode unit. A coordinate conversion step of performing coordinate conversion to a data coordinate system; and a matching analysis step of performing a defect analysis using the defect data, the defect classification data, and the coordinate-converted failure mode classification data. Defect analysis method.