JP2000268632A - Insulating film and manufacture thereof and electronic device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a factor hindering high speed performance of a device when fullerene is used for a copper wiring layer and to exhibit the benefit of lowering of resistance due to copper wiring to the maximum by performing vacuum deposition for fullerene, generating light-crosslinking reaction between fullerene molecules one another and making fullerene molecules into high molecules. SOLUTION: Fullerene molecules are molecules existing stably by a structure in which 60, 70 or 84 carbons are covalent bound with one another, for instance, and six-membered rings and five-membered rings are linked. Fine powder of C60 fullerene is set at a deposition source and a silicon substrate doped with ions and made to have lower resistance is set at a vacuum deposition device. Evacuation is performed till base vacuum becomes about 2×10-6 Torr or below. By determining a substrate temperature for a room temperature, films are made in thickness of about 250 nm at film making speed of about 0.5 nm/second. An ultraviolet light source of about 365 nm is selected for these fullerene films for about 30 to 60 seconds, these fullerene films are irradiated with ultraviolet ray for 30 minutes, carbon of C60 fullerene molecules and carbon of other C60 fullerenes are coupled one another across oxygen and fullerene molecules are made into high molecules.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for forming an insulating film and a technique for manufacturing an electronic device such as a semiconductor device, a display device, and a multilayer circuit board such as an MCM (multi-chip module) using the insulating film. .

[0002]

[0003]

2. Description of the Related Art As is well known, semiconductor devices and display devices are expected to be further integrated and further miniaturized in the background of the demand for further miniaturization and higher functionality of electronic devices using them. Is needed. However, for example, in order to increase the speed of these devices, it is necessary to roughly resolve two delay factors. 1) Solving the transistor delay problem, such as changing the design of the device active area itself to be suitable for high-speed operation. 2) The solution of the wiring delay problem such as lowering the resistance of the wiring layers themselves or lowering the dielectric constant of a so-called interlayer insulating film between the wiring layers to reduce the capacitance between the wiring layers.

[0004] As a result of recent miniaturization of devices, the problem of transistor delay has not changed much, while the problem of wiring delay has become very serious. The reason is that the miniaturization of devices has led to the miniaturization of the wiring layer itself,
This is because the resistance of the wiring layer itself increases due to the reduction in the wiring cross-sectional area, and the wiring capacitance increases as the distance between the wiring layers decreases. Therefore, solving the problem of wiring delay has emerged as a very important issue as a breakthrough to further miniaturization.

[0005]

As a method of dealing with the problem of wiring delay, there is a movement to search for a lower resistance copper, silver, or gold instead of an aluminum-based material for the wiring layer itself. Wiring has already been realized and practically applied to device products.

However, even if the wiring material is switched to copper, the distance between the wirings is still short, that is, the problem of the capacitance remains unsolved, and there is still room for improvement as a fundamental solution of the wiring delay. Remains intact. In particular, it has been customary to use a silicon oxide film as an interlayer insulating film around a wiring layer in a conventional device of the aluminum wiring layer generation, but when a copper wiring is used, a copper wiring layer is used. It cannot be designed to directly contact the silicon oxide film. A silicon nitride film is interposed between the copper wiring layer and the silicon oxide film to avoid direct contact between the two, but the silicon nitride film is an insulating material with a remarkably high dielectric constant. Although the resistance of the wiring material itself has been reduced, the capacitance between wirings has been increased, which is a hindrance in solving the problem of wiring delay. In a future generation of electronic devices with further miniaturization, the problem of an increase in inter-wiring capacitance due to a silicon nitride film will inevitably become a major factor as a factor that governs the overall device speed.

[0007] The problem to be solved by the present invention is to reduce such capacitance between wirings. In particular, in an electronic device using a copper wiring layer, it is an object of the present invention to eliminate a factor that hinders the high-speed performance of the device and to maximize the benefit of reducing the resistance by the copper wiring.

[0008]

Means for Solving the Problems To solve the above problems, the present invention provides the following means.

First, an insulating film made of a polymer in which fullerene molecules are bonded to each other. And an electronic device using the same as an insulating film. More specifically, for example, an insulating film polymerized by vacuum deposition of fullerene and then causing a photocrosslinking reaction between the fullerene molecules. And an electronic device using the same as an insulating film.

Second, a method for producing an insulating film polymerized by vacuum-depositing fullerene and then causing a photocrosslinking reaction between the fullerene molecules. And a method for manufacturing an electronic device having such a manufacturing method as one step.

In the above two means, when the electronic device has a copper wiring, it is preferable to use the above means as an insulating film between wiring layers, because the inherent high-speed performance of the copper wiring can be utilized. In the above means, for example, ultraviolet rays may be used as the photocrosslinking reaction.

Next, the operation of the above means will be described. See FIG.

In the present invention, fullerene is polymerized to form a film material. The fullerene molecule has, for example, 60 carbon atoms.
, Or 70, 84, etc. are covalently bonded to each other, and have a structure in which a six-membered ring and a five-membered ring are connected like a soccer ball, and have a spherical shape as a whole and can exist very stably. In recent years, it has attracted attention as a molecule. FIG. 1 shows C6
FIG. 2 is a structural diagram (a schematic perspective view) of a 0 fullerene molecule. In the figure, small round particles represent carbon atoms, and those connecting the carbon atoms in a bar shape are carbon-carbon bonds. As described above, each carbon atom constituting fullerene is bonded to each of the other three carbon atoms shown in the drawing, and has a spherical shape as a whole. Fullerene molecules have a void in which almost no electron cloud exists in the center of the sphere.Therefore, use of the fullerene molecule as a conductor or semiconductor has been actively studied by enclosing another atom in the void. In the present invention, it is rather possible to lower the dielectric constant of fullerene molecules by not enclosing anything in these voids, and fullerenes are molecules that can exist very stably, but by irradiating energy rays, We focused on the fact that a film can be easily formed by forming a polymer by covalent bonding with each other. When a film is formed of the fullerene as a whole, the existence ratio of voids is increased at the molecular level, even though the film is stable, so that the dielectric constant can be lowered. Furthermore, even if the coating is formed so as to be in direct contact with the copper wiring, even if the heat history is long, copper does not diffuse toward the insulating film. Because the fullerene molecule itself has a remarkable covalent bond, it can be a strong barrier to prevent copper from diffusing as ions.

[0014]

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. See FIG. 1 again.

The C60 fullerene used for film formation has an FCC structure (face-center closest-packed structure) as shown in FIG. The structure of the C60 fullerene polymer thin film that has undergone the polymerization process after the deposition is assumed to be as shown in FIG. FIG.
reference.

FIG. 2 is a structural diagram (schematic plan view) of a C60 fullerene polymer, wherein (a) to (c) show different types of polymers. In each of (a) to (c), a carbon atom is indicated by a black circle, and a bond between carbon and carbon is expressed by a straight line connecting the black circles to each other. (A) is a ladder-shaped polymer formed by covalently bonding two carbon atoms of one C60 fullerene and two carbon atoms of the other C60 fullerene,
(B) is a planar polymer formed by gathering a plurality of ladder-like polymers shown in (a) and covalently bonding carbon atoms of a C60 fullerene skeleton forming each polymer to each other; ) Is a polymer formed by covalently bonding C60 fullerenes with other C60 fullerenes at a plurality of places in a plane.

The presumption that C60 fullerene is polymerized as shown in FIG. 2 is based on the results of IR absorption spectrum (shown in FIG. 3) and X-ray diffraction spectrum (shown in FIG. 4). As a result of the X-ray diffraction spectrum, the crystal orientation can be determined, but as shown in FIG.
A peak was observed on one surface. On the other hand, according to the IR absorption spectrum, 527cm ^-1, 577cm ^-1, 1183cm
The peak intensity at ^-1 and 1428 cm ^-1 is 100: 37: 2.
It was observed that the ratio was 3:24, indicating that it was an FCC crystal. A gold electrode having a diameter of 1 mm was formed on the same C60 fullerene thin film, and the dielectric constant calculated from the capacitance measurement result was 3.0.

A transistor is formed on the surface of a semiconductor substrate, and the entire substrate is covered with an interlayer insulating film so as to cover the transistor. As the interlayer insulating film, for example, a BPSG film is selected, and has a thickness of 800 nm by a CVD (chemical vapor deposition) method.
After coating, the top surface of which can be flattened by a CMP (chemical mechanical polishing) method can be used. Alternatively, an SOG (spin-on-glass) film that can form a flat film by coating is used. But it is good. A resist mask is formed on the surface of the interlayer insulating film thus formed, and a contact window is provided through a normal photolithography process so as to expose the upper surface of the gate of the transistor. After the resist mask is ashed, a tungsten film is formed by CVD over the entire surface so as to fill the contact window and have a sufficient thickness. Other refractory metal-based materials and other metal materials can be used, but tungsten is the most widely used. The condition at this time is WF6 (tungsten hexafluoride) + H2
The substrate temperature is about 400 ° C., the gas pressure is 0.5 Torr, and the power is 500 W using a mixed gas of (hydrogen). Then C
Only the contact windows are left by the MP (chemical mechanical polishing) method, and the other portions are removed. The structure formed by the above steps will be described as a “substrate layer” in FIG. FIGS. 5 to 8 referred to below are explanatory views of one embodiment of the present invention (parts 1 to 4, each of which is a process sectional view). See FIG.

FIG. 5 is an explanatory view (part 1, process sectional view) of an embodiment of the present invention.

In the step (a), C60 fullerene is vacuum-deposited on the substrate layer formed as described above. A fine powder of C60 fullerene is set as an evaporation source, and a silicon substrate which has been ion-doped to have a low resistance is set in a vacuum evaporation apparatus. Subsequently, evacuation was performed until the base vacuum became 2 × 10 ⁻⁶ Torr or less.

When the substrate temperature is room temperature, the film forming speed is 0.5 nm.
/ Sec to form a film with a thickness of about 250 nm. In the subsequent step (c), a UV light source of 365 nm (about 1000 W) is selected and irradiated with UV light for 30 seconds to 60 seconds for 30 minutes to the C60 fullerene molecule in the subsequent step (c) for the C60 fullerene film laminated as shown in the step (b). And the carbon of the other C60 fullerene molecule are bonded to each other with oxygen in between to form a polymer. See FIG.

Following the step (c) shown in FIG.
In step (1), a 50 nm silicon oxide film was further formed on the C60 fullerene polymer film. Plasma CVD
Although it is preferable to form the silicon oxide film using a method, a normal thermal CVD method may be used. When the plasma CVD method is used, first, the film forming speed is high, and thus it is suitable for mass production. Subsequently, in a step (2), a resist is applied and formed on the surface of the silicon oxide film.
Then, the resist is patterned through a normal photolithography process to form a mask, and in the subsequent step (4), a window is provided in accordance with the position of the tungsten layer in the base substrate layer using the mask. Using the mask pattern, the silicon oxide film and the C60 fullerene film are sequentially opened, and it is preferable that both are formed by plasma etching. The silicon oxide film is etched using fluorine plasma. See FIG.

After removing the silicon oxide film, step (5)
Then, the C60 fullerene film is removed. At this time, oxygen plasma is used for the etching instead of the fluorine plasma used in the step (4). Thereafter, the resist used for the mask is ashed and removed by down-flow ashing using plasma containing oxygen. Subsequent process (6)
Then, tantalum nitride (TaN) is deposited by sputtering so as to extend from the inside of the opening to the outside and make electrical contact with the tungsten layer at the bottom of the opening. Next, copper is embedded in the opening whose inner surface is covered with a 10 nm-thick tantalum nitride film (TaN). First, as shown in step (7), a copper (Cu) seed layer is deposited on the entire surface inside and outside of the opening by sputtering to a thickness of about 50 nm, and then the step (8) is performed. As described above, a sufficiently thick copper (Cu) plating layer including the inside of the opening is formed by electroplating. See FIG.

Subsequently, in a step (9a), the tantalum nitride (TaN) / copper (Cu) double layer remaining on the flat surface except for the inside of the opening is polished and removed at a time by a CMP (chemical mechanical polishing) method. I do. Thereafter, in step (10a), a C60 fullerene film is formed to a thickness of about 800 nm on top of another. The forming method at this time is the same as the above-described method of forming the fullerene film. A silicon oxide film (SiO2) is formed on the entire surface. It is formed to a thickness of about 5 nm by a CVD method. Further, the wiring layer is formed to have a thickness of about 50 nm. In this case, if necessary, the surface may be flattened by using both film formation by plating and etch back by CMP (chemical mechanical polishing). Further, a silicon oxide film (SiO2) is formed on the entire surface. It is formed to a thickness of 50 nm by the CVD method.

On the surface of this silicon oxide film (SiO 2)
A resist is applied and formed, and a pattern is formed on the resist through a normal photolithography process. At this time, the opening of the resist pattern is patterned by being previously aligned with the position of the underlying tungsten layer to be contacted. Using such a resist pattern, a deep contact window reaching the tungsten layer is opened by plasma etching. Opening is performed by appropriately switching the etchant so that fluorine plasma is used for the silicon oxide film and oxygen plasma is used for the C60 fullerene film. One tantalum nitride (TaN) is placed inside and outside the opening.
0 nm sputter-formed, then copper inside and outside the opening
0 nm is formed by sputtering. Subsequently, copper is buried in the openings by electrolytic plating.

It is possible to form a deep contact window and a shallow contact window in the same device, but in such a case, it is necessary to add the following steps.

The TaN / Cu film other than the wiring groove by CMP (below)
Layered layer of tantalum nitride and copper in order)
Leave. In addition, with cap and etching stopper layer
Chemical vapor deposition of silicon nitride (SiN) 50nm
C60 fullerene film 800nm, wiring
SiO serving as an etching stopper layer during layer etching _Two
Film 5 nm, C60 fullerene film 50 nm, and mask
Layer SiO_TwoA film was formed to a thickness of 50 nm. First, add
A-pattern into fluorine plasma and oxygen plasma respectively
And a second layer wiring pattern.
Formed a turn. Finally, convert the SiN film to fluorine plasma
After further processing, the first wiring in the groove of dual damascene structure
Similarly, a laminated wiring of TaN and Cu was embedded. On this occasion,
No darkening or poor conduction of the via was observed at all.
For etching the C60 fullerene film, for example, an oxide film is used.
Processed by dry etching using fluorine-based plasma
Use it as a mask or
Processing can be performed using an inorganic resist.

In the above-described embodiment, the C60 fullerene film is formed immediately after the copper wiring layer is left only in the opening window and the others are removed by using the CMP (chemical mechanical polishing) method. Prior to forming CVD
A silicon nitride film (SiN) with a thickness of about 50
nm. This will be described with reference to FIG. See FIG.

FIG. 9 is an explanatory view (process sectional view) of a modified embodiment of the present invention. After the step (9b) corresponding to the above-described step (9a), the surface is planarized by a CMP (chemical mechanical polishing) method so that copper remains only in the opening window. A silicon film (SiN) is entirely formed by a chemical vapor deposition method.
In b), the C60 fullerene film is polymerized through vacuum deposition and ultraviolet irradiation to form a C60 fullerene polymer film. Subsequently, an SiO ₂ film and a C60 fullerene film are sequentially deposited, and the formation method at this time may be the same as that described in the above step (10a).

As described above, the greatest merit of forming the C60 fullerene film with silicon nitride (SiN) interposed therebetween is that the insulating films are less likely to be separated from each other and the reliability is increased. When the C60 fullerene film is directly attached to the copper surface, the possibility of peeling due to unexpected stress caused by heat or mechanical stress during the process cannot be denied, but it is characterized in that it can be eliminated.
However, on the other hand, as already pointed out as a problem of the prior art, silicon nitride (SiN) is an insulating material having a very high dielectric constant.
Even if the thickness is very small, it can be a major factor in increasing the dielectric constant of the entire interlayer insulating film, which in turn increases the inter-wiring capacitance and hinders the speeding up of the device to some extent. Will need to be further increased, or the speed performance needs to be slightly increased, and depending on the situation, the priority will need to be used depending on the situation.

The above is an explanation of the present invention based on the embodiment. Next, the effect of how much the high-speed performance is improved through the present invention as compared with the conventional art has been confirmed, and this will be described. See FIG.

FIG. 10 is an explanatory diagram of the evaluation circuit. Specifically, FIG. 10 shows a so-called ring oscillator circuit for both A and B. A is a ring oscillator in which 100 inverters are connected in series with two inverters as one set, and B is a ring oscillator in which a wiring between one inverter and another inverter is intentionally lengthened as one set and 100 stages are connected in series. The connected ring oscillator. In these ring oscillators, a wiring thickness of 0.5
In the case of a ring oscillator having a long wiring with a wiring pitch of 0.4 μm and a wiring pitch of 0.4 μm, the length of the wiring is particularly increased by 50 μm. The signal delay time caused by different types of the interlayer insulating film is determined by determining whether such a ring oscillator circuit employs a C60 fullerene film as the interlayer insulating film or an SiO ₂ film as in the related art. And two types were prepared and converted from the oscillation frequency when these ring oscillator circuits operated, and evaluated. The signal delay time per inverter obtained in B is from the input of an inverter having a long wiring to the input of the next inverter. From the results obtained in this way, as a result of comparing the response speed between the above-described example of the embodiment of the present invention and the example of the related art using the SiO ₂ film, it was found that the response speed between the copper wiring and the C60 fullerene film was large. When the silicon nitride (SiN) film is not interposed, the speed is improved by about 30%, and the copper wiring and C6
When a silicon nitride (SiN) film is interposed between the 0 fullerene film and the fullerene film, the speed is improved by about 20%.

In each of the above embodiments, C60 has been described as an example of fullerene.
It does not occur only in 60, for example, C70, C7
6, C78, C82, C96, C100, C102, C
In any fullerene such as 120, the hollow region where almost no electron cloud exists in the molecule is wide, and for example, the dielectric constant of C70 is reduced to 2.7. In addition, the same effect can be expected since the two are relatively easily bonded to each other to form a coating film by irradiation with energy rays such as ultraviolet rays. Among higher order fullerenes, C120 can be generated by irradiating a C60 thin film with ultraviolet / visible light to fuse C60 molecules with each other.

[0035]

As described above, when the film is formed of the fullerene as a whole, the existence ratio of voids is increased at the molecular level, even though the film is stable, so that the dielectric constant can be lowered. Furthermore, even if the coating is formed so as to be in direct contact with the copper wiring, even if the heat history is long, copper does not diffuse toward the insulating film. Since the fullerene molecule itself has a remarkable covalent bond, it can prevent copper from diffusing as ions.

[Brief description of the drawings]

FIG. 1 is a structural diagram of a C60 fullerene molecule (schematic perspective view).

FIG. 2 is a structural diagram of a C60 fullerene polymer (schematic plan view).

FIG. 3 Results of IR absorption spectrum inspection

FIG. 4 X-ray diffraction test results

FIG. 5 is an explanatory view of one embodiment of the present invention (part 1, process sectional view).

FIG. 6 is an explanatory view of one embodiment of the present invention (part 2, process cross-sectional view).

FIG. 7 is an explanatory view of one embodiment of the present invention (part 3, process cross-sectional view).

FIG. 8 is an explanatory view of one embodiment of the present invention (part 4, process cross-sectional view).

FIG. 9 is an explanatory view (process sectional view) of a modified embodiment of the present invention.

FIG. 10 is an explanatory diagram of an evaluation circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/314 H01L 21/314 A 5F058 21/768 C08J 5/18 CFA 5G303 // C08J 5/18 CFA H01L 21/90 A 5G333 P (72) Inventor Shiro Yamaguchi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Katsumi Suzuki 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No.1 F-term in Fujitsu Limited (reference) 4F071 AA69 BB11 BC01 4G046 CB03 CC01 CC06 4J032 CA32 CA45 CB01 CE12 CG08 4K029 BA08 BA34 BB02 BC00 BD01 GA01 5F033 HH11 HH32 JJ01 JJ11 JJ32 KK11 MM13 NN11 QQ10 QQ12 QQ37 QQ48 QQ74 QQ81 RR04 RR06 RR09 RR15 RR21 SS10 SS12 SS15 SS22 TT04 XX12 XX25 XX27 5F058 AA 10 AC10 AF10 AG09 AH02 BA05 BA20 BD01 BD04 BD19 BF03 BF07 BF32 BF33 BH20 BJ02 5G303 AA07 AB07 BA03 CA11 5G333 AA03 AB13 AB21 BA01 CA03 DA21 DB02 FB02 FB21

Claims (11)

[Claims] An insulating film made of a polymer in which fullerene molecules are bonded to each other. 2. An insulating film polymerized by vacuum-depositing fullerene and then causing a photocrosslinking reaction between the fullerene molecules. 3. An electronic device using an insulating film made of a polymer in which fullerene molecules are bonded to each other. 4. A method for producing an insulating film polymerized by vacuum-depositing fullerene and then causing a photocrosslinking reaction between the fullerene molecules. 5. An electronic device having an insulating film made of a polymer in which fullerene molecules are bonded to each other. 6. An electronic device having an insulating film polymerized by vacuum deposition of fullerene and then causing a photocrosslinking reaction between the fullerene molecules. 7. A method for manufacturing an electronic device, comprising the steps of vacuum-depositing fullerene, and then causing a photocrosslinking reaction between the fullerene molecules to polymerize to form an insulating film. 8. The method for manufacturing an insulating film according to claim 4, wherein ultraviolet light is selected as irradiation light at the time of the photocrosslinking reaction. 9. The method of manufacturing an electronic device according to claim 7, wherein ultraviolet light is selected as irradiation light at the time of the photocrosslinking reaction. 10. The electronic device according to claim 5, wherein the insulating film is formed so as to be in contact with a wiring layer containing copper. 11. The method according to claim 7, further comprising the steps of: forming a wiring layer containing copper; and forming the insulating film so as to be in contact with the wiring layer.