JP2000261252A - Distortion compensation power amplification circuit - Google Patents

Distortion compensation power amplification circuit

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Publication number
JP2000261252A
JP2000261252A JP11065911A JP6591199A JP2000261252A JP 2000261252 A JP2000261252 A JP 2000261252A JP 11065911 A JP11065911 A JP 11065911A JP 6591199 A JP6591199 A JP 6591199A JP 2000261252 A JP2000261252 A JP 2000261252A
Authority
JP
Japan
Prior art keywords
distortion
output
detector
signal
power amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11065911A
Other languages
Japanese (ja)
Inventor
Kazuhiro Fujisawa
和弘 藤沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Electric Corp
Original Assignee
Kokusai Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Electric Corp filed Critical Kokusai Electric Corp
Priority to JP11065911A priority Critical patent/JP2000261252A/en
Publication of JP2000261252A publication Critical patent/JP2000261252A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale of a distortion compensation power amplification circuit where envelope feedback control is applied to the complex synthesis PD method and to reduce the cost. SOLUTION: Part of an input signal before being divided into two by a distributor 11 is extracted by a directional coupler 10 and is subjected to envelope detection by a detector 23 to obtain a reference input of an error detector 24. Meanwhile, part of the output of a power amplifier 18 is extracted and the signal obtained by envelope detection is inputted to the error detector 24 to detect the difference (distortion component) from the reference input. A control part 25 controls the amplitude and phase of the tertiary distortion of the opposite polarity generated by a tertiary distortion generator 13 so that this difference is made 0.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、VHF,UHF帯
のデジタル移動通信の基地局無線設備に実装される送信
機の電力増幅回路に関し、特に、電力増幅器の発生歪を
抑えて電力効率を上げるための歪補償回路が付加された
電力増幅回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier circuit of a transmitter mounted on a base station radio equipment for digital mobile communication in the VHF and UHF bands, and more particularly, to increase power efficiency by suppressing distortion generated in a power amplifier. And a power amplification circuit to which a distortion compensation circuit is added.

【0002】[0002]

【従来の技術】デジタル移動通信の基地局送信装置に
は、電力用トランジスタを用いた電力増幅回路が設けら
れている。基地局の電力増幅回路は、線形性が良く、高
出力で歪の少ないA級またはAB級動作で、終段はパラ
レル合成またはプッシュプル構成による回路が一般的で
ある。
2. Description of the Related Art A power amplifier circuit using a power transistor is provided in a base station transmitter for digital mobile communication. The power amplifier circuit of the base station is a class A or class AB operation having good linearity, high output, and low distortion, and a circuit using a parallel synthesis or push-pull configuration is generally used at the final stage.

【0003】図3は電力増幅器の入出力特性例図であ
る。デジタル変調された単一キャリア信号(CW)の入
力電力PINに対する出力電力POUT と3次歪の特性例で
ある。入力電力PINが大きくなると、出力電力POUT
ともに3次歪が1:3の傾斜に添って増加し、出力電力
OUT が非線形領域にかかると増加が顕著になる(3次
歪劣化点)。その点と出力電力との差が3次相互変調歪
(IM3 )である。また、この図には、例えば、入力信
号がπ/4シフトQPSK変調されたデジタル信号の場
合の送信出力における隣接チャネルに対する漏洩電力
(ACP)を示している。
FIG. 3 is an example of input / output characteristics of a power amplifier. It is an example of the characteristics of the output power P OUT and the third-order distortion with respect to the input power P IN of the digitally modulated single carrier signal (CW). When the input power P IN increases, the output power P OUT with third-order distortion is 1: increases along the third slope, the output power P OUT becomes remarkable to increase, according to the non-linear region (third-order distortion deterioration point) . The difference between that point and the output power is the third-order intermodulation distortion (IM 3 ). Also, this figure shows, for example, the leakage power (ACP) for the adjacent channel in the transmission output when the input signal is a digital signal subjected to π / 4 shift QPSK modulation.

【0004】このように、入力電力が大きくなると、入
出力特性が非線形性を示すようになり、デジタル変調さ
れた単一キャリアの場合、入力電力が大きくなると、出
力電力に歪成分が含まれるようになる。また、多周波信
号の場合は入力が大きくなると相互変調歪(IM3 )が
発生するようになる。このような歪が発生するとスプリ
アス放射として規制されるため、最大出力が、増幅器の
飽和レベルよりかなり低い値に制限されるので、増幅器
の電力効率が低下することになる。
As described above, when the input power increases, the input / output characteristics show nonlinearity. In the case of a digitally modulated single carrier, when the input power increases, a distortion component is included in the output power. become. In the case of a multi-frequency signal, as the input increases, intermodulation distortion (IM 3 ) occurs. When such distortion occurs, it is regulated as spurious radiation, so that the maximum output is limited to a value considerably lower than the saturation level of the amplifier, and the power efficiency of the amplifier is reduced.

【0005】上述の単一キャリア入力の増加による出力
劣化や多周波入力による相互変調歪の発生は、図からわ
かるように、主として3次歪の発生によるものであり、
このような3次歪を補償する歪補償技術の数々が開発さ
れ実用化されている。
As can be seen from the figure, the above-mentioned output deterioration due to an increase in single carrier input and intermodulation distortion due to multi-frequency input are mainly due to the generation of third-order distortion.
A number of distortion compensation techniques for compensating for such third-order distortion have been developed and put into practical use.

【0006】プリディストーション(PD)は歪補償技
術の一つであり、電力増幅器の前段に電力増幅器で発生
する歪成分を相殺するための信号を発生させるプリディ
ストーション回路(PD回路:前置歪み補償回路)を設
けて、電力増幅器の発生歪を相殺して歪量を改善し、電
力効率を向上をしようとするものである。
[0006] Predistortion (PD) is one of distortion compensation techniques, and a predistortion circuit (PD circuit: predistortion compensation) for generating a signal for canceling a distortion component generated in a power amplifier at a stage preceding the power amplifier. Circuit) to offset the distortion generated by the power amplifier to improve the amount of distortion and improve power efficiency.

【0007】図4は従来の歪補償電力増幅回路のブロッ
ク図である。この例は、複素合成PD法に包絡線帰還制
御を適用した歪補償電力増幅回路である。図において、
11は分配器、12はPD回路、13は歪発生器、14
は可変減衰器、15は可変移相器、16は遅延線、17
は合成器、18は電力増幅器、19は方向性結合器、2
0は検波器、21は制御部、22はメモリである。
FIG. 4 is a block diagram of a conventional distortion compensation power amplifier circuit. This example is a distortion-compensated power amplifier circuit in which envelope feedback control is applied to the complex synthesis PD method. In the figure,
11 is a distributor, 12 is a PD circuit, 13 is a distortion generator, 14
Is a variable attenuator, 15 is a variable phase shifter, 16 is a delay line, 17
Is a combiner, 18 is a power amplifier, 19 is a directional coupler, 2
0 is a detector, 21 is a control unit, and 22 is a memory.

【0008】例えば、入力信号としてπ/4シフトQP
SK変調された単一キャリア信号が入力され、分配器1
1によって遅延線16とPD回路12に分配される。P
D回路12の歪発生器13は3次歪発生器であり、デジ
タル変調された単一キャリアの入力信号の極性を反転し
て3次歪を発生させ、無歪の正極(非反転)キャリア入
力信号と合成してキャリア成分を相殺し、逆極性の3次
歪のみを出力する。その出力は、可変減衰器14と可変
移相器15で振幅と位相が調整され、合成器17で、遅
延線16を介した信号と合成される。その合成信号は電
力増幅器18で増幅されるが、そのとき電力増幅器18
で発生する3次歪成分が、PD回路12で発生させた逆
極性の3次歪成分によって相殺されて歪補償された送信
出力が得られる。送信出力に含まれる残留歪を検出する
ため、その一部が方向性結合器19によって抽出され、
検波器20で包絡線検波されて制御部21に送られる。
For example, as an input signal, a π / 4 shift QP
The SK-modulated single carrier signal is input,
1 to the delay line 16 and the PD circuit 12. P
The distortion generator 13 of the D circuit 12 is a tertiary distortion generator, inverts the polarity of the digitally modulated input signal of a single carrier to generate tertiary distortion, and outputs a non-distorted positive (non-inverted) carrier input. The signal is combined with the signal to cancel the carrier component, and only the third-order distortion of the opposite polarity is output. The output is adjusted in amplitude and phase by a variable attenuator 14 and a variable phase shifter 15, and is combined with a signal via a delay line 16 by a combiner 17. The synthesized signal is amplified by the power amplifier 18, at which time the power amplifier 18
Is canceled by the third-order distortion component of the opposite polarity generated by the PD circuit 12, and a transmission output with distortion compensated is obtained. In order to detect the residual distortion included in the transmission output, a part thereof is extracted by the directional coupler 19,
The envelope is detected by the detector 20 and sent to the control unit 21.

【0009】一方、メモリ22には、送信出力が無歪の
ときの包絡線検波後の波形データが、予め格納されてお
り、制御部21は、検波器20から入力されたデータを
メモリ22のデータと比較し、その差(歪成分)が零に
なるように、可変減衰器14と可変移相器15の値を制
御する。
On the other hand, the waveform data after the envelope detection when the transmission output is no distortion is stored in the memory 22 in advance, and the control unit 21 stores the data input from the detector 20 in the memory 22. The values of the variable attenuator 14 and the variable phase shifter 15 are controlled such that the difference (distortion component) becomes zero with the data.

【0010】[0010]

【発明が解決しようとする課題】しかし、上記従来の歪
補償電力増幅回路においては、メモリ22に記憶させて
おく包絡線検波後の波形データのデータ量が多いため、
回路規模が大きく、かつ、高価である、という問題があ
る。さらに、このような歪補償電力増幅回路が実装され
た送信機を工場で多数生産する場合、電力増幅器の構成
部品の性能のばらつきにより、無歪状態の出力信号を解
析した波形データがばらつくため、多数の製品を一台ず
つ測定してメモリ22にデータを格納しなければなら
ず、工数がかかって原価が下げられない、という問題が
ある。
However, in the above-mentioned conventional distortion-compensated power amplifier circuit, since the amount of waveform data after envelope detection stored in the memory 22 is large,
There is a problem that the circuit scale is large and expensive. Further, when a large number of transmitters equipped with such a distortion compensation power amplifier circuit are manufactured in a factory, waveform data obtained by analyzing an output signal in a non-distortion state varies due to variations in performance of components of the power amplifier. A large number of products must be measured one by one and the data must be stored in the memory 22, which causes a problem that the number of steps is increased and the cost cannot be reduced.

【0011】発明の目的は、上記従来の問題点を解消す
るために行ったものであり、簡単な回路を付加すること
によりメモリを省略して歪補償電力増幅回路の回路規模
を小さくするとともに、多数生産する場合、一台ずつの
調整作業をなくして工数を軽減し、コストを下げられる
ようにした歪補償電力増幅回路を提供することにある。
An object of the present invention is to solve the above-mentioned conventional problems. A simple circuit is added to omit a memory to reduce a circuit scale of a distortion compensation power amplifier circuit. It is an object of the present invention to provide a distortion-compensated power amplifier circuit in which a large number of devices are manufactured, the adjustment work for each device is eliminated, the number of steps is reduced, and the cost is reduced.

【0012】[0012]

【課題を解決するための手段】本発明の歪補償電力増幅
回路は、ディジタル変調された単一キャリアの入力信号
を電力増幅して送信出力とする場合の電力増幅器の非線
形性によって発生し隣接チャネルに対する漏洩電力とな
る歪成分を抑圧するために、前記入力信号を2分配する
分配器と、該分配器で2分配された一方の信号を入力
し、前記電力増幅器の非線形性によって発生する歪と逆
極性の3次歪を発生させる歪発生器と、該歪発生器の出
力の振幅を制御信号によって変化させる可変減衰器と、
該可変減衰器の出力の移相量を制御信号によって変化さ
せる可変移相器と、該可変移相器の出力と前記分配器で
2分配された他方の信号を遅延させた信号とを合成する
合成器と、該合成器で合成された信号を電力増幅して送
信出力とする電力増幅器と、前記入力信号の一部を抽出
して包絡線検波する第1の検波器と、前記送信出力の一
部を抽出して包絡線検波する第2の検波器と、前記第1
の検波器から出力される無歪の包絡線検波出力を基準信
号とし、前記第2の検波器の出力と比較してその差であ
る歪成分を出力する誤差検出器と、該誤差検出器から出
力される歪成分がゼロになるような前記制御信号をそれ
ぞれ前記可変減衰器と前記可変移相器に与える制御部と
が備えられ、前記電力増幅器で発生し隣接チャネルに対
する漏洩電力となる前記歪成分が前記歪発生器によって
発生させた逆極性の3次歪によって相殺されるように構
成されたことを特徴とするものである。
SUMMARY OF THE INVENTION A distortion-compensated power amplifier circuit according to the present invention generates a digitally modulated input signal of a single carrier and amplifies the input signal as a transmission output. And a divider that divides the input signal into two in order to suppress a distortion component that becomes leakage power with respect to the input signal. A distortion generator that generates a third-order distortion of opposite polarity, a variable attenuator that changes the amplitude of the output of the distortion generator by a control signal,
A variable phase shifter that changes the phase shift amount of the output of the variable attenuator by a control signal, and a signal obtained by delaying the output of the variable phase shifter and the other signal divided into two by the distributor. A combiner, a power amplifier that power-amplifies the signal combined by the combiner and generates a transmission output, a first detector that extracts a part of the input signal and performs envelope detection, A second detector for extracting a part and detecting the envelope;
An error detector that outputs a distortion component, which is a difference between the output of the second detector and the distortion-free envelope detection output that is output from the detector as a reference signal, and an output from the error detector. A control unit that supplies the control signal such that the output distortion component becomes zero to the variable attenuator and the variable phase shifter, wherein the distortion generated in the power amplifier and becoming leakage power to an adjacent channel is provided. The components are configured to be offset by third-order distortion of the opposite polarity generated by the distortion generator.

【0013】[0013]

【発明の実施の形態】図1は本発明の実施例を示すブロ
ック図である。図において、分配器11と合成器17の
間のPD回路12と遅延線16、及び、電力増幅器1
8、方向性結合器19、検波器20は従来と同じであ
る。10は入力信号の一部を抽出する方向性結合器、2
3は抽出した入力信号を包絡線検波する検波器、24は
誤差検出器である。入力側の検出器23と出力側の検出
器20は、共に忠実に入力される信号を検波し、比較誤
差(歪成分)が確実に検出できるように、方向性結合器
または抵抗減衰器によって入力レベルがほぼ同じくなる
ように調整されている。
FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, a PD circuit 12 and a delay line 16 between a distributor 11 and a combiner 17 and a power amplifier 1
8. The directional coupler 19 and the detector 20 are the same as the conventional one. 10 is a directional coupler for extracting a part of the input signal, 2
Reference numeral 3 denotes a detector for detecting the envelope of the extracted input signal, and reference numeral 24 denotes an error detector. The detector 23 on the input side and the detector 20 on the output side both detect a signal that is faithfully input, and use a directional coupler or a resistive attenuator to detect the comparison error (distortion component) without fail. The levels have been adjusted to be almost the same.

【0014】誤差検出器24は、差動増幅回路で構成さ
れ、例えば、π/4シフトQPSKのデジタル変調され
た入力信号を検波器23で包絡線検波した無歪包絡線信
号を比較規準とし、送信出力を検波器20で包絡線検波
した信号との差(歪成分)を求めて制御部25に与え
る。制御部25は、その歪成分が零になるように可変減
衰器14と可変移相器15を制御する。
The error detector 24 is constituted by a differential amplifier circuit. For example, an error-free envelope signal obtained by envelope-detecting the digitally-modulated input signal of π / 4 shift QPSK by the detector 23 is used as a comparison criterion. A difference (distortion component) between the transmission output and the signal detected by the envelope detection by the detector 20 is obtained and given to the control unit 25. The control unit 25 controls the variable attenuator 14 and the variable phase shifter 15 so that the distortion component becomes zero.

【0015】上記のように、本発明では、入力信号の一
部を包絡線検波した無歪包絡線信号を規準信号とするこ
とによって従来のメモリを省略し、電力増幅された送信
出力の一部を包絡線検波した信号と比較して送信出力に
含まれる歪成分をとり出し、歪発生器13で発生した相
殺用の歪成分の振幅と位相を制御することによって送信
出力の歪を相殺し、電力増幅器18の電力効率を高めた
ことを要旨とするものである。
As described above, in the present invention, a conventional memory is omitted by using a distortion-free envelope signal obtained by envelope-detecting a part of an input signal as a reference signal, and a part of a power-amplified transmission output is obtained. Is compared with a signal obtained by envelope detection to extract a distortion component included in the transmission output, and cancel the distortion of the transmission output by controlling the amplitude and phase of the distortion component for cancellation generated by the distortion generator 13; The gist is to increase the power efficiency of the power amplifier 18.

【0016】図2は本発明の効果を示す送信出力の周波
数スペクトラムである。送信周波数f0 のプラス側隣接
チャネル((+)Adj.ch.)とマイナス側隣接チャネル
((−)Adj.ch.)における所定の帯域の電力、即ち、
隣接チャネル漏洩電力(ACP)は、補償“なし”のと
き((+)側−38.75dB、(−)側−38.00d
B)に対し、補償“あり”のとき((+)側−48.0
0dB、(−)側−49.25dB)となり、約10dBの改
善量が得られ、実用上極めて大きい改善結果が得られ
た。
FIG. 2 is a frequency spectrum of a transmission output showing the effect of the present invention. The power of a predetermined band in the plus side adjacent channel ((+) Adj.ch.) And the minus side adjacent channel ((−) Adj.ch.) Of the transmission frequency f 0 , that is,
The adjacent channel leakage power (ACP) is “-38.75 dB on the (+) side and −38.00 d on the (−) side when the compensation is“ none ”.
B), when compensation is present ((+) side -48.0)
0 dB, -49.25 dB on the (-) side), an improvement of about 10 dB was obtained, and an extremely large improvement in practical use was obtained.

【0017】図3は、前述のように、電力増幅器の入出
力特性にACPの特性を記入したものであり、補償“あ
り”のときのACPが、“なし”のときに比べて約10
dBの改善が得られている。歪改善量は、2〜3dBでも実
用上は低消費電力化の効果があることを考えれば、約1
0dBの改善は極めて著しい改善である。
FIG. 3 shows the characteristics of the ACP in the input / output characteristics of the power amplifier, as described above.
dB improvement has been obtained. The distortion improvement amount is about 1 in consideration of the effect of reducing power consumption even in the case of 2-3 dB.
The 0 dB improvement is a very significant improvement.

【0018】[0018]

【発明の効果】以上詳細に説明したように、本発明を実
施することにより、簡単な回路を付加するだけでメモリ
を省略できるので回路規模を縮小することができコスト
を下げることができる。さらに、多数の送信機を生産す
る場合の調整工数が削減され、装置のコスト低減に極め
て著しい効果を発揮する。さらに、本発明は、次世代移
動通信システムのW−CDMA(広帯域CDMA:Wide
band Code Division Multiple Access)システムにおい
ても適用することができる。
As described in detail above, by implementing the present invention, the memory can be omitted by simply adding a simple circuit, so that the circuit scale can be reduced and the cost can be reduced. Further, the number of adjustment steps when producing a large number of transmitters is reduced, which is extremely effective in reducing the cost of the apparatus. Further, the present invention provides a W-CDMA (Wideband CDMA) for a next generation mobile communication system.
band Code Division Multiple Access) system.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

【図2】本発明の効果を示す送信出力の周波数スペクト
ラムである。
FIG. 2 is a frequency spectrum of a transmission output showing the effect of the present invention.

【図3】本発明の効果を示す電力増幅器の入出力特性例
図である。
FIG. 3 is an example of input / output characteristics of a power amplifier showing the effects of the present invention.

【図4】従来の歪補償電力増幅回路のブロック図であ
る。
FIG. 4 is a block diagram of a conventional distortion compensation power amplifier circuit.

【符号の説明】[Explanation of symbols]

10,19 方向性結合器 11 分配器 12 PD回路 13 歪発生器 14 可変減衰器 15 可変移相器 16 遅延線 17 合成器 18 電力増幅器 20 検波器 21 制御部 22 メモリ 23 検波器 24 誤差検出器 25 制御部 DESCRIPTION OF SYMBOLS 10, 19 Directional coupler 11 Divider 12 PD circuit 13 Distortion generator 14 Variable attenuator 15 Variable phase shifter 16 Delay line 17 Synthesizer 18 Power amplifier 20 Detector 21 Control part 22 Memory 23 Detector 24 Error detector 25 Control part

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 ディジタル変調された単一キャリアの入
力信号を電力増幅して送信出力とする場合の電力増幅器
の非線形性によって発生し隣接チャネルに対する漏洩電
力となる歪成分を抑圧するために、 前記入力信号を2分配する分配器と、 該分配器で2分配された一方の信号を入力し、前記電力
増幅器の非線形性によって発生する歪と逆極性の3次歪
を発生させる歪発生器と、 該歪発生器の出力の振幅を制御信号によって変化させる
可変減衰器と、 該可変減衰器の出力の移相量を制御信号によって変化さ
せる可変移相器と、 該可変移相器の出力と前記分配器で2分配された他方の
信号を遅延させた信号とを合成する合成器と、 該合成器で合成された信号を電力増幅して送信出力とす
る電力増幅器と、 前記入力信号の一部を抽出して包絡線検波する第1の検
波器と、 前記送信出力の一部を抽出して包絡線検波する第2の検
波器と、 前記第1の検波器から出力される無歪の包絡線検波出力
を基準信号とし、前記第2の検波器の出力と比較してそ
の差である歪成分を出力する誤差検出器と、 該誤差検出器から出力される歪成分がゼロになるような
前記制御信号をそれぞれ前記可変減衰器と前記可変移相
器に与える制御部とが備えられ、 前記電力増幅器で発生し隣接チャネルに対する漏洩電力
となる前記歪成分が前記歪発生器によって発生させた逆
極性の3次歪によって相殺されるように構成された歪補
償電力増幅回路。
In order to suppress a distortion component which is generated due to nonlinearity of a power amplifier and becomes leakage power to an adjacent channel when a digitally modulated input signal of a single carrier is power-amplified as a transmission output, A splitter for splitting an input signal into two, a distortion generator for inputting one of the signals split by the splitter and generating a third-order distortion having a polarity opposite to that of a distortion caused by nonlinearity of the power amplifier; A variable attenuator that changes the amplitude of the output of the distortion generator by a control signal; a variable phase shifter that changes the amount of phase shift of the output of the variable attenuator by a control signal; and the output of the variable phase shifter A combiner that combines a signal obtained by delaying the other signal divided into two by the divider, a power amplifier that power-amplifies the signal combined by the combiner to generate a transmission output, and a part of the input signal Extract and envelope A first detector for detecting, a second detector for extracting a part of the transmission output and performing envelope detection, and a distortion-free envelope detection output output from the first detector as a reference signal. And an error detector that outputs a distortion component that is the difference between the output of the second detector and the control signal such that the distortion component output from the error detector becomes zero. A variable attenuator and a control unit for giving to the variable phase shifter, wherein the distortion component generated by the power amplifier and serving as leakage power to an adjacent channel is generated by the third-order distortion of the opposite polarity generated by the distortion generator. A distortion-compensated power amplifier circuit configured to cancel.
JP11065911A 1999-03-12 1999-03-12 Distortion compensation power amplification circuit Pending JP2000261252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11065911A JP2000261252A (en) 1999-03-12 1999-03-12 Distortion compensation power amplification circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11065911A JP2000261252A (en) 1999-03-12 1999-03-12 Distortion compensation power amplification circuit

Publications (1)

Publication Number Publication Date
JP2000261252A true JP2000261252A (en) 2000-09-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP11065911A Pending JP2000261252A (en) 1999-03-12 1999-03-12 Distortion compensation power amplification circuit

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Country Link
JP (1) JP2000261252A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1249930A2 (en) * 2001-04-10 2002-10-16 Matsushita Electric Industrial Co., Ltd. Predistortion linearizer and predistortion compensation method and program
US6720829B2 (en) 2001-12-25 2004-04-13 Matsushita Electric Industrial Co., Ltd. Distortion-compensated amplifying circuit
US6833758B2 (en) 2002-05-29 2004-12-21 Matsushita Electric Industrial Co., Ltd. Power amplifier
WO2005027340A1 (en) * 2003-09-10 2005-03-24 Hitachi Kokusai Electric Inc. Distortion compensating amplifier apparatus
US7209715B2 (en) 2002-07-30 2007-04-24 Matsushita Electric Industrial Co., Ltd. Power amplifying method, power amplifier, and communication apparatus
US7821337B2 (en) 2006-04-21 2010-10-26 Nec Corporation Power amplifier
US7877076B2 (en) 2004-09-29 2011-01-25 Nec Corporation Error calculation circuit for mixer
US7893787B2 (en) 2005-08-19 2011-02-22 Nec Corporation DC offset cancellation circuit for modulator using 1-bit signal conversion

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1249930A2 (en) * 2001-04-10 2002-10-16 Matsushita Electric Industrial Co., Ltd. Predistortion linearizer and predistortion compensation method and program
EP1249930A3 (en) * 2001-04-10 2004-06-02 Matsushita Electric Industrial Co., Ltd. Predistortion linearizer and predistortion compensation method and program
US7046972B2 (en) 2001-04-10 2006-05-16 Matsushita Electric Industrial Co., Ltd. Predistortion linearizer and predistortion distortion compensation method, program, and medium
US6720829B2 (en) 2001-12-25 2004-04-13 Matsushita Electric Industrial Co., Ltd. Distortion-compensated amplifying circuit
US6833758B2 (en) 2002-05-29 2004-12-21 Matsushita Electric Industrial Co., Ltd. Power amplifier
US6972621B2 (en) 2002-05-29 2005-12-06 Matsushita Electric Industrial Co., Ltd. Power amplifier
US7209715B2 (en) 2002-07-30 2007-04-24 Matsushita Electric Industrial Co., Ltd. Power amplifying method, power amplifier, and communication apparatus
WO2005027340A1 (en) * 2003-09-10 2005-03-24 Hitachi Kokusai Electric Inc. Distortion compensating amplifier apparatus
JPWO2005027340A1 (en) * 2003-09-10 2007-11-08 株式会社日立国際電気 Distortion compensation amplifier
US7877076B2 (en) 2004-09-29 2011-01-25 Nec Corporation Error calculation circuit for mixer
US7893787B2 (en) 2005-08-19 2011-02-22 Nec Corporation DC offset cancellation circuit for modulator using 1-bit signal conversion
US7821337B2 (en) 2006-04-21 2010-10-26 Nec Corporation Power amplifier

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