JP2000260998A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce resistance in a semiconductor layer having an silicon-on- insulator(SOI) structure and realize a high-speed dynamic threshold operation. SOLUTION: A gate electrode 30a is formed in the upper layer of a semiconductor layer formed in an active region on an insulation film 20 with a gate insulating film 21 in between that is formed on a substrate 12, and a source region 10b as well as a drain region 10c are formed in a semiconductor layer 10a on both sides of the gate electrode 30a. Furthermore, the semiconductor layers are formed in a manner such that their film thickness varies by every prescribed region within the active region, so that the film thicknesses of the semiconductor layer in the channel forming region and source region 10b are larger than that of the drain region 10c.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an SOI (Silicon On Insulator or
The present invention relates to a method for manufacturing a semiconductor device having a semiconductor layer having a semiconductor on insulator (miconductor on insulator) structure.

[0002]

2. Description of the Related Art MOS (Metal Oxide Semiconductor)
Or MIS (Metal Insulator Semiconductor) field effect transistor (MOSFET; MOS Field Effect T)
2. Description of the Related Art Semiconductor devices having a semiconductor layer having an SOI (Silicon On Insulator) structure have attracted attention with the development of high integration and high performance of an LSI on which a semiconductor device (ransistor) is mounted. In the SOI structure, complete element isolation is performed by an insulating film such as silicon oxide, so that soft errors and latch-up are suppressed, and high reliability can be obtained even in a highly integrated LSI. In addition, since the junction capacitance of the diffusion layer can be reduced, charging / discharging related to switching is reduced, which is advantageous for higher speed and lower power consumption.

A method of forming a semiconductor layer (hereinafter, also referred to as an SOI layer) formed on an insulating film on a substrate in the above-mentioned SOI structure can be roughly classified into a SIMOX method and a bonding method. SIMOX (Separation
The IMplanted OXygen method is a method in which oxygen is implanted at a high concentration deeply into a silicon substrate, and a buried oxide film is formed by heat treatment. According to this method, S
Although the OI layer has excellent thin film uniformity, there is a problem in crystallinity particularly in a region near the buried oxide film. On the other hand, the bonding method has excellent crystallinity of the SOI layer. However, after the bonding step, it is necessary to control the SOI layer to a desired film thickness by combining grinding, polishing, and the like. Not good.

In the above situation, in the bonding method, an SOI using an insulating film such as silicon oxide as a stopper is used.
A method has been developed to improve the uniformity of the thickness of the SOI layer by simultaneously controlling the film thickness by selective polishing of the layer and forming the element isolation insulating film. In the following, the SOI
A method for forming a semiconductor device having a MOSFET in a silicon semiconductor layer having a structure will be described.

FIG. 13 is a sectional view of a semiconductor device formed by the above method. An insulating film 20 made of, for example, silicon oxide is formed on the upper surface of the bonding surface S of the semiconductor substrate 12.
Is formed, and a semiconductor layer 10a made of single crystal silicon is buried in a trench T for element isolation formed on the upper surface thereof. Each semiconductor layer 10 a is separated from each other by the insulating film 20. A gate insulating film 21 made of silicon oxide is formed on an upper layer of the semiconductor layer 10a, and a gate electrode 30a made of, for example, polysilicon is formed thereon.
Are formed. A source diffusion layer 10b and a drain diffusion layer 10c are formed in the semiconductor layer 10a on the side of the gate electrode 30a, and a MOS field effect transistor having a channel formation region in the semiconductor layer 10a is formed as described above. ing.

A method for manufacturing the above semiconductor device will be described with reference to the drawings. First, as shown in FIG. 14A, a resist film R1 having a pattern for opening the element isolation region I is formed on the first silicon semiconductor substrate 10 by a photolithography process.

Next, as shown in FIG. 14B, etching such as RIE (reactive ion etching) is performed using the resist film R1 as a mask to form a trench T serving as an element isolation region.
Is formed to have a depth Y. After the etching, the resist film R1 is removed.

Next, as shown in FIG. 14C, silicon oxide is deposited on the entire surface of the trench T for element isolation by CVD (Chemical Vapor Deposition) to form an insulating film 20, for example.

Next, as shown in FIG. 15D, the upper surface of the insulating film 20 is subjected to CMP (Chemical Mechanical Polishing).
After flattening by the method or the like, the second silicon semiconductor substrate 12 is bonded to the upper layer.

Next, as shown in FIG. 15E, the first silicon semiconductor substrate 10 is removed from the side of the first silicon semiconductor substrate 10 by, eg, CMP.
Polishing is performed using the insulating film 20 as a stopper, and the semiconductor layer (SOI layer) 10a embedded in the isolation trench T is separated to form an SOI structure. Here, the drawing is drawn upside down from FIG. 15D.

Next, as shown in FIG. 16F, a gate insulating film 21 made of silicon oxide is formed on the surface of the semiconductor layer 10a by, for example, thermal oxidation, and then the upper layer of the gate insulating film is formed by, for example, CVD. Deposit polysilicon on
The gate electrode 30a is formed by processing into a gate electrode pattern.

Next, as shown in FIG. 16 (g), as the conductive impurity D1, for example, a p-type impurity such as boron when the semiconductor layer 10a is n-type, and a p-type impurity when the semiconductor layer 10a is p-type. An n-type impurity such as phosphorus is ion-implanted using the gate electrode 30a as a mask, and an impurity activation anneal process is performed to thereby perform source diffusion layer 10b and drain diffusion layer 1
0c is formed. Thus, a semiconductor device having a MOSFET having a channel formation region in the semiconductor layer 10a as shown in FIG. 13 is formed. In the subsequent steps, for example, a MOSFET is coated by a CVD method, silicon oxide is deposited, an interlayer insulating film is formed, and a gate electrode and a source electrode are formed.
A contact hole reaching a drain diffusion layer or the like is opened, and an upper wiring is formed with a metal material such as tungsten or aluminum to obtain a desired semiconductor device.

In a semiconductor device having a MOSFET having a channel formation region in the semiconductor layer which is the SOI layer, the SOI layer in a floating state is connected to a gate electrode to thereby form a dynamic threshold (Dynamic-Threshold). A method has been proposed in which the drain current is improved by using the operation.

[0014]

However, in the above-described semiconductor device, in order to connect the gate electrode to the SOI layer and perform the dynamic threshold operation at a high speed, the electric charge required in the SOI layer is sufficiently increased. However, depending on the semiconductor device, the gate width may be long and the resistance of the SOI layer may not be negligible.
High-speed dynamic threshold operation may be difficult.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to reduce the resistance of an SOI layer (a semiconductor layer above an insulating film) in a semiconductor device having an SOI structure. It is an object of the present invention to provide a semiconductor device capable of performing a dynamic threshold operation at a high speed when a gate electrode is connected to the semiconductor device, and a method of manufacturing the same.

[0016]

In order to achieve the above object, a semiconductor device according to the present invention comprises a substrate, an insulating film formed on the substrate, and a predetermined region formed on the insulating film. And a semiconductor layer formed to have a different thickness.

The semiconductor device according to the present invention is preferably
In a region where the thickness of the semiconductor layer is large, the insulating film thereunder is thin, and in a region where the thickness of the semiconductor layer is small, the insulating film thereunder is thick.

The semiconductor device of the present invention is preferably
The semiconductor layer has a first region having at least a first thickness;
A second region having a second film thickness larger than the first film thickness, wherein a conductive impurity concentration in the semiconductor layer in the first region is higher than a conductive impurity concentration in the semiconductor layer in the second region. It is formed higher than the impurity concentration.

The semiconductor device of the present invention is preferably
A channel formation region formed in the semiconductor layer; a source region and a drain region connected to the channel formation region; a gate insulating film formed on the semiconductor layer; and a gate insulating film formed on the gate insulating film. And a field effect transistor including the gate electrode. More preferably, the gate electrode is formed so as to be connected to the channel formation region.

The semiconductor device of the present invention is preferably
The thickness of the semiconductor layer in the source region and the drain region or the drain region is smaller than the thickness of the semiconductor layer in the channel formation region.

The semiconductor device of the present invention is preferably
At least the channel forming region, more preferably the conductive impurity concentration in the region near the interface with the insulating film in the semiconductor layer in the channel forming region and the source region,
It is formed to be higher than the conductive impurity concentration in the semiconductor layer in the other region.

In the above-described semiconductor device, in the semiconductor layer having the SOI structure, in a region where the thickness of the semiconductor layer is large, an underlying insulating film is thin, and in a region where the thickness of the semiconductor layer is small, the underlying insulating film is thin. The semiconductor layer is formed on the substrate such that the semiconductor layer has at least a first region and a second region that is thicker than the first film thickness and has a lower concentration of conductive impurities than the first region. The semiconductor layer is formed so as to have a different thickness for each predetermined region on the insulating film thus formed.

For example, a channel formation region is formed in a semiconductor layer, a gate electrode is formed above a semiconductor layer via a gate insulating film, and a source region and a drain region are formed in the semiconductor layer on both sides of the gate electrode. In addition, a field effect transistor capable of performing a dynamic threshold operation by connecting a gate electrode and a channel formation region is formed. In the above-described field-effect transistor, for example, the thickness of the semiconductor layer in the source region and the drain region or in the drain region is formed smaller than the thickness of the semiconductor layer in the channel formation region. In a field-effect transistor, for example, the concentration of conductive impurities in a region near an interface with an insulating film in a semiconductor layer in at least a channel formation region, more preferably in a channel formation region and a source region, is higher than that in a semiconductor layer in another region. Of the conductive impurities.

According to the above-described semiconductor device, the semiconductor layer is formed so as to have a different thickness in each of the predetermined regions. A portion having a large thickness and a low resistance can be provided. Therefore, for example, in a field-effect transistor that performs a dynamic threshold operation, the thickness of the semiconductor layer in the channel formation region and the source region can be increased to reduce the resistance.
The threshold operation can be performed at high speed. In addition, by setting the conductive impurity concentration in the region near the interface between the thickened region and the insulating layer of the semiconductor layer higher than in other regions, the resistance of the semiconductor layer can be reduced.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a plurality of steps on a surface of a first substrate made of a semiconductor; The first on the first substrate continuing to the step
Forming an insulating film, bonding a second substrate from the upper surface of the first insulating film, and polishing the first substrate while leaving a semiconductor layer in the active region portion of the first substrate. Have.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having an element isolation region and an active region adjacent to the element isolation region. Forming an element isolation groove in an element isolation region of the first substrate, forming a step shallower than the groove in a predetermined region in the active region of the first substrate to reduce the thickness, Forming a first insulating film on the first substrate on the step and on the first substrate adjacent to the groove and the step; bonding a second substrate from an upper surface of the first insulating film; Polishing the first substrate while leaving the semiconductor layer in the active region portion of the first substrate using the first insulating film as a stopper.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, after the step of forming the first insulating film, before the step of bonding the second substrate, the method further includes a step of flattening the first insulating film by a chemical mechanical polishing process or the like. Alternatively, preferably, after the step of forming the first insulating film, before the step of bonding the second substrate, a step of forming a bonding layer such as a polysilicon layer on the first insulating film is further included. And a step of flattening the bonding layer by a chemical mechanical polishing process or the like before the step of bonding the second substrate.

The method of manufacturing a semiconductor device according to the present invention is as follows.
Preferably, after the step of polishing the first substrate, the first substrate
A step of forming a gate insulating film on an upper layer of the semiconductor layer in the active region portion left by the step of polishing the substrate, and a step of forming a gate electrode on the upper layer of the gate insulating film,
A conductive impurity is introduced using the gate electrode as a mask,
Forming a source region and a drain region in the semiconductor layer; More preferably, in the step of forming the drain region or the step of forming the drain region and the source region, a step shallower than the groove is formed and the semiconductor layer left in the thinned region is formed. Form.

The method of manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, after the step of forming the first insulating film, and before the step of bonding the second substrate, a step shallower than the groove is formed in an active region of a region except a region thinned. Removing the first insulating film from the upper surface until the first substrate is exposed; introducing a conductive impurity of the same conductivity type as the first substrate into the exposed surface layer of the first substrate; A second substrate is formed on the first substrate and the first insulating film.
The method further includes the step of forming an insulating film. In the step of bonding the second substrate, the second substrate is bonded from an upper surface of the second insulating film.

The method for manufacturing a semiconductor device according to the present invention described above comprises:
Preferably, after the step of forming the second insulating film, before the step of bonding the second substrate, the method further includes a step of flattening the second insulating film by a chemical mechanical polishing process or the like. Alternatively, preferably, after the step of forming the second insulating film, before the step of bonding the second substrate, a step of forming a bonding layer such as a polysilicon layer on the second insulating film is further included. And a step of flattening the bonding layer by a chemical mechanical polishing process or the like before the step of bonding the second substrate.

In the above-described method for manufacturing a semiconductor device, an element isolation groove is formed in an element isolation region of a first substrate made of a semiconductor, and a step smaller than the groove is formed in a predetermined region in an active region of the first substrate. The first
A plurality of steps are formed on the surface of the substrate. Next, a first insulating film is formed on a plurality of steps including the inside of the element isolation groove and on a first substrate continuous with the steps, and is flattened by a chemical mechanical polishing process or the like, or After forming a bonding layer such as a polysilicon layer and flattening this layer by chemical mechanical polishing or the like, the second substrate is bonded from the upper surface of the first insulating film, and the first insulating film in the element isolation region is stoppered. Then, the first substrate is polished while leaving the semiconductor layer in the active region portion of the first substrate. With the above, SO
As the semiconductor layer having the I structure, a semiconductor layer formed to have a different thickness in each predetermined region can be formed.

Further, after forming the first insulating film on the first substrate, a step shallower than the groove is formed until the first substrate in the active region other than the thinned region is exposed until the first substrate is exposed. The insulating film is removed from the upper surface, a conductive impurity of the same conductivity type as that of the first substrate is introduced into the exposed surface layer of the first substrate, and a second insulating film is formed over the first substrate and the first insulating film. . In this case, after the second insulating film is flattened by a chemical mechanical polishing process or the like, or after a bonding layer such as a polysilicon layer is formed and this layer is flattened by a chemical mechanical polishing process or the like. From the upper surface of the second insulating film,
The substrates are bonded together, and the first substrate is polished while leaving the semiconductor layer in the active region of the first substrate. After the first substrate is polished while leaving the semiconductor layer in the active region portion as described above, a gate insulating film is formed on the semiconductor layer in the active region portion,
A gate electrode is formed over the gate insulating film, a conductive impurity is introduced using the gate electrode as a mask, and a source region and a drain region are formed in the semiconductor layer. Here, the drain region or the drain region and the source region are formed in the semiconductor layer left in the thinned region by forming a step shallower than the groove.

According to the method of manufacturing a semiconductor device described above, S
As the semiconductor layer having the OI structure, a semiconductor layer formed to have a different thickness in each predetermined region can be formed.
That is, the thickness of the semiconductor layer is reduced in a portion where a step is formed shallower than the groove in a predetermined region in the active region of the first substrate, and the thickness of the semiconductor layer is reduced in a region where the step is not formed. It can be formed thick. Therefore, a portion having a large thickness of the semiconductor layer and a low resistance can be formed with respect to a portion having a high resistance because the thickness of the semiconductor layer is small. Therefore, for example, in a field-effect transistor that performs a dynamic threshold operation, the thickness of the semiconductor layer in the channel formation region and the source region can be increased to reduce the resistance, thereby increasing the speed of the dynamic threshold operation. Can be done. In addition, by introducing conductive impurities of the same conductivity type as that of the first substrate (semiconductor layer) into the semiconductor layer left thick in a region where no step is formed, an interface between the semiconductor layer and the insulating film is formed. The conductive impurity concentration in the nearby region can be higher than that in other regions, and the resistance of the semiconductor layer can be reduced.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIG. 1 is a sectional view of a semiconductor device according to this embodiment. An insulating film 20 made of, for example, silicon oxide is formed on the upper surface of the bonding surface S of the semiconductor substrate 12, and is used for adjusting the film thickness of the semiconductor layer having the SOI structure in the trench T1 for element isolation formed on the upper surface. The semiconductor layer 10a made of single crystal silicon is embedded on the step T2. Each semiconductor layer 10 a is separated from each other by the insulating film 20. A gate insulating film 21 made of silicon oxide is formed on the semiconductor layer 10a, and a gate electrode 30a made of, for example, polysilicon is formed on the gate insulating film 21. A source diffusion layer 10b and a drain diffusion layer 10c are formed in the semiconductor layer 10a on the side of the gate electrode 30a, and a MOS field effect transistor having a channel formation region in the semiconductor layer 10a is formed as described above. ing. Here, the channel forming region and the source diffusion layer 1
0b, the film thickness X of the semiconductor layer is
It is formed thicker than the film thickness Y of the semiconductor layer at c. Correspondingly, the thickness of the insulating film below the region where the thickness of the semiconductor layer is large is thinner than the thickness of the insulating film below the region where the thickness of the semiconductor layer is small, and The films are formed so that the sum of the film thicknesses is equal in each region, whereby the surface of the semiconductor layer is planarized. Further, the gate electrode 30a is connected to a channel formation region in the semiconductor layer 10a by a contact connection portion (not shown) or the like, so that a dynamic threshold operation can be performed.

In the above-described semiconductor device, the SOI type semiconductor layer is formed so that the channel formation region and the source diffusion layer and the drain diffusion layer have different thicknesses, and the thickness of the semiconductor layer in the drain diffusion layer 10c is different. The thickness of the semiconductor layer in the channel formation region and the source diffusion layer 10b is larger than that of the portion having a higher resistance due to the smaller thickness.
This part has low resistance. Therefore, since the resistance of the semiconductor layers in the channel formation region and the source region is reduced, the dynamic threshold operation can be performed at high speed.

The method of manufacturing the above semiconductor device will be described with reference to the drawings. First, as shown in FIG.
A resist having a pattern for opening an element isolation region I on a first silicon semiconductor substrate 10 by a photolithography process and protecting first and second active regions (AR1, AR2) to be a channel formation region, a source region, and a drain region The film R1 is formed.

Next, as shown in FIG. 2B, etching such as RIE (reactive ion etching) is performed using the resist film R1 as a mask to form a trench T serving as an element isolation region.
1 is formed to have a depth X. After the etching, the resist film R1 is removed.

Next, as shown in FIG. 3C, a first active region A serving as a drain region of a MOSFET is formed on the first silicon semiconductor substrate 10 by a photolithography process.
An opening is formed in R1, and a resist film R2 having a pattern for protecting the second active region AR2 serving as a channel formation region and a source region is formed.

Next, as shown in FIG. 3D, etching such as RIE is performed using the resist film R2 as a mask.
A step T2 shallower than the trench T1 is formed to have a depth Z (= XY), and the first silicon semiconductor substrate 10 in the first active region AR1 is thinned. After the etching, the resist film R2 is removed.

Next, as shown in FIG.
By VD (Chemical Vapor Deposition) method, silicon oxide is deposited in a thickness of about 1 μm on the entire surface in the element isolation trench T1, on the step T2, and on the first silicon semiconductor substrate 10 continuous to the trench and the step, and is insulated. The film 20 is formed. If necessary, a polysilicon layer (not shown) having a thickness of about 2 to 10 μm may be formed on the insulating film 20 by, for example, a CVD method so as to easily perform a planarization process in a later step.

Next, as shown in FIG.
0 or a polysilicon layer (not shown) is formed by CMP (Chemical M).
echanical Polishing), flattening by etch-back or reflow, etc.
First, the silicon semiconductor substrate 12 is bonded by van der Waals force, and the bonding surface is fixed by dehydration polymerization of the bonding interface by, for example, annealing at 1100 ° C. for 2 hours.

Next, as shown in FIG.
The semiconductor layer (SOI layer) 1 polished from the side of the first silicon semiconductor substrate 10 by the MP method using the insulating film 20 as a stopper and embedded in the element isolation trench T1 and the step T2.
0a to form an SOI structure. Here, the drawing is drawn upside down from FIG. 4 (f). Here, the thickness of the semiconductor layer in the first active region AR1 is Y,
The film thickness in the second active region AR2 is X.

Next, as shown in FIG. 5H, after ion implantation of impurities for adjusting the threshold value as necessary, a gate insulating film made of silicon oxide is formed on the surface of the semiconductor layer 10a by, for example, thermal oxidation. 21 and then, for example, CVD
A polysilicon layer 30 is deposited on the gate insulating film by a method.

Next, as shown in FIG. 6I, a resist film having a gate electrode pattern (not shown) is formed, and an etching process such as RIE is performed to process the polysilicon layer 30 into a gate electrode pattern. Form 30a.

Next, as shown in FIG. 6 (j), as the conductive impurity D1, for example, when the semiconductor layer 10a is n-type, a p-type impurity such as boron (for example, BF ₂ ) and the semiconductor layer 10a are p-type impurities. In the case of the type, an n-type impurity such as phosphorus or arsenic is applied at 3 × 10 ¹⁵ at using the gate electrode 30a as a mask.
Ion implantation is performed at a dose of oms / cm ² , and impurity activation annealing is performed to form a source diffusion layer 10b and a drain diffusion layer 10c. As described above, the MOSFET having the channel formation region in the semiconductor layer 10a as shown in FIG.
Is formed. As the subsequent steps,
For example, a gate for performing a dynamic threshold operation by covering a MOSFET by CVD method, depositing silicon oxide to form an interlayer insulating film, opening a contact hole reaching a gate electrode, a source / drain diffusion layer, and the like. A desired semiconductor device is obtained by forming an upper wiring including a metal material such as tungsten or aluminum, including an upper wiring for connecting an electrode and a channel formation region.

According to the above-described method of manufacturing a semiconductor device, a step shallower than a trench for element isolation is formed in a first active region of a first silicon semiconductor substrate, and a semiconductor layer having an SOI structure is formed between this region and another region. Can be formed to have different thicknesses. That is, the thickness of the semiconductor layer in the first active region can be reduced, and the thickness of the semiconductor layer can be increased in the second active region where no step is formed. Therefore,
A second active region, which is a channel forming region and a source region having a thick semiconductor layer and a low resistance, is formed with respect to a first active region which is a drain region having a high resistance because the thickness of the semiconductor layer is small. be able to. Therefore, for example, in a field-effect transistor that performs a dynamic threshold operation, the thickness of the semiconductor layer having the SOI structure in the channel formation region and the source region can be increased to reduce the resistance. Can be performed at high speed.

Second Embodiment FIG. 7 is a sectional view of a semiconductor device according to the second embodiment . The semiconductor device of the present embodiment is substantially the same as the semiconductor device of the first embodiment, except that the concentration of conductive impurities in the region 10d near the interface with the insulating film in the semiconductor layer 10a in the channel formation region and the source region is reduced. Semiconductor layer 1 in another region
The only difference is that it is formed higher than the conductive impurity concentration in Oa.

In the above-described semiconductor device, the SOI type semiconductor layer has a different thickness in the channel formation region and the source diffusion layer and the drain diffusion layer, and the channel formation region is different from the thickness of the semiconductor layer in the drain diffusion layer 10c. In addition, since the thickness of the semiconductor layer in the source diffusion layer 10b is large and low in resistance, the dynamic threshold operation can be performed at high speed. Further, the resistance of the semiconductor layer can be further reduced by setting the conductive impurity concentration in the channel formation region and the region near the interface between the semiconductor layer and the insulating film in the source diffusion layer 10b higher than in other regions.

A method for manufacturing the above semiconductor device will be described with reference to the drawings. First, the structure up to the structure shown in FIG. 8A is the same as that of the first embodiment. That is, a resist film having a pattern for opening the element isolation region I is formed on the first silicon semiconductor substrate 10 by a photolithography process, and is subjected to etching such as RIE (reactive ion etching) to form a groove to be an element isolation region. T1 is formed to have a depth X, then a resist film having a pattern for opening the first active region AR1 is formed, and etching such as RIE is performed to form a step T2 shallower than the trench T1 to a depth Z ( = X
-Y). Next, silicon oxide is deposited to a thickness of about 1 μm on the entire surface in the element isolation trench T1, on the step T2, and on the first silicon semiconductor substrate 10 continuous with the trench and the step by, for example, the CVD method.
An insulating film 20 is formed.

Next, as shown in FIG.
The first insulating film 20 is removed by etching such as IE or polishing treatment such as a CMP method until the first silicon semiconductor substrate in the second active region is exposed.

Next, as shown in FIG. 9C, as the conductive impurity D2, for example, when the first silicon semiconductor substrate 10 is p-type, a p-type impurity such as boron (for example, BF ₂ ) is used. When the silicon semiconductor substrate 10 is an n-type, an n-type impurity such as phosphorus or arsenic is ion-implanted, and an activation anneal treatment of the impurity is performed. The conductive impurity concentration in the region 10d near the interface is introduced higher than the conductive impurity concentration in the semiconductor layer in the other region.

Next, as shown in FIG.
The first silicon semiconductor substrate 10 and the first silicon
Silicon oxide is deposited on the entire surface of the insulating film 20 to form a second insulating film 22. If necessary, a polysilicon layer (not shown) is formed on the second insulating film 22 by a CVD method, for example, so that a flattening process, which is a post-process, is facilitated.
It may be formed with a film thickness of about 0 μm.

Next, as shown in FIG. 10E, when the upper surface of the second insulating film 22 or the polysilicon layer (not shown) is formed, the upper surface of the polysilicon layer is subjected to the CMP method and the etch-back process. Alternatively, after flattening by a reflow process or the like, the second silicon semiconductor substrate 12 is first bonded to the upper layer by van der Waals force,
The bonding surface is fixed by dehydration polymerization of the bonding interface by annealing at 100 ° C. for 2 hours.

Next, as shown in FIG. 10F, the first silicon semiconductor substrate 10 is removed from the side of the first silicon semiconductor substrate 10 by, for example, the CMP method.
The semiconductor layer (SOI) polished by using the first insulating film 20 as a stopper and buried in the isolation trench T1 and the step T2.
(Layer) 10a to form an SOI structure. here,
The drawing is drawn upside down from FIG. 10 (e). Here, the thickness of the semiconductor layer in the first active region AR1 is Y, and the thickness in the second active region AR2 is X.

Next, as shown in FIG. 11 (g), a gate insulating film 21 made of silicon oxide is formed on the surface of the semiconductor layer 10a by, for example, thermal oxidation, and then the upper layer of the gate insulating film is formed by, for example, CVD. Then, a polysilicon layer is deposited and processed into a gate electrode pattern to form a gate electrode 30a.

Next, as shown in FIG. 11H, as the conductive impurity D1, for example, when the semiconductor layer 10a is n-type, a p-type impurity such as boron (for example, BF ₂ ) and the semiconductor layer 10a are p-type impurities. In the case of the type, an n-type impurity such as phosphorus or arsenic is used, and 3 × 10 ¹⁵
Ion implantation is performed at a dose of atoms / cm ² , and activation annealing of impurities is performed to form a source diffusion layer 10b and a drain diffusion layer 10c. As described above, the MOSFE having the channel formation region in the semiconductor layer 10a as shown in FIG.
A semiconductor device having T is formed. In the subsequent steps, for example, a MOSFET is coated by a CVD method, silicon oxide is deposited, an interlayer insulating film is formed, a contact hole reaching a gate electrode, a source / drain diffusion layer, and the like is opened, and a dynamic threshold is formed. A desired semiconductor device is formed by forming an upper wiring using a metal material such as tungsten or aluminum, including an upper wiring for connecting a gate electrode for operation and a channel formation region.

According to the above-described method of manufacturing a semiconductor device, a step shallower than the trench for element isolation is formed in the first active region of the first silicon semiconductor substrate, and the thickness of the semiconductor layer in the first active region is reduced. Then, in the second active region, the thickness of the semiconductor layer is formed to be large, a channel forming region and a source region having low resistance with respect to the first active region are formed, and the dynamic threshold operation is performed at high speed. Field effect transistors that can be formed. Also,
By forming the conductive impurity concentration in the channel formation region and the region near the interface between the semiconductor layer and the insulating film in the source diffusion layer 10b higher than other regions, the resistance of the semiconductor layer can be further reduced.

Third Embodiment FIG. 12 is a sectional view of a semiconductor device according to the third embodiment .
The semiconductor device of the present embodiment is substantially the same as the semiconductor device of the first embodiment, except that the thickness X of the semiconductor layer in the channel formation region is different from the thickness of the semiconductor layer in the source diffusion layer 10b and the drain diffusion layer 10c. The only difference is that it is formed thicker than the thickness Y.

The semiconductor device of the present embodiment can be formed in the same manner as in the first embodiment. That is, the first
It can be formed in the same manner as in the manufacturing method of the first embodiment, except that a region to be a source / drain diffusion layer is set as an active region and a region to be a channel formation region is set as a second active region.

In the semiconductor device according to the present embodiment, similarly to the semiconductor device of the first embodiment, the SOI type semiconductor layer has a different film thickness between the channel formation region and the source diffusion layer and the drain diffusion layer, Since the thickness of the semiconductor layer in the channel formation region and the source diffusion layer 10b is larger than the thickness of the semiconductor layer in the layer 10c and the resistance is low, the dynamic threshold operation can be performed at high speed.

The semiconductor device of the present invention can be applied to any semiconductor device having an SOI type semiconductor layer.
In particular, the present invention can be preferably applied to a semiconductor device having a MOSFET which performs a dynamic threshold operation by connecting a gate electrode and a channel formation region over an SOI semiconductor layer.

The present invention is not limited to the above embodiment. For example, in the semiconductor device of the above embodiment,
A sidewall insulating film serving as an LDD spacer on both sides of the gate electrode is formed, and a conductive impurity is ion-implanted before and after the formation of the sidewall insulating film, thereby forming a so-called LDD (Lightly Doped Drain) structure.
It is also possible to form a drain diffusion layer. In addition, a salicide (Self Aligned Silicide) for forming a metal silicide layer such as cobalt silicide or titanium silicide in a self-aligned manner on the upper surface of the source / drain diffusion layer.
) It is possible to further reduce the resistance by using the process. Further, each of the gate electrode, the first insulating film, the second insulating film, and the like may have a single-layer structure or a multilayer structure. In addition, various changes can be made without departing from the spirit of the present invention.

[0064]

As described above, according to the semiconductor device of the present invention, in the semiconductor device having the SOI structure, the SOI
The resistance of the layer (the semiconductor layer above the insulating film)
When the gate electrode is connected to the layer, the dynamic threshold operation can be performed at high speed.

Further, according to the method of manufacturing a semiconductor device of the present invention, the semiconductor device of the present invention can be easily manufactured, and the resistance of the SOI layer (the semiconductor layer above the insulating film) can be reduced. A semiconductor device that performs a dynamic threshold operation at high speed when a gate electrode is connected to the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor device according to the first embodiment. FIG. 2A illustrates a process up to a step of forming a resist film that opens an element isolation region, and FIG. The steps up to the step of forming a separation groove are shown.

FIG. 3 shows a step that follows the step shown in FIG. 2;
(D) up to the step of forming a resist film that opens the active region.
Shows the steps up to the step of forming the step in the first active region.

FIG. 4 shows a step subsequent to that of FIG. 3; (e) shows a step until an insulating film is formed; and (f) shows a step until a bonding step of a second substrate.

FIG. 5 shows a step that follows the step shown in FIG. 4;
(H) shows a process up to the step of forming a SOI layer by polishing a silicon semiconductor substrate, and (h) shows a process up to a process of forming a polysilicon layer serving as a gate electrode.

6 shows a step subsequent to that of FIG. 5; (i) shows up to a gate electrode patterning step; and (j) shows a source / drain diffusion layer forming step.

FIG. 7 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIGS. 8A and 8B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor device according to a second embodiment, in which FIG. 8A illustrates up to a step of forming a first insulating film, and FIG. The steps up to the step of exposing the first substrate are shown.

FIG. 9 shows a step that follows the step in FIG. 8;
(D) shows the process up to the step of increasing the impurity concentration in the region near the interface with the insulating film in the active region, and (d) shows the process up to the process of forming the second insulating film.

10 shows a step subsequent to that of FIG. 9; FIG. 10 (e) shows a step up to a bonding step of a second substrate; and FIG. 10 (f) shows a step up to a step of forming an SOI layer by polishing the first silicon semiconductor substrate.

FIG. 11 shows a step that follows the step in FIG. 10, and (g)
Shows the steps up to the step of patterning the gate electrode, and (h) shows the steps up to the step of forming the source / drain diffusion layers.

FIG. 12 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 13 is a sectional view of a semiconductor device according to a conventional example.

14A and 14B are cross-sectional views showing a manufacturing process of a method of manufacturing a semiconductor device according to a conventional example, in which FIG. 14A shows up to a step of forming a resist film for opening an element isolation region, and FIG. (C) up to the step of forming the insulating film.

FIG. 15 shows a step that follows the step shown in FIG. 14, and (d)
FIG. 4A shows the process up to the step of bonding the second substrate, and FIG. 4E shows the process up to the process of forming the SOI layer by polishing the first silicon semiconductor substrate.

FIG. 16 shows a step that follows the step shown in FIG. 15;
Shows the steps up to the step of patterning the gate electrode, and (g) shows the steps up to the step of forming the source / drain diffusion layers.

[Explanation of symbols]

10: first silicon semiconductor substrate, 10a: semiconductor layer (S
OI layer), 10b: source diffusion layer, 10c: drain diffusion layer, 10d: region near the interface with the insulating film in the semiconductor layer,
12: second silicon semiconductor substrate, 20: first insulating film, 2
DESCRIPTION OF SYMBOLS 1 ... Gate insulating film, 22 ... Second insulating film, 30 ... Polysilicon layer, 30a ... Gate electrode, D1, D2 ... Conductive impurities, R1, R2 ... Resist film, T1 ... Element isolation groove, T
2: step, S: bonding surface, I: element isolation region, AR
1: first active region, AR2: second active region

Continued on the front page F-term (reference)

Claims (27)

[Claims] 1. A semiconductor device comprising: a substrate; an insulating film formed on the substrate; and a semiconductor layer formed on the insulating film and having a different thickness for each predetermined region. 2. The semiconductor device according to claim 1, wherein said insulating film is thinner in a region where said semiconductor layer is thicker, and said insulating film is thicker in a region where said semiconductor layer is thinner. 2. The semiconductor device according to 1. 3. The semiconductor layer has at least a first region having a first film thickness and a second region having a second film thickness larger than the first film thickness. The conductive impurity concentration in the semiconductor layer,
The semiconductor device according to claim 1, wherein the semiconductor device is formed to be higher than a conductive impurity concentration in the semiconductor layer in the second region. 4. A channel forming region formed in the semiconductor layer, a source region and a drain region connected to the channel forming region, a gate insulating film formed on the semiconductor layer, and the gate insulating film. 2. The semiconductor device according to claim 1, wherein a field effect transistor including a gate electrode formed in an upper layer is formed. 5. The semiconductor device according to claim 4, wherein said gate electrode is formed so as to be connected to said channel formation region. 6. The semiconductor device according to claim 4, wherein the thickness of the semiconductor layer in the drain region is smaller than the thickness of the semiconductor layer in the channel formation region. 7. The semiconductor device according to claim 4, wherein the thickness of the semiconductor layer in the source region and the drain region is smaller than the thickness of the semiconductor layer in the channel formation region. 8. The semiconductor device according to claim 1, wherein a conductive impurity concentration in at least a region near an interface with said insulating film in said semiconductor layer in said channel formation region is formed higher than a conductive impurity concentration in said semiconductor layer in another region. The semiconductor device according to claim 4. 9. A conductive impurity concentration in a region near an interface with the insulating film in the semiconductor layer in the channel formation region and the source region is higher than a conductive impurity concentration in the semiconductor layer in another region. 9. The semiconductor device according to claim 8, wherein the semiconductor device is formed. 10. A step of forming a plurality of steps on a surface of a first substrate made of a semiconductor, and forming a first insulating film on the steps of the first substrate and on the first substrate continuous with the steps. Manufacturing a semiconductor device, comprising: bonding a second substrate from an upper surface of the first insulating film; and polishing the first substrate while leaving a semiconductor layer in the active region portion of the first substrate. Method. 11. A method of manufacturing a semiconductor device having an element isolation region and an active region adjacent to the element isolation region, comprising the steps of: forming an element isolation groove in an element isolation region of a first substrate made of a semiconductor; Forming a step shallower than the groove in a predetermined region in the active region of the first substrate to reduce the thickness; and forming a step in the groove, on the step, and on the first substrate continuous with the groove and the step. Forming a first insulating film on the substrate; bonding a second substrate from an upper surface of the first insulating film; and using the first insulating film in the element isolation region as a stopper, the active region portion of the first substrate. Polishing the first substrate while leaving the semiconductor layer as described above. 12. The semiconductor device according to claim 11, further comprising a step of flattening said first insulating film after said step of forming said first insulating film and before said step of bonding said second substrate. Production method. 13. The method according to claim 12, wherein the step of flattening the first insulating film is a chemical mechanical polishing process. 14. The method according to claim 11, further comprising, after the step of forming the first insulating film, and before the step of bonding the second substrate, forming a bonding layer on the first insulating film. Of manufacturing a semiconductor device. 15. The method according to claim 14, wherein a polysilicon layer is formed as the bonding layer. 16. After the step of forming the bonding layer,
The method of manufacturing a semiconductor device according to claim 14, further comprising a step of flattening the bonding layer before the step of bonding the second substrate. 17. The method according to claim 16, wherein the step of flattening the bonding layer is a chemical mechanical polishing step. 18. After the step of polishing the first substrate, a step of forming a gate insulating film on the semiconductor layer in the active region portion left by the step of polishing the first substrate; 12. The semiconductor device according to claim 11, further comprising: a step of forming a gate electrode in a layer above the film; and a step of introducing a conductive impurity using the gate electrode as a mask to form a source region and a drain region in the semiconductor layer. Production method. 19. The method of manufacturing a semiconductor device according to claim 18, wherein in the step of forming the drain region, a step shallower than the groove is formed in the semiconductor layer left in the thinned region. . 20. The semiconductor device according to claim 18, wherein, in the step of forming the source region and the drain region, a step which is shallower than the groove is formed in a semiconductor layer left in a thinned region. Manufacturing method. 21. After the step of forming the first insulating film and before the step of bonding the second substrate, an active region of a region except a region which is formed thinner by forming a step shallower than the groove. Removing the first insulating film from the upper surface until the first substrate is exposed, and introducing a conductive impurity of the same conductivity type as the first substrate into a surface layer portion of the exposed first substrate, Forming a second insulating film on the first substrate and the first insulating film; and bonding the second substrate to the second insulating film.
2. The method according to claim 1, wherein the second substrate is bonded from an upper surface of the insulating film.
9. The method for manufacturing a semiconductor device according to item 8. 22. The semiconductor device according to claim 21, further comprising a step of flattening the second insulating film after the step of forming the second insulating film and before the step of bonding the second substrate. Production method. 23. The method according to claim 22, wherein the step of flattening the second insulating film is a chemical mechanical polishing step. 24. The method according to claim 21, further comprising, after the step of forming the second insulating film, and before the step of bonding the second substrate, a step of forming a bonding layer on the second insulating film. Of manufacturing a semiconductor device. 25. The method according to claim 24, wherein a polysilicon layer is formed as the bonding layer. 26. After the step of forming the bonding layer,
The method of manufacturing a semiconductor device according to claim 24, further comprising a step of flattening the bonding layer before the step of bonding the second substrate. 27. The method according to claim 26, wherein the step of flattening the bonding layer is a chemical mechanical polishing step.