JP2000260913A - Electrode of semiconductor device - Google Patents
Electrode of semiconductor deviceInfo
- Publication number
- JP2000260913A JP2000260913A JP6641999A JP6641999A JP2000260913A JP 2000260913 A JP2000260913 A JP 2000260913A JP 6641999 A JP6641999 A JP 6641999A JP 6641999 A JP6641999 A JP 6641999A JP 2000260913 A JP2000260913 A JP 2000260913A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor device
- intermediate substrate
- solder
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、多数の格子状に配
列したハンダボール状の電極を中間基板底面に有した半
導体装置および混成集積回路のハンダ付け強度を向上さ
せるための半導体装置の電極構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a large number of solder ball-shaped electrodes arranged on a bottom surface of an intermediate substrate and an electrode structure of a semiconductor device for improving the soldering strength of a hybrid integrated circuit. It is about.
【０００２】[0002]
【従来の技術】従来、半導体装置および混成集積回路の
被実装基板への実装電極部には金属製リードが多用され
ていたが、入出力端子数の増加に対してリードピッチの
ファイン化に限界があることから、近年はパッケージ下
面に格子状に電極を配することにより、多ピン、広ピッ
チ、小型化を実現するＢＧＡ（ＢａｌｌＧｒｉｄ Ａｒ
ｒａｙ）の端子構造が次第に多用されるようになってき
ている。2. Description of the Related Art Conventionally, metal leads are frequently used for mounting electrodes of a semiconductor device and a hybrid integrated circuit on a mounting substrate. However, as the number of input / output terminals increases, there is a limit to finer lead pitch. Therefore, in recent years, a BGA (Ball Grid Ar) that realizes a multi-pin, wide pitch, and miniaturization by arranging electrodes in a grid pattern on the lower surface of the package has been recently developed.
(Ray) terminal structure is increasingly used.
【０００３】以下、従来のＢＧＡ、ＣＳＰ（Ｃｈｉｐ
Ｓｉｚｅ Ｐａｃｋａｇｅ）を例に構造を説明する。図
５は従来の半導体装置および混成集積回路の電極の断面
図である。図５において１は半導体チップ、２は材質が
ポリイミドの基板材料で、所望の形状に加工した中間基
板部、３は第１電極部であって、中間基板２に接着剤で
張り付けられた銅箔をエッチングでパターンや電極とし
て形成した回路の中でパッケージ外との電気的接続を行
い、一定の間隔で格子状に配置され、中間基板２の開口
部を通して反対の面側からも電極表面が露出する構造と
なっている。４は基板電極とパッケージ間の導通と固定
を行うハンダボール、５は中間基板２に半導体チップ１
を固定するための接着剤、６は半導体チップ１の電極と
中間基板２上の電極との導通を行うＡｕワイヤ、７は半
導体チップやＡｕワイヤ６を保護するための封止樹脂で
ある。[0003] Conventional BGA, CSP (Chip)
The structure will be described by taking Size Package) as an example. FIG. 5 is a cross-sectional view of electrodes of a conventional semiconductor device and a hybrid integrated circuit. In FIG. 5, 1 is a semiconductor chip, 2 is a substrate material made of polyimide, an intermediate substrate portion processed into a desired shape, and 3 is a first electrode portion, which is a copper foil adhered to the intermediate substrate 2 with an adhesive. Are electrically connected to the outside of the package in a circuit formed as a pattern or an electrode by etching, are arranged in a grid at regular intervals, and the electrode surface is also exposed from the opposite surface side through the opening of the intermediate substrate 2 It has a structure to do. 4 is a solder ball for conducting and fixing between the substrate electrode and the package, and 5 is a semiconductor chip 1 on the intermediate substrate 2.
Is an adhesive for fixing the semiconductor chip 1 and the Au wire 6 for protecting the semiconductor chip and the Au wire 6.
【０００４】次にＢＧＡ、ＣＳＰの製造工程を簡単に説
明する。中間基板２に半導体チップ１を接着剤５で固定
した後、半導体チップ１の電極と中間基板２上の電極間
をＡｕワイヤ６でワイヤボンディングし導通させる。そ
の後、封止樹脂７で半導体チップ１が実装された面のみ
を封止する。次に封止されていない中間基板２の面の格
子状に並んだ第１電極部３に球状のハンダを載置したの
ち加熱して、第１電極部３とハンダ付けすると同時に球
状のハンダボール４を形成させパッケージの最終形態と
なる。[0004] Next, a brief description will be given of a manufacturing process of BGA and CSP. After the semiconductor chip 1 is fixed to the intermediate substrate 2 with the adhesive 5, the electrodes of the semiconductor chip 1 and the electrodes on the intermediate substrate 2 are wire-bonded with Au wires 6 to conduct. Thereafter, only the surface on which the semiconductor chip 1 is mounted is sealed with the sealing resin 7. Next, a spherical solder is placed on the first electrode portions 3 arranged in a grid on the surface of the unsealed intermediate substrate 2 and then heated to solder the first electrode portions 3 and simultaneously with the spherical solder balls. 4 to form the final form of the package.
【０００５】ＢＧＡ、ＣＳＰはパッケージとして基板ラ
ンド上に印刷したクリームハンダにハンダボール４を着
地させて実装する。実装後、基板とパッケージ間の熱膨
張係数差によって発生する応力に対して、リード付き部
品は、リードの伸び縮みで応力緩和するのに対して、Ｂ
ＧＡ、ＣＳＰではハンダ付け部で直接応力を受ける構造
であるため、接続界面から破断しやすく信頼性が低い傾
向にある。この場合、ハンダ付け部の信頼性を確保する
ために樹脂封止を行っていた。[0005] The BGA and CSP are mounted as a package by landing a solder ball 4 on cream solder printed on a substrate land. After mounting, the components with leads reduce the stress caused by the difference in thermal expansion coefficient between the board and the package.
Since GA and CSP have a structure in which a stress is directly applied at a soldered portion, they are liable to be broken at a connection interface and have low reliability. In this case, resin sealing was performed to ensure the reliability of the soldered portion.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、高密度
実装基板では樹脂封止のためのスペースを確保すること
が困難になってきており、また樹脂封止工程における加
熱工程が本来の実装工程に対する熱ストレスと時間、コ
ストの増加となっていた。以上のことから、ＢＧＡタイ
プの半導体パッケージおよび混成集積回路におけるハン
ダ接合部の信頼性向上策は不十分な実状にあった。However, it is becoming difficult to secure a space for resin encapsulation on a high-density mounting board, and the heating step in the resin encapsulation step is not suitable for the original mounting step. Stress, time and cost were increasing. In view of the above, measures for improving the reliability of solder joints in BGA type semiconductor packages and hybrid integrated circuits have been insufficient.
【０００７】本発明は上記課題を解決するもので、樹脂
封止を用いず半導体パッケージおよび混成集積回路のハ
ンダ付け部強度を高める半導体装置電極を提供する事を
目的する。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device electrode which increases the strength of a soldering portion of a semiconductor package and a hybrid integrated circuit without using resin sealing.
【０００８】[0008]
【課題を解決するための手段】本発明は、中間基板に半
導体装置を実装し外部との接続にＡｕめっきあるいはハ
ンダボールが付いた電極を前記中間基板下面に有する構
造の半導体装置および混成集積回路において、半導体装
置および混成集積回路と基板との接続を行う第１電極部
と、材質がハンダと金属間化合物の形成により結合する
金属、あるいは表面処理からなりハンダの接合強度を向
上させるための第２電極部より構成したことを特徴とす
る半導体装置電極である。本発明により、ハンダ付け部
の強度を高める電極構造が得られる。SUMMARY OF THE INVENTION The present invention provides a semiconductor device and a hybrid integrated circuit having a structure in which a semiconductor device is mounted on an intermediate substrate and an electrode provided with Au plating or solder balls for connection to the outside is provided on the lower surface of the intermediate substrate. A first electrode portion for connecting a semiconductor device and a hybrid integrated circuit to a substrate; and a first electrode portion made of a metal bonded to a solder and an intermetallic compound by forming an intermetallic compound, or a surface treatment for improving a solder bonding strength. A semiconductor device electrode comprising two electrode portions. According to the present invention, an electrode structure that increases the strength of the soldered portion can be obtained.
【０００９】[0009]
【発明の実施の形態】本発明の請求項１に記載の発明
は、中間基板に半導体装置を実装し外部との接続にＡｕ
めっきあるいはハンダボールが付いた電極を前記中間基
板下面に有する構造の半導体装置および混成集積回路に
おいて、半導体装置および混成集積回路と基板との接続
を行う第１電極部と、材質がハンダと金属間化合物の形
成により結合する金属、あるいは表面処理からなりハン
ダの接合強度を向上させるための第２電極部より構成し
たことを特徴とする半導体装置電極である。本発明の構
成により、ハンダ付け部の強度を高める電極構造が得ら
れる。DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, a semiconductor device is mounted on an intermediate substrate and Au is connected to an external device.
In a semiconductor device and a hybrid integrated circuit having a structure in which an electrode with plating or a solder ball is provided on the lower surface of the intermediate substrate, a first electrode portion for connecting the semiconductor device and the hybrid integrated circuit to the substrate is formed of a material between solder and metal. A semiconductor device electrode comprising a metal bonded by forming a compound or a second electrode portion made of a surface treatment for improving the bonding strength of solder. According to the configuration of the present invention, an electrode structure that increases the strength of the soldered portion can be obtained.
【００１０】本発明の請求項２に記載の発明は、中間基
板に設置された第２電極部は第１電極とは平面的、立体
的にクリアランスをもって設置することを特徴とする請
求項１記載の半導体装置電極であって、特に第２電極部
の構成により、ハンダ付け部の強度を向上させることが
できる。According to a second aspect of the present invention, the second electrode portion provided on the intermediate substrate is provided with a clearance two-dimensionally and three-dimensionally from the first electrode. In particular, the strength of the soldered portion can be improved by the configuration of the second electrode portion.
【００１１】本発明の請求項３に記載の発明は、中間基
板に半導体装置を実装し外部との接続にＡｕめっきある
いはハンダボールが付いた電極を中間基板下面に有する
構造の半導体装置および混成集積回路において、中間基
板と同等の外形を有し回路を形成して能動部品受動部品
を実装可能とするとともに、中間基板上の第１電極に対
応的に開口部を設け開口部および開口部周辺に第２電極
部を設けた第２中間基板を、中間基板に接着部材で固定
し一体構造としたことを特徴とする請求項１記載の半導
体装置電極である。本発明の構成により、半導体パッケ
ージおよび混成集積回路の機能が向上すると同時に、中
間基板に第２電極部を直接設けることが不可能な構造で
あっても、容易に第２電極部を設けることができる。According to a third aspect of the present invention, there is provided a semiconductor device having a structure in which a semiconductor device is mounted on an intermediate substrate and an electrode provided with Au plating or a solder ball for connection to the outside is provided on a lower surface of the intermediate substrate. In the circuit, the outer shape is equivalent to that of the intermediate substrate, and a circuit is formed so that active components and passive components can be mounted. In addition, an opening is provided corresponding to the first electrode on the intermediate substrate, and the opening and the periphery of the opening are provided. 2. The semiconductor device electrode according to claim 1, wherein the second intermediate substrate provided with the second electrode portion is fixed to the intermediate substrate with an adhesive member to form an integral structure. According to the configuration of the present invention, the functions of the semiconductor package and the hybrid integrated circuit are improved, and at the same time, the second electrode portion can be easily provided even if the second electrode portion cannot be directly provided on the intermediate substrate. it can.
【００１２】本発明の請求項４に記載の発明は、第２中
間基板の開口部断面をテーパー状に形成し、第２電極部
も開口部形状に適応して形成することにより半導体装置
が被接続基板とハンダ接続された時のハンダフィレット
形状を制御する事を特徴とする請求項３記載の半導体装
置電極である。中間基板２の開口部のハンダフィレット
に応力破壊に対して弱い部位となるくぼみ部の発生を防
ぐこと可能となり、上述の請求項３の第２電極部の効果
と併せてハンダ付け部の強度を向上させることができ
る。According to a fourth aspect of the present invention, the semiconductor device is covered by forming the cross section of the opening of the second intermediate substrate into a tapered shape and forming the second electrode portion also in accordance with the shape of the opening. 4. The semiconductor device electrode according to claim 3, wherein a shape of the solder fillet when soldered to the connection substrate is controlled. It becomes possible to prevent the formation of a recessed portion which is a weak portion against stress destruction in the solder fillet in the opening of the intermediate substrate 2, and to reduce the strength of the soldered portion together with the effect of the second electrode portion of the third aspect. Can be improved.
【００１３】以下、本発明の実施の形態について、ＢＧ
Ａ、ＣＳＰパッケージの中間基板がポリイミドの場合を
例に説明する。Hereinafter, the embodiment of the present invention will be described with reference to BG
A, The case where the intermediate substrate of the CSP package is polyimide will be described as an example.
【００１４】（実施の形態１）図１は本発明の実施の形
態１における半導体装置電極の斜視図、図２は図１の半
導体装置電極の断面図である。図中、従来の技術と同符
号のものは基本的には同一であるので説明の詳細は省略
する。図１において、８は電極部３を外部接続用端子と
して使用するために中間基板２に設けられた開口部の開
口端に、開口部を囲むように設けた第２電極部で、この
場合は、第１電極部と立体的にクリアランスを保った状
態にある。(Embodiment 1) FIG. 1 is a perspective view of a semiconductor device electrode according to Embodiment 1 of the present invention, and FIG. 2 is a sectional view of the semiconductor device electrode of FIG. In the figure, those having the same reference numerals as those of the prior art are basically the same, and therefore, detailed description thereof will be omitted. In FIG. 1, reference numeral 8 denotes a second electrode unit provided at an opening end of an opening provided in the intermediate substrate 2 so as to use the electrode unit 3 as a terminal for external connection so as to surround the opening. , In a state where the clearance is three-dimensionally maintained with the first electrode portion.
【００１５】次にこのような電極部構造にハンダボール
を形成した場合について説明する。図２において、最終
パッケージの形態にするため、従来の技術同様、クリー
ムハンダを第１電極部３と第２電極部８に印刷し、ハン
ダ球を第１電極部３に載置したのち、リフロー炉にてハ
ンダを加熱溶融する。そして冷却するとハンダボール４
は電極部３と第２電極部８で接合される。この接合形態
ならば、電極部３のハンダ接続と併せて第２電極部８の
接続部が電極部３に対する補強となり、ハンダ付け強度
を向上させることができる。Next, a case where a solder ball is formed in such an electrode portion structure will be described. In FIG. 2, cream solder is printed on the first electrode portion 3 and the second electrode portion 8, and solder balls are placed on the first electrode portion 3 in the same manner as in the prior art to form a final package. Heat and melt the solder in a furnace. And when cooled, solder ball 4
Are joined at the electrode portion 3 and the second electrode portion 8. With this bonding mode, the connection portion of the second electrode portion 8 reinforces the electrode portion 3 in addition to the solder connection of the electrode portion 3, and the soldering strength can be improved.
【００１６】（実施の形態２）図３は本発明の実施の形
態２における半導体装置電極の断面図である。図３にお
いて、９は第２中間基板であって、回路を形成して能動
部品、受動部品を実装可能とすると同時に、中間基板２
と同等の外形で中間基板２に設けられた電極部３と対応
的に開口部を設けたガラスエポキシ、セラミック、ポリ
イミド等の有機系、無機系の基材で作られる。１０は前
記第２中間基板９と中間基板２とを固定するための接着
剤を示す。(Embodiment 2) FIG. 3 is a sectional view of a semiconductor device electrode according to Embodiment 2 of the present invention. In FIG. 3, reference numeral 9 denotes a second intermediate substrate, which forms a circuit to enable mounting of active and passive components,
It is made of an organic or inorganic base material such as glass epoxy, ceramic, or polyimide provided with an opening corresponding to the electrode portion 3 provided on the intermediate substrate 2 with an outer shape equivalent to that of the intermediate substrate 2. Reference numeral 10 denotes an adhesive for fixing the second intermediate substrate 9 and the intermediate substrate 2.
【００１７】次にこのような構造のものにハンダボール
を形成した場合について説明する。接着材１０で第２中
間基板９を中間基板２に固定する。これにより、第１電
極部３と第２電極部８とが実施の形態１と同様に立体的
にクリアランスを持った構造になる。クリームハンダを
第１電極部３と第２電極部８と能動部品、受動部品の電
極部にも同時に印刷し、第１電極部３と第２電極部８に
はハンダ球を実装し、その他の電極には適応的に能動部
品、受動部品を実装した後、リフロー炉にてハンダを加
熱溶融するとハンダボール４は第１電極部３と第２電極
部８で接合され、実施の形態１と同等の効果を得ること
が可能となる。Next, a case where a solder ball is formed on such a structure will be described. The second intermediate substrate 9 is fixed to the intermediate substrate 2 with an adhesive 10. Thus, the first electrode unit 3 and the second electrode unit 8 have a structure having a three-dimensional clearance as in the first embodiment. The cream solder is simultaneously printed on the first electrode section 3 and the second electrode section 8 and on the electrode sections of the active component and the passive component, and solder balls are mounted on the first electrode section 3 and the second electrode section 8. After the active components and passive components are adaptively mounted on the electrodes, when the solder is heated and melted in a reflow furnace, the solder balls 4 are joined at the first electrode portion 3 and the second electrode portion 8, and are the same as in the first embodiment. Can be obtained.
【００１８】（実施の形態３）図４は本発明の実施の形
態３における半導体装置電極の断面図である。図４にお
いて、第２中間基板９の開口部にテーパーを設けてハン
ダボール４の形状を変形させたものである。この構造に
より、第２中間基板９を付加したことによる開口部距離
の延長に伴い、開口部に形成されるフィレットにくぼみ
部が形成されやすい構造になっていたのが、開口部形状
にそってフィレットが形成されるために、くぼみが出来
にくい構造となる。(Embodiment 3) FIG. 4 is a sectional view of a semiconductor device electrode according to Embodiment 3 of the present invention. In FIG. 4, the shape of the solder ball 4 is deformed by providing a taper in the opening of the second intermediate substrate 9. With this structure, with the extension of the opening distance due to the addition of the second intermediate substrate 9, a structure in which a recess is easily formed in the fillet formed in the opening has been adopted. Since a fillet is formed, a structure in which a depression is hardly formed is obtained.
【００１９】[0019]
【発明の効果】以上のように本発明によれば、接続端子
が本体下部に格子状に並び、ハンダ接続部で全ての破壊
応力を受ける形態をとる半導体パッケージおよび混成集
積回路のハンダ付け部の強度を向上することが可能とな
る。また、第２の中間基板に第２電極部を設置してこれ
を半導体パッケージおよび混成集積回路と一体化するこ
とにより、半導体パッケージおよび混成集積回路の機能
向上が図れると同時に、中間基板の構成、構造に関わら
ず第２電極部の設置が可能となると同時に、ハンダフィ
レット形状の制御も容易に可能となる。As described above, according to the present invention, the connection terminals are arranged in a lattice pattern at the lower portion of the main body, and all of the soldering portions receive the destructive stress in the semiconductor package and the soldering portion of the hybrid integrated circuit. Strength can be improved. Further, by providing the second electrode portion on the second intermediate substrate and integrating it with the semiconductor package and the hybrid integrated circuit, the functions of the semiconductor package and the hybrid integrated circuit can be improved, and at the same time, the configuration of the intermediate substrate, Regardless of the structure, the second electrode portion can be installed, and at the same time, the shape of the solder fillet can be easily controlled.
【図１】本発明の実施の形態１における半導体装置電極
の斜視図FIG. 1 is a perspective view of a semiconductor device electrode according to a first embodiment of the present invention.
【図２】図１の半導体装置電極の断面図FIG. 2 is a sectional view of the semiconductor device electrode of FIG. 1;
【図３】本発明の実施の形態２における半導体装置電極
の断面図FIG. 3 is a sectional view of a semiconductor device electrode according to a second embodiment of the present invention;
【図４】本発明の実施の形態３における半導体装置電極
の断面図FIG. 4 is a sectional view of a semiconductor device electrode according to a third embodiment of the present invention;
【図５】従来の半導体装置および混成集積回路の電極の
断面図FIG. 5 is a sectional view of a conventional semiconductor device and electrodes of a hybrid integrated circuit.
１ 半導体チップ ２ 中間基板 ３ 第１電極部 ４ ハンダボール ５ 接着剤 ６ 金ワイヤ ７ 封止樹脂 ８ 第２電極部 ９ 第２中間基板 １０ 接着剤 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Intermediate substrate 3 1st electrode part 4 Solder ball 5 Adhesive 6 Gold wire 7 Sealing resin 8 2nd electrode part 9 2nd intermediate substrate 10 Adhesive
Claims (4)
接続にＡｕめっきあるいはハンダボールが付いた電極を
前記中間基板下面に有する構造の半導体装置および混成
集積回路において、前記半導体装置および混成集積回路
と基板との接続を行う第１電極部と、材質がハンダと金
属間化合物の形成により結合する金属、あるいは表面処
理からなりハンダの接合強度を向上させるための第２電
極部より構成されていることを特徴とする半導体装置電
極。1. A semiconductor device and a hybrid integrated circuit having a structure in which a semiconductor device is mounted on an intermediate substrate and an electrode having an Au plating or a solder ball for connection to the outside is provided on a lower surface of the intermediate substrate. It is composed of a first electrode portion for connecting the integrated circuit and the substrate, and a second electrode portion for improving the bonding strength of the solder, which is made of a metal or a material whose surface is bonded by forming an intermetallic compound with the solder. A semiconductor device electrode, comprising:
記第１電極とは平面的、立体的にクリアランスをもって
設置することを特徴とする請求項１記載の半導体装置電
極。2. The semiconductor device electrode according to claim 1, wherein the second electrode portion provided on the intermediate substrate is provided with a two-dimensional and three-dimensional clearance with respect to the first electrode.
接続にＡｕめっきあるいはハンダボールが付いた電極を
前記中間基板下面に有する構造の半導体装置および混成
集積回路において、前記中間基板と同等の外形を有し、
回路を形成して能動部品、受動部品を実装可能とすると
ともに、前記中間基板上の第１電極に対応的に開口部を
設け、前記開口部および開口部周辺に前記第２電極部を
設けた第２中間基板を前記中間基板に接着部材で固定し
一体構造としたことを特徴とする請求項１記載の半導体
装置電極。3. A semiconductor device and a hybrid integrated circuit having a structure in which a semiconductor device is mounted on an intermediate substrate and an electrode provided with Au plating or a solder ball for connection to the outside is provided on a lower surface of the intermediate substrate. Has the outer shape of
A circuit is formed so that an active component and a passive component can be mounted, an opening is provided corresponding to the first electrode on the intermediate substrate, and the second electrode portion is provided around the opening and the opening. 2. The semiconductor device electrode according to claim 1, wherein the second intermediate substrate is fixed to the intermediate substrate with an adhesive member to form an integral structure.
状に形成し、前記第２電極部も前記開口部形状に適応し
て形成することにより前記半導体装置が前記被接続基板
とハンダ接続された時のハンダフィレット形状を制御す
る事を特徴とする請求項３記載の半導体装置電極。4. The semiconductor device according to claim 1, wherein a cross section of the opening of the second intermediate substrate is formed in a tapered shape, and the second electrode portion is also formed in conformity with the shape of the opening. 4. The semiconductor device electrode according to claim 3, wherein the shape of the solder fillet when the soldering is performed is controlled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6641999A JP2000260913A (en) | 1999-03-12 | 1999-03-12 | Electrode of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6641999A JP2000260913A (en) | 1999-03-12 | 1999-03-12 | Electrode of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000260913A true JP2000260913A (en) | 2000-09-22 |
Family
ID=13315268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6641999A Pending JP2000260913A (en) | 1999-03-12 | 1999-03-12 | Electrode of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000260913A (en) |
-
1999
- 1999-03-12 JP JP6641999A patent/JP2000260913A/en active Pending
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