JP2000260200A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To measure the operating margin of a sense amplifier. SOLUTION: Concerning this semiconductor memory device, when a high level signal is outputted from a test signal generating circuit 7, MOS transistors M1 and M2 are turned on, a bit line setting voltage VB1 is impressed to a bit line BL and a bar bit line bar setting voltage VB2 is impressed to a bit line bar /BL respectively. Then, the bit line setting voltage VB1 and the bit line bar setting voltage VB2 are differentially impressed to the sense amplifier, to which the bit line and the bit line bar are connected, and the operating margin is measured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art A first publication (JP-A-59-1985)
No. 94) describes a DRAM for controlling a precharge voltage of a dummy cell to measure an operation margin of a memory cell.

A second publication (Japanese Patent Laid-Open No. 5-36273)
No. 1) describes a memory provided with potential lowering means for lowering the potential of a bit line during a test.

[0004]

The technique disclosed in the first publication is effective in a method in which the capacitance value of a dummy cell is reduced to about half that of a memory cell, but is generally used in recent years.
It cannot be used for the / 2VCC precharge method. Further, according to the technology of this patent, the capacity of the dummy cell is equal to that of the memory cell.
/ 2, and the capacitance value varies more than the memory cell, so that the measurement data of the operation margin varies greatly. Further, this publication does not disclose a technique for measuring an operation margin of a sense amplifier.

In the second publication, the capacity of a test memory cell is fixed, and the margin can be checked only by judging good or bad. In addition, the capacity of the test memory cell needs to be smaller than that of the memory cell of the memory cell array, and the capacitance value is larger than that of the memory cell of the memory cell array. This publication also does not disclose a technique for measuring an operation margin of a sense amplifier.

An object of the present invention is to provide a semiconductor memory device capable of measuring an operation margin of a sense amplifier without requiring a dedicated dummy cell and a test memory cell.

Another object of the present invention is to provide a semiconductor memory device capable of measuring the operation margin of a memory cell and a sense amplifier without requiring a dedicated dummy cell and a test memory cell.

[0008]

(First means) A memory cell, a word line connected to a selection gate of the memory cell, and a bit line pair for reading and writing data of the memory cell. A sense circuit for amplifying the difference voltage between the bit line pair, and the bit line pair of the memory cell array having different voltage values from each other, and the difference between the bit lines during a normal read operation. Voltage applying means for applying a voltage smaller than the voltage difference generated in the pair to generate a predetermined voltage difference.

(Second Solution) A memory cell array including a memory cell, a word line connected to a selection gate of the memory cell, and a bit line pair for reading and writing data of the memory cell, A sense circuit for amplifying the difference voltage between the bit line pair, and a signal generated in one of the bit line pairs by reading data from a predetermined memory cell written in advance after precharging the bit line pair. Control means for storing the change in potential as it is.

(Third Solution) A memory cell array having a memory cell, a word line connected to a selection gate of the memory cell, and a bit line pair for reading and writing data of the memory cell. A sense circuit for amplifying a difference voltage between the bit line pairs and a connection means for short-circuiting corresponding ones of the plurality of bit line pairs in the memory cell array are provided.

(Fourth Solution) A memory cell array having a memory cell, a word line connected to a selection gate of the memory cell, and a bit line pair for reading and writing data of the memory cell. A sense circuit for amplifying a difference voltage between the pair of bit lines, word line control means for receiving a test signal and simultaneously turning on one or more of the word lines, and precharging the pair of bit lines; Control means for changing a voltage level of one of the pair from the precharge voltage to set a potential for margin measurement, and then reading data from the memory cell to be measured to the other of the bit line pair. Features.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 shows a configuration of a semiconductor memory device according to a first embodiment of the present invention,
The example of AM is shown.

N-channel MOS transistor M1
One electrode of the (switch transistor) is connected to the bit line (BL), and the gate is connected to the test signal line.

On the other hand, an N-channel MOS transistor M
2 (switching transistor) has one electrode connected to the bit line bar (/ BL) and its gate connected to the test signal line.

The bit line (BL) and the bit line bar (/ B
L) is connected to one sense amplifier in the column circuit 1 including a sense amplifier, a precharge equalizer, a column address decoder, and the like. This sense amplifier exists for each bit line and bit line bar pair. For example, the MOS transistors M1 and M2 constitute a test circuit 9 for one sense amplifier.

Reference numeral 3 denotes a row address decoder / driver. An external address input unit 5 supplies a column address signal to the column circuit 1 and a row address signal to the row address decoder / driver 3.

When the test signal from the test signal generating circuit 7 is at a high level (H), the MOS transistor M1 is turned on, and the bit line setting voltage (hereinafter, referred to as the bit line setting voltage) supplied to the other electrode of the bit line (BL). , This voltage is VB1) is applied to the bit line (BL).

When the test signal from test signal generation circuit 7 is at a high level (H), MOS transistor M
2 is turned on, and the bit line bar setting voltage (hereinafter, this voltage is referred to as VB2) supplied to the other electrode of the bit line bar (/ BL) is applied to the bit line bar (/ BL). You.

At the time of testing the sense amplifier in the column circuit 1, the circuit operates at the timing shown in FIG. 2 as a measurement cycle of the operation margin of the sense amplifier. That is, first, the test signal becomes high level (H), and the bit line (BL)
Becomes VB1, and the potential of the bit line bar (/ BL) becomes VB2.

The test signal becomes low level (L) and M
After the OS transistors M1 and M2 are turned off, the sense amplifier is operated. The sense amplifier is connected to the bit line (B
L) and the signal (VB1-
VB2) is amplified.

If (VB1−VB2 + Vofs)> 0, the potential of the bit line (BL) becomes the power supply voltage, and the potential of the bit line (/ BL) becomes the ground level.

If (VB1−VB2 + Vofs) <0, on the contrary, the potential of the bit line (BL) becomes the ground level, and the potential of the bit line (/ BL) becomes the power supply voltage. Here, Vofs represents an offset of the sense amplifier to which the bit line (BL) and the bit line bar (/ BL) are connected.

Therefore, when (VB1-VB2) is a positive value close to 0 V (for example, 5 mV), the output of the sense amplifier becomes the power supply voltage (= high level), and (VB1-VB2)
If 2) is a negative value close to 0 V (for example, -5 mV) and the output of the sense amplifier becomes the ground voltage (= low level),
It can be seen that the offset of the sense amplifier is small (in the example, the offset is ± 5 mV or less).

At the normal operation timing of the sense amplifier (eg, timing of enabling the sense amplifier and latching the output of the sense amplifier), the test is performed by setting the difference voltage between VB1 and VB2 smaller than the difference voltage at the time of normal reading. For example, it is possible to evaluate a margin including the driving force of the sense amplifier.

The operation margin can be similarly measured for other sense amplifiers to which other bit lines and bit line bars are differentially connected.

It should be noted that in the specific examples of supply of VB1 and VB2 described below, illustration of the external address input unit 5 and the test signal generation circuit 7 is omitted.

(First Method of Supplying Bit Line Setting Voltage (VB1) and Bit Line Bar Setting Voltage (VB2) to FIG. 1) FIG. 3 shows the bit line setting voltage (VB1) and the bit line bar setting voltage to FIG. A first method of supplying the set voltage (VB2) will be described. The memory circuit 11 includes a test circuit, a memory cell array, a row address decoder / driver, a sense amplifier, a precharge equalizer, a column address decoder, and the like.

The bit line setting voltage (VB1) and the bit line bar setting voltage (VB2) described in the first embodiment correspond to the external pins 13 and 15 of the semiconductor memory device (semiconductor integrated circuit).
Is supplied from outside through

(Second Method of Supplying Bit Line Setting Voltage (VB1) and Bit Line Bar Setting Voltage (VB2) to FIG. 1) FIG. 4 shows the bit line setting voltage (VB1) and the bit line bar setting voltage to FIG. The second supply method of the set voltage (VB2) will be described. The memory circuit 11 includes a test circuit, a memory cell array, a row address decoder / driver, a sense amplifier, a precharge equalizer, a column address decoder, and the like.

The bit line setting voltage (VB1) and the bit line bar setting voltage (VB2) described in the first embodiment correspond to the bit line setting voltage (VB1) provided inside the semiconductor memory device (semiconductor integrated circuit). Bit line bar setting voltage (VB
It is supplied from the generation circuit 17 of 2).

(Second Embodiment) In a second embodiment of the present invention, when writing a high level to a capacitor of a memory cell via a bit line (for example, BL), a bit line (for example, After the voltage of BL) is lower than the power supply voltage, the data is read. Bit line (for example, BL)
When a low level is written to the capacitor of the memory cell via the memory cell, the voltage of the bit line (for example, BL) is set higher than the ground voltage, and then the data is read.

Reference bit line bar (for example, / BL)
Is the same precharge level as normal (for example,
1/2 VCC). Thereby, it is possible to set the signal of the bit line and the bit line bar pair smaller than usual.

Specifically, in the first half operation of the timing shown in FIG. 6, when writing to the capacitor of the memory cell via the bit line (eg, BL) is at a high level, the voltage of the bit line (eg, BL) is Is lower than the power supply voltage.

That is, after writing a high level to the capacitors of a large number of memory cells via the bit lines (for example, BL), the bit lines (for example, BL) are supplied with a precharge voltage from a precharge voltage supply circuit (not shown). BL)
And a bit line bar (for example, / BL) is precharged.

Next, as in the circuit of FIG. 5, a plurality of word lines are simultaneously opened (the MOS transistors of the memory cells are turned on), and a bit line (for example, BL) is set to a potential intermediate between the power supply voltage and the precharge voltage (this voltage). Is Vx).

Next, by closing the word line (the MOS transistor of the memory cell is turned off), the voltage Vx is written in the memory cell.

Next, again, a precharge voltage (for example, 1/2 VCC) from a precharge voltage supply circuit (not shown)
After precharging the bit line (for example, BL) and the bit line bar (for example, / BL), only one word line of the memory cell in which the above-mentioned Vx potential is written is opened (for the memory cell). A MOS transistor is turned on), and a signal is read out to a bit line (for example, BL).

With the above operation, a level lower than the normal high level can be set to the bit line (eg, BL).

Conversely, to set a bit line (for example, / BL) higher than the normal low level, a low level is applied to the capacitors of a large number of memory cells via the bit line (for example, / BL). After writing the level, the precharge voltage from the precharge voltage supply circuit (not shown)
A bit line (eg, BL) and a bit line bar (eg, /
BL) is precharged.

Next, as in the circuit of FIG. 5, the word line is simultaneously opened (the MOS transistor of the memory cell is turned on), and the bit line (for example, BL) is set to an intermediate potential between the ground voltage and the precharge voltage (Vp). The voltage is Vy).

Next, by closing the word line (turning off the MOS transistor of the memory cell), the voltage Vy is
Write to memory cells. Next, after precharging the bit line (for example, BL) and the bit line bar (for example, / BL) again with a precharge voltage from a precharge voltage supply circuit (not shown), the potential Vy is written. Only one word line of the memory cell is opened (the MOS transistor of the memory cell is turned on), and the bit line (for example, B
L) Read the signal.

Alternatively, as a method of setting a lower level than a normal high level to a bit line (for example, BL), a bit line (for example, BL) and a bit line bar are set by a precharge voltage from a precharge voltage supply circuit (not shown). (Eg, / BL) after precharging,
Are opened (the MOS transistor of the memory cell is turned on), and the bit line (for example, BL) is set to the low level.

Thereafter, all word lines are closed (the MOS transistors of the p memory cells are turned off), and a low-level potential (Va) close to the precharge level is written.

Next, the bit line (for example, for example) is again supplied with a precharge voltage from a precharge voltage supply circuit (not shown).
BL) and a bit line bar (e.g., / BL) are precharged, and then one memory cell in which a high level has been written in advance and word lines of a plurality (p) of memory cells in which Va has been previously written are connected. Open (turn on the MOS transistor of the memory cell) and read the signal.

As a result, if the precharge voltage is Vp, the capacitance of the bit line (for example, BL) is CB, the capacitance of the memory cell is CS, and the voltage of the bit line is V, the following equation (1) is applied to the bit line. , (2) hold. Therefore, the voltage V of the bit line becomes a value represented by the equation (3).

CB × Vp + CS × 0 = Va × (CB + p × CS) (1) CB × Vp + CS × VDD + p × CS × Va = (CB + (p + 1) × CS) V (2) V = (CB × Vp + CS × VDD + p × CS × Va) / (CB + (p + 1) × CS) (3) where CS / CB = 8, Vp = 0.5 × VDD, and Va = (4 × (VDD) / 9.

When V is obtained from the above equation for the case of p = 0, 1, 2, 3, the following is obtained. If p = 0, V
= 0.556VDD, when p = 1, V = 0.544V
When DD, p = 2, V = 0.527 VDD, and when p = 3, V = 0.508 VDD.

A bit line in a normal case where p = 0 (for example,
BL) and bit line bar (e.g., / BL) versus signal (V-Vp) = 0.056 VDD, for example, p = 2
In this case, (V−Vp) = 0.027 VDD, which indicates that the signal level is significantly reduced. By setting the value of p depending on which value of the offset of the sense amplifier should be NG, the operation margin of the sense amplifier can be measured.

(Third Embodiment) FIG. 7 shows a configuration of a semiconductor memory device according to a third embodiment of the present invention.

In FIG. 7, TEST is a mode switching signal input terminal, CT [0. . . 63] (N) is a column test signal input terminal, AD4 to AD9, AD4N to AD9N
Is a column address signal input terminal. CSN is a column selection terminal. B0 and B0N are bit output terminals.

As shown in FIG. 7, in a test circuit for coupling a large number of bit lines and bit line bars by a test signal, predetermined data is written in advance in a capacitor of a memory cell at a predetermined row address.

For example, when the number of bit lines and bit line bar pairs is 64, the predetermined data has 33 bits at a high level and the remaining 31 bits at a low level. It is assumed that the data of the memory cell is read by a normal read operation other than the test mode, and the bit line and the bit line bar are amplified to the power supply voltage or the ground voltage by the sense amplifier.

Thereafter, when 64 bit lines are coupled (short) by a test signal, ignoring the parasitic capacitance of the coupling line and the like, the equalization equalizes the voltage of 33 bit lines to VDD and 31 bits to VDD. It becomes 0V. Therefore, V (bit line voltage) = (33 × VDD + 31 ×
0) / 64, which is approximately 0.516 VDD.

For the bit line bar, V (voltage of the bit line bar) = (31 × VDD + 33 × 0) /64=0.484
VDD.

Therefore, the bit line and bit line bar pair signal in the normal case are the same as in the second embodiment (V-Vp).
= 0.056 VDD, (V (bit line voltage)
−V (voltage of the bit line bar)) = 0.032 VDD, and the bit line and the bit line bar pair signal can be set to a state lower than usual.

Thereafter, by operating the sense amplifier and checking whether normal reading can be performed, the operation margin of the sense amplifier can be measured.

In the above description, the level of the bit line is set by using the read operation. However, a method of setting the level of the bit line by using the write operation is also possible.

In this case, when the number of bit lines and bit line bar pairs is 64, it is assumed that the bit lines are at the power supply voltage and the bit line bar is at the ground voltage, and that Only one bit line and a bit line bar pair are subjected to a high level write operation, and then 64 bit lines are connected (short) and equalized to obtain V (bit line voltage) and V (bit line voltage). The bar voltage is:

V (bit line voltage) = (63 × 0.5 V)
DD + VDD) / 64, which is about 0.508 VDD.

V (voltage of bit line bar) = (63 ×
0.5 VDD) / 64, which is approximately 0.492 VDD.

Therefore, the bit line and bit line bar pair signal are (0.508 VDD−0.492 VDD) = 0.
016 VDD, indicating that there is a possibility that the setting can be made more finely in the case of writing. Then, the operation margin of the sense amplifier can be measured.

FIG. 10 shows a circuit example of the column address decoder of FIG. 7 (provided that the column address is 4 bits).
Here, A4d to A7d, A4dN to A7dN are AD4 to AD7, AD4N to AD7N in FIG.

A4d to A7d, A4dN to A7 in FIG.
dN is usually AD4 to AD7, AD4N to AD7N
During the test, a plurality of column selection signals (CS0 to CS1)
5) can be a signal that simultaneously holds.

As a result, the number of switch transistors and the number of signal lines can be reduced as shown in FIG.

(Fourth Embodiment) FIG. 8 shows a configuration of a semiconductor memory device according to a fourth embodiment of the present invention.

In FIG. 8, TAD0 to TAD3, TA
D0B to TAD3B are test address input terminals, A
D0 to AD3 are row address input terminals. FIG.
5 is a circuit example for turning on a plurality of word lines. In FIG. 8, an external address input unit and a test signal generating circuit such as a sense amplifier, a precharge equalizer, and a column address decoder are omitted.

FIG. 8 shows a case where the word line has an address of 4 bits for simplicity. Also, an example of a circuit in the case where the number of word lines to be simultaneously turned on is twelve, which is 3/4 of the total number of word lines, is shown.

In FIG. 8, during a normal read operation, test signals TEST to TEST together with signals AD0 to AD3 corresponding to address inputs of row address decoder / driver 3 are provided.
0, TAD0 to TAD3, TAD0B to TAD3B,
Input to the row line test circuit.

In this circuit example, the TEST0 signal
TAD0 to TAD3, TAD0B to TAD3B are shown in FIG.
By configuring the row line test circuit so as to output with the logic shown in FIG. 1, 3/4 of the word line is turned on at the time of the test for any combination of AD0 to AD3. .

In FIG. 11, a signal TEST0 that turns on ワ ー ド of the word line and TAD0 to TAD0 in that case are shown.
3, TAD0B to TAD3B are shown, but TAD0 to TAD3, TAD0B to TAD3
It is easy to output the signal B by logic such as always turning on the word line by １ ／.

FIG. 12 shows TAD0 to TAD3 and TAD0.
As means for generating B to TAD3B, AD0 to AD3
FIG. 2 is a block diagram of a test signal circuit using the test signal.

FIG. 9 is a circuit example of the row address decoder / driver 3 of FIG. WLEN is a word line enable input terminal.

(Fifth Embodiment) In the first to fourth embodiments, the semiconductor memory device for measuring the operation margin of the sense amplifier has been described. In the fifth embodiment, a semiconductor memory device circuit capable of measuring an operation margin including each memory cell and a sense amplifier will be described.

In FIG. 13, after precharging a bit line and a bit line bar with a precharge voltage from a precharge voltage supply circuit (not shown), a plurality of word lines are turned on, and a reference bit line (bit line bar) is turned on. ), Read data from multiple memory cells, and reference bit line (bit line bar)
After changing the voltage from the precharge voltage, the operation timing of a circuit for reading data from a memory cell to be measured to a bit line and observing an operation margin of the memory cell is shown. In FIG. 13, PC is a precharge signal, W
LEN0 is a word line enable signal (for normal use),
WLENT is a word line enable signal (for test), and SE0 is a sense amplifier enable signal.

When the test signal is at the high level, WL
At a timing when ENT is at a high level, a plurality of word lines are turned on, and a normal memory cell data read operation to a bit line (precharge is performed to open a word line, and data is read as a change in potential to a bit line). A series of actions)
I do. However, at this time, the sense amplifier remains off.

Next, only the memory cell to be measured is WLEN
The signal is turned on at a timing of 0, and after a predetermined time, the sense amplifier is turned on at a timing of SE0 to read data.

As described above, the operation margin of each memory cell and sense amplifier can be measured.

(Sixth Embodiment) FIG. 14 shows a configuration of a semiconductor memory device according to a sixth embodiment of the present invention. FIG.
In 4, TEST is a mode switching signal input terminal,
CT [0. . . 15] (N) is a column test signal input terminal, and AD4 to AD7 are column address signal input terminals. CSN is a column selection terminal. B0 and B0N are
This is a bit output terminal.

FIG. 15 shows an operation timing chart of FIG. In FIG. 15, PC is a precharge signal, WLEN0 is a word line enable signal (for normal and test use), and SE0 is a sense amplifier enable signal.

Using the semiconductor memory device of FIG. 14 and the operation timing chart of FIG. 15, the operation margin including each memory cell and the sense amplifier can be measured.

In the following operation, BL0 to BL15 are read bit lines, and BL0N to BL15N are reference bit lines (bit line bars). When the test signal TEST for measuring the operation margin is at a high level, after precharging, data is read out from the previously written memory cell to the reference bit line as described below. At this time, unlike the normal operation, the sense amplifier is not operated.

Next, a plurality of reference bit lines are connected to the signal CT0.
N-CT15N shorts the switch (MOS
Transistor ON), reference bit line (bit line bar)
Is changed from the precharge level.

Thereafter, the word line is turned on at the timing of WLEN0, and data is read from the memory cell to be measured to the read bit line BL0. After the signal is amplified by the sense amplifier, the CS0 signal is turned on, and the signals are read out to B0 and B0N.

Thus, the operation margin of the memory cell can be measured.

In the memory cell read in the first operation, the data is read in advance by short-circuiting by the test switch so that the voltage of the reference bit line becomes a voltage suitable for the margin measurement according to the data read in each column. Written. For example, when eight reference bit lines are short-circuited, three cells are set to a high level (H) and five cells are set to a low level (L), and the voltage of the reference bit line (bit line bar) is slightly lowered from the precharge level.

When the test signal is at a high level, a switch (MOS transistor) for shorting a plurality of reference bit lines (bit line bars) is set to a high level (H) in addition to a read operation without a sense amplifier operation. The timing of the signal CSTST to be turned on at the timing is added.

CT0 to CT15, CT0N to CT15N
Is turned on at the timing of this CSTST. CT0
CT15, CT0N to CT15N are generated by a test signal generation circuit, and can be set so as to short-circuit a reference bit line (bit line bar) at a required position.

By appropriately setting the already written data to be read in the first operation and CT0 to CT15 and CT0N to CT15N, the reference bit line can be set to various levels of voltages.

In FIG. 14, the circuit (test circuit) 51 for shorting the reference bit line and the sense amplifier, precharge equalizer, and column circuit (column address decoder, etc.) 1 are located at the same position with respect to the memory cell array. The circuit 51 for short-circuiting the (bit line bar) may be located at a position opposite to these.

As shown in FIG. 16 of the third embodiment,
CT0 to CT15 are referred to as CS0 to CS15, and CT0N to
CT15N may be CS0 to CS15.

[0091]

As described above, according to the present invention, the operation margin of the sense amplifier can be measured. Further, the operation margin of the memory cell and the sense amplifier can be measured.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a read timing chart of the semiconductor memory device of FIG. 1;

FIG. 3 shows a first method of supplying a bit line setting voltage (VB1) and a bit line bar setting voltage (VB2) to FIG.

FIG. 4 shows a second method of supplying the bit line setting voltage (VB1) and the bit line bar setting voltage (VB2) to FIG.

FIG. 5 is a diagram for explaining an operation of the second embodiment of the semiconductor memory device of the present invention;

FIG. 6 is an operation timing chart of the second embodiment of the semiconductor memory device of the present invention.

FIG. 7 is a diagram showing a configuration of a third embodiment of the semiconductor memory device of the present invention.

FIG. 8 is a diagram showing a configuration of a fourth embodiment of the semiconductor memory device of the present invention.

FIG. 9 is a circuit diagram of the row address decoder / driver of FIG. 8;

FIG. 10 is a circuit diagram of a column address decoder of FIG. 7;

11 is a signal timing chart in the semiconductor memory device of FIG. 8;

FIG. 12 is a diagram illustrating a test signal generation circuit of FIG. 8;

FIG. 13 is an operation timing chart of the fifth embodiment of the semiconductor memory device of the present invention.

FIG. 14 is a diagram showing a configuration of a sixth embodiment of the semiconductor memory device of the present invention.

FIG. 15 is an operation timing chart of the sixth embodiment of the semiconductor memory device of the present invention.

FIG. 16 is a circuit diagram corresponding to the third and sixth embodiments of the semiconductor memory device of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Column circuit, 3 ... Row address decoder / driver, 5 ... External address input part, 7 ... Test signal generation circuit, 9 ... Test circuit, M1, M2 ... MO
S transistor, 51 ... test circuit.

Claims (7)

[Claims] A memory cell array including a memory cell, a word line connected to a select gate of the memory cell, and a bit line pair for reading and writing data of the memory cell; A sense circuit for amplifying a difference voltage; and a voltage having a voltage value different between the bit line pair of the memory cell array and the difference being smaller than a voltage difference generated in the bit line pair during a normal read operation. And a voltage applying means for applying a predetermined voltage difference to generate a predetermined voltage difference. 2. The voltage application unit includes: a first switch unit connected to one of the bit line pairs; a second switch unit connected to the other of the bit line pairs; and the first switch. And a second terminal for inputting a second voltage supplied to said second switch means, and a first terminal for inputting a first voltage supplied to said means. 1
3. The semiconductor memory device according to claim 1. 3. The voltage applying means includes: first switching means connected to one of the bit line pairs; and second switching means connected to the other of the bit line pairs. 2. The semiconductor memory device according to claim 1, wherein a first voltage and a second voltage are supplied to the first and second switch means, respectively. 4. A memory cell array comprising: a memory cell; a word line connected to a select gate of the memory cell; and a bit line pair for reading and writing data of the memory cell; A sense circuit for amplifying the difference voltage; and, after precharging the bit line pair, by reading data from a predetermined memory cell written in advance, a change in potential generated in one of the bit line pair is detected. A semiconductor memory device comprising: a control unit for storing data as it is. 5. The semiconductor memory device according to claim 4, wherein said control means causes data to be simultaneously read from a plurality of memory cells to which data has been previously written. 6. A memory cell array comprising: a memory cell; a word line connected to a select gate of the memory cell; and a bit line pair for reading and writing data of the memory cell; A semiconductor memory device comprising: a sense circuit for amplifying a difference voltage; and connection means for short-circuiting corresponding ones of a plurality of bit line pairs in the memory cell array. 7. A memory cell array comprising: a memory cell; a word line connected to a select gate of the memory cell; and a bit line pair for reading and writing data of the memory cell; A sense circuit for amplifying a difference voltage; word line control means for receiving a test signal and simultaneously turning on one or more of the word lines; and after precharging the bit line pair, one voltage of the bit line pair Control means for setting a potential for margin measurement by changing a level from a precharge voltage and reading data from the memory cell to be measured to the other of the bit line pair. apparatus.