JP2000260187A - Superconductive latching/sfq hybrid ram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To substantially reduce a necessary AC bias current by using an effective combination of an AC type logical circuit biased by an AC current and a fluxoid type logic circuit biased by a DC current. SOLUTION: A 256 RAM block construction comprises a memory cell with 16 row and 16 columns, a voltage type logic driver circuit and sense circuit composed of superconductive latching elements biased by an AC current, and a fluxoid type logic decoder circuit composed of a superconductive single fluxoid quantum (FSQ) biased by a DC current. An AC power used for the whole RAMs can largely be reduced by arranging the decoder circuit part to be a fluxoid type logic circuit biased by a DC current, and an increase in AC power consumption in the driver circuit can be absorbed by adopting a multi-driver system.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a superconducting integrated circuit comprising a Josephson element operating at a very low temperature as a basic element, and more particularly, to a superconducting random access memory (RAM) which can operate at low power consumption and at high speed. ). Further, the present invention provides an RA high-speed cache memory for a superconducting computer,
About M.

[0002]

2. Description of the Related Art Generally, superconducting integrated circuits are roughly classified into two types. One is to use a strong nonlinearity appearing in the current-voltage characteristics of the Josephson element, and is called a voltage type logic. The voltage type logic has the same logic type as the logic used in a semiconductor integrated circuit. The other uses the nonlinearity of the current phase characteristic of the Josephson element and is called a fluxoid type logic.

A superconducting integrated circuit of the voltage type logic has a constant voltage (usually, a state “0” is set to a zero voltage level and a state “1” is set to a desired output voltage level) for a fixed time (for example, during a clock cycle). This is a circuit for performing a logical operation according to the voltage level. An operation signal of a voltage-type logic superconducting integrated circuit is called a level signal.
In a voltage-type logic superconducting integrated circuit, an underdamped Josephson element having a McCamba coefficient of 1 or more is normally used by being biased with an alternating current. Yes,
2πI ₀ CR _D ² / Φ ₀ , where I ₀ is the critical current value of the Josephson element, C is the capacitance, _RD is the resistance, and Φ ₀ is the single flux quantum. For details, refer to page 38 of “Ultra high-speed Josephson device published by Baifukan”. A voltage-type logic element is also called a latching (or latch) element because once it switches to the voltage state, it does not return to the initial state (superconducting state) unless the bias current returns to zero.

On the other hand, a superconducting integrated circuit of a fluxoid type logic has a single flux quantum (SFQ).
A circuit that outputs a pulse, and performs a logic operation in accordance with the propagation of magnetic flux quantum and the quantum state of the circuit. The operation signal of the superconducting integrated circuit of the fluxoid type logic is referred to as an SFQ pulse signal. In a superconducting integrated circuit of the fluxoid type logic, usually, a Josephson element in an overdamped state having a MacKamba coefficient of 1 or less is used by being biased with a direct current. The fluxoid logic circuit performs a logic operation by holding or propagating the SFQ. As described above, the circuit of the fluxoid type logic has a feature that the basic gate itself has a memory function, so that it can be easily pipelined. Note that the element of the fluxoid type logic is a circuit that performs a logic operation according to the propagation of magnetic flux quanta and the quantum state of the circuit as described above, and thus may be a circuit that handles a plurality of magnetic flux quanta. However, since a circuit that handles single flux quantum (SFQ) is often used, it is also called an SFQ element.

Some conventional superconducting RAMs have been developed which are composed of voltage-conducting logic superconducting integrated circuits.
As an example, see the literature (IEEE Trans. On Applied Supercond
uctivity, vol. 5, no.2, pp. 2447-2452, June, 199
5, “A 380ps, 9.5 mW Josephson 4-Kbit RAM operated
at high bit yield ").
The circuit of the fluxoid type logic has a RAM, that is, it is difficult to take a configuration of a random access memory (a configuration of a two-dimensional array). Therefore, a shift register-like memory that can be configured with a relatively simple one-dimensional structure (for example, Reference IEEE T
rans.on Applied Superconductivity, vol. 3, no.4
pp. 3102-3113, Dec. 1993, “RSFQ 1024-bit shift r
Although some egisters for acquisition memory ") have been developed, a RAM using fluxoid logic has not yet been developed.

[0006]

In the conventional voltage-type logic superconducting RAM, since all are constituted by latching elements, it is necessary to bias an AC high-frequency current. There is a major problem that a large current of several amps must be supplied at a high frequency.

[0007] On the other hand, the fluxoid logic circuit has the advantages of higher speed and lower power consumption than the voltage logic circuit, and has the great advantage of requiring only a direct current bias. There is a problem that a random access memory requiring a configuration cannot be easily configured.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and includes a voltage type logic circuit biased by an alternating current and a fluxoid type logic biased by a direct current. An object of the present invention is to provide a superconducting RAM capable of operating at high speed while significantly reducing a required AC bias current by effectively using circuits in combination.

[0009]

To achieve the above object, the present invention provides a driver circuit constituted by a superconducting latching element biased by an alternating current, and a superconducting single flux quantum biased by a direct current. (SFQ) and a decoder circuit constituted by elements.

That is, a superconducting latching / SFQ hybrid RAM according to one embodiment of the present invention comprises a driver circuit composed of a superconducting latching element biased by an alternating current, and a superconducting single biased by a direct current. A superconducting random access memory including a decoder circuit composed of magnetic flux quantum (SFQ) elements as one block;
It is composed of a block array in which a plurality of these blocks are arranged in an array, a block decoder circuit for selecting each block, and a superconducting latching element biased with an alternating current for transmitting a signal between blocks at high speed. And a transmission line having impedance matching with the block driver circuit.

Further, according to the present invention, there is provided an impedance conversion circuit for supplying an alternating bias current, a level logic signal of a superconducting latching element and a superconducting single flux quantum (SFQ) element in the superconducting random access memory. And a signal conversion circuit between the pulse logic signals described above.

In the present invention, the pipeline operation is performed in a configuration in which signal propagation between blocks, a decoder circuit in a block, and a driver circuit in a block are divided.

A feature of the present invention is that, first, when a load having a large inductance such as a word line or a bit line of a memory cell array is driven, a voltage-type logic driver circuit having a high driving capability is used. Second, for signal propagation over long distances such as between blocks, a signal is propagated at high speed through a transmission line (strip line) whose impedance is matched with that of a voltage-type logic driver circuit. Third, the other circuits are constituted by circuits using fluxoid type logic from the viewpoint of low power consumption. Fourth, in order to make use of the advantages of the high speed and the circuit of the fluxoid type logic, a multistage pipeline is used.

Thus, the superconducting latching / S of the present invention
The FQ hybrid RAM is a superconducting RAM that can significantly reduce an AC bias current and operate at high speed by effectively using a voltage-type logic superconducting circuit and a fluxoid-type logic superconducting circuit. Can be realized.

[0015]

Next, the present invention will be described with reference to the drawings.

(Embodiment) FIG. 1 is a block diagram showing a configuration of a superconducting latching / SFQ hybrid RAM according to an embodiment of the present invention. Here, a 16 Kbit superconducting latching / SFQ hybrid RAM is shown. ing. As is apparent from FIG.
It comprises 256 RAM blocks, a block decoder circuit, a block driver circuit, a voltage-type logic driver circuit for transmitting signals between blocks, an impedance matching line, and an LC resonance circuit for supplying a high-frequency alternating current (AC). ing. In this embodiment, 10 GHz
In order to enable the clock operation, the size of the storage cell array driven by one voltage-type logic driver circuit is reduced to 16
It is limited to 256 bits in 16 rows and 16 columns. Therefore, in the illustrated example, a multi-driver system for transmitting signals to a large number of RAM blocks in parallel is adopted.

FIG. 2 is a block diagram showing the structure of the 256 RAM block shown in FIG. 1. The voltage type logic circuit comprises a storage cell array of 16 rows and 16 columns and a superconducting latching element biased by an alternating current. Driver circuit and a sense circuit, and a fluxoid logic decoder circuit composed of a superconducting single flux quantum (SFQ) element biased by a direct current.

As shown in the figure, by constituting the decoder circuit with a fluxoid type logic circuit, the AC power can be greatly reduced. As in the past, in the case of a superconducting RAM using voltage-type logic, approximately 70% of the AC power was consumed by the decoder circuit. Therefore, by making this part a DC current biased fluxoid-type circuit, The AC power used in the entire RAM can be significantly reduced. With this reduction effect, it is possible to absorb an increase in AC power consumption in the driver circuit section due to the multi-driver system.

Referring now to FIG. 3, the signal propagation path and pipeline configuration of the superconducting latching / SFQ hybrid RAM of this embodiment will be described. Address, data,
First, an input signal such as R / W is transmitted to a 256 RAM block via a block decoder circuit, a block driver circuit, and an impedance matching line in the first clock cycle. In the next clock cycle, the decoder of the logic logic in the 256 RAM block operates, and in the next clock cycle, the driver circuit of the voltage logic, the memory cell array, and the sense circuit of the voltage logic operate, and the last clock cycle To propagate the output signal to the block sense circuit via the impedance matching line.

In this way, a 16K-bit superconducting latching / SFQ hybrid RAM was constructed with four stages of pipelines.

As described above, the superconducting latching / SFQ hybrid RAM according to the present embodiment uses a voltage type logic superconducting circuit and a fluxoid type superconducting circuit effectively in combination. Thereby, there is an effect that a superconducting RAM capable of greatly reducing an AC bias current and operating at high speed can be realized.

In the present embodiment, the storage capacity is set to 16K bits, and the RA of a 10 GHz clock is
Although a large-capacity RAM is configured, a large-capacity RAM can be configured while maintaining a 10 GHz clock by increasing the number of pipeline stages by arranging this RAM as a basic block and increasing the number of pipeline stages. You can do it.

[0023]

As described above, according to the present invention, the AC bias current can be greatly reduced by effectively combining the voltage type logic superconducting circuit and the fluxoid type superconducting circuit. Superconducting RA that can reduce and operate at high speed
M can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a superconducting latching / SFQ hybrid RAM according to the present invention.

FIG. 2 shows a superconducting latching / according to one embodiment of the present invention.
FIG. 4 is a block diagram for explaining a configuration of a 256 RAM block of the SFQ hybrid RAM.

FIG. 3 is a schematic diagram for explaining a signal propagation path and a pipeline configuration of an embodiment of a superconducting latching / SFQ hybrid RAM of the present invention.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazunori Miyahara 1-14-3 Shinonome, Shinonome, Koto-ku, Tokyo Foundation International Superconducting Technology Research Center Inside the Superconductivity Engineering Laboratory (72) Inventor Yoichi Enomoto, Koto-ku, Tokyo 1-14-3 Shinonome Foundation Corporation International Superconducting Technology Research Center Inside the Superconducting Engineering Laboratory

Claims (4)

[Claims] 1. A superconducting circuit comprising: a driver circuit constituted by a superconducting latching element biased by an alternating current; and a decoder circuit constituted by a superconducting single flux quantum (SFQ) element biased by a direct current. A random access memory as one block, a block array in which a plurality of the blocks are arranged in an array, a block decoder circuit for selecting each block, and a bias with an alternating current for transmitting a signal between blocks at high speed. A superconducting latching / SFQ hybrid RAM, comprising: a block driver circuit constituted by a superconducting latching element as described above; and a transmission line having impedance matching with the block driver circuit. 2. The superconducting random access memory according to claim 1, further comprising a signal conversion circuit between a level logic signal of a superconducting latching element and a pulse logic signal of a superconducting single flux quantum (SFQ) element. Superconducting latching / SFQ hybrid RAM. 3. The superconducting latching / SFQ hybrid RA according to claim 1, further comprising an impedance conversion circuit for supplying an AC bias current.
M. 4. A superconducting latching / SFQ hybrid RAM according to claim 1, wherein a pipeline operation is performed for each of signal propagation between blocks, a decoder circuit in the block, and a driver circuit in the block.