JP2000253086A - Digital costas loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacity of a ROM. SOLUTION: An address conversion circuit 11 divides a 8-bit control signal Θdenoting a phase error of 0-2π into a high-order 2-bit conversion control signal and a low-order 6-bit address Θ' of 0-π/2. A 0-π/2 since ROM 12 and a cosine ROM 13 respectively output sine data and cosine data according to the address Θ'. The sign data and the cosine data outputted from the sign ROM 12 and the cosine ROM 13 are outputted on the basis of a conversion control signal as they are or replaced or inverted to obtain the sine data and the cosine data corresponding to the control signal 0-2π.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital Costas loop circuit for use in a digital phase demodulation circuit for removing a carrier component from a digital complex signal obtained by quadrature detection, and in particular, to reduce the ROM capacity incorporated in the circuit. About.

[0002]

2. Description of the Related Art FIG. 3 shows a general configuration of a front end section in a digital receiver including a digital phase demodulation circuit. Such a digital receiver is used for receiving digital television satellite broadcasts and the like.

In a front end section of a digital receiver, a signal received by an antenna 31
2 down-converts to an arbitrary intermediate frequency signal (IF signal). Next, orthogonal detection is performed by the orthogonal detection circuit 33,
Analog I signal baseband _(I A), to obtain a Q signal _{(Q A).} The analog I signal and Q signal are AD
The digital I signal _(I D) by the converter 34, is converted into a Q signal _{(Q D)} is input to the Nyquist filter 35. The Nyquist filter 35 performs a filtering process for removing unnecessary high-frequency components and preventing intersymbol interference.

Here, a quadrature signal is generated by a quadrature detection circuit 33.
When generating minutes, synchronous detection of perfect carrier is not performed.
Baseband analog I and Q signals and data
A carrier component remains in the digital I signal and Q signal. this
Digital Costa to remove residual carrier components
This digital costa has a sloop circuit 36.
The data from which residual carrier components have been removed by the loop circuit
Digital I 'signal (I' _D), Q 'signal (Q'_D) Got
It is.

[0005] The digital Costas loop circuit 36 includes a complex multiplication circuit 361 and a digital I 'including a residual carrier component.
A carrier phase error detection circuit 362 for detecting a residual carrier component as a phase error component from the signal and the Q ′ signal and outputting a control signal Θ for canceling out the phase error component; ROM 36 which outputs the values of sine (sine) data and cosine (cos) data corresponding to
3 The ROM 363 includes a sign ROM 41 for outputting sign data and a cosine ROM 42 for outputting cosine data.

The complex multiplication circuit 361 performs the following operation: I ′ = I × cosｃｏ−Q × sinΘ Q ′ = I × sin × + Q × cosΘ Is obtained.

In this way, even if perfect synchronous detection is not performed in the quadrature detection circuit 33, the remaining carrier component can be removed by the digital Costas loop circuit, and the received digital data can be demodulated. Can be.

[0008]

Here, the control signal Θ applied to the ROM 363 of the digital Costas loop circuit 36 has a value corresponding to 0 to 2π. The capacity corresponding to is required. For example,
As shown in FIG. 5, assuming that control signal Θ indicates a value of 0 to 2π, this digital conversion value is 0 to 255.
Using this digital conversion value as an address, sign ROM 4
1 outputs sign data that changes from 0 → 127 → 0−128 → 0. The cosine ROM 42 has 127
Cosine data that changes from 0 to 128 to 0 to 127 is output.

Then, as shown in FIG.
When the bit and output data are n bits, the sign ROM
41 and the cosine ROM 42 each require a capacity of (2m × n) bits.

An object of the present invention is to provide a digital Costas loop circuit capable of reducing the capacity of the sine ROM and the cosine ROM.

[0011]

According to the present invention, there is provided a complex multiplier for complexly multiplying a digital complex signal by sine data and cosine data, and a carrier phase error component of an output of the complex multiplier is detected. A carrier phase error detection circuit that generates a control signal, and a sine cosine data generation circuit that generates sine data and cosine data to be supplied to the complex multiplier based on the control signal generated in the carrier phase error detection circuit. In a digital Costas loop circuit for removing a residual carrier component from a digital complex signal obtained by quadrature detection, the sine cosine data generation circuit converts the control signal into a conversion control signal and an address signal to a sine ROM and a cosine ROM. And an address conversion circuit for converting to A sine ROM and a cosine ROM for outputting data and partial cosine data, respectively, and a partial sine data and a partial cosine data output from the sine ROM and the cosine ROM to the complex multiplication circuit based on the conversion control signal. A data conversion circuit for converting the data into sine data and cosine data.

As described above, the control signal is not directly used as an address, but is divided into a conversion control signal and an address signal.
The ROM can be made partial corresponding to a part of the control signal. Therefore, the capacity of the ROM can be reduced. Since the sine and cosine change periodically, by converting the output of the ROM according to the conversion control signal, the same sine data and cosine data as when the control signal is directly used as the address can be obtained. .

The conversion control signal is an upper bit, and the sine ROM and the cosine ROM are 0 to 2π.
It is preferable to store only the output value corresponding to 1/4 of the inputs. By using the upper two bits as the conversion control signal, the address signal can be set to a range of 1/4, and for example, the sine ROM and the cosine ROM can have a capacity for an input of 0 to π / 2. Then, in the data conversion circuit, the same signal as for the input of 0 to 2π can be obtained by inverting or exchanging the outputs from the sine ROM and the cosine ROM as they are.

The above-described sine ROM and cosine RO
It is preferable that the number of bits of each address of M is 1 bit less than the sine data and the cosine data.

Further, the data conversion circuit includes a sign RO
M and a cosine ROM output inverting circuit, and a sine ROM and cosine ROM output and an output from the inverting circuit are input, and a selector is selected from these inputs in accordance with a conversion control signal and output. Is preferred. Thereby, the above-described conversion processing can be performed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

In the digital Costas loop circuit of this embodiment, the complex multiplication circuit 361 and the carrier phase error detection circuit 362 have the same configuration as the conventional example shown in FIG. The configuration of the ROM 363 that outputs sine data and cosine data according to the control signal Θ from the carrier phase error detection circuit 362 is different.

That is, the ROM 363 of the present embodiment
As shown in FIG. 1, address conversion circuit 11, sine data ROM 12, cosine data ROM 13,
And a data conversion circuit 14. The control signal Θ from the carrier phase error detection circuit 362 is input to the address conversion circuit 11, where it is converted into a conversion control signal and an address Θ ′. And the address Θ 'is the signature R
It is supplied to the OM 12 and the cosine ROM 13 as a read address. Sine ROM 12, Cosine ROM 13
Outputs partial sine data and partial cosine data corresponding to the address Θ ′. The data conversion circuit 14 receives the partial sine data, the partial cosine data, and the conversion control signal, and outputs sine data and cosine data.

Here, the number of bits of the control signal Θ is m, the number of bits of sine data and cosine data is n, the number of bits of the conversion control signal is 2, and the number of bits of the address Θ ′ is m−
2. The number of output bits of the sine ROM 12 and the cosine ROM 13 is n-1.

Therefore, the sine ROM 12, the cosine RO
M13 may have a capacity of {2 ^m−2 × (n−1)} bits.

FIG. 2 shows a specific example of the configuration of the ROM 363 in which the number of bits of the control signal Θ is m = 8 bits and the number of sine data and cosine data bits is n = 8 bits.

The control signal Θ, address Θ ′, sine ROM output, cosine RO
FIG. 6 shows the relationship between the M output and sine data and cosine data.

First, the control signal Θ is applied to the address conversion circuit 1
1 and is divided into upper 2 bits and lower 6 bits. The divided upper two bits are supplied to the data conversion circuit 14 as a conversion control signal. The lower 6 bits are supplied as an address $ 'to the sine ROM 12 and the cosine ROM 13. Corresponding sine data and cosine data are output from the sine ROM 12 and the cosine ROM 13 based on the address Θ ′. Here, the address Θ ′ is a value obtained by taking the upper two bits of the control signal 、, and varies within a range of 範 囲 of the control signal Θ. That is, if the control signal Θ has a value in the range of 0 to 2π, the address Θ ′ has a value of 0 to π / 2. Then, R
The capacity of the OM 363 can be reduced to 1/4 as compared with the case where values for inputs of 0 to 2π are stored.

The output of the sine ROM 12 and the cosine ROM 13 is 7 bits. This means that sine data for an input in the range of 0 to π / 2 and cosine data are 0 to 2π
This is because 1/2 of the value for the input of “. Thus, the number of bits at each address in the ROM 363 can be reduced by one bit.

In this way, the sine ROM 12 and the cosine ROM 13 output sine data (partial sine data) and cosine data (partial cosine data) in the range of 0 to π / 2. And these sign ROM1
2 and the output of the cosine ROM 13 are supplied to the MSB adding circuits 141 and 142 of the data conversion circuit 14. The MSB adding circuits 141 and 142 add 0 as an MSB which is a bit (sign bit) for indicating a code. Since the numerical value is represented by a two's complement, the MSB is a sign bit.

Next, the numerical value added by one bit in the MSB adding circuits 141 and 142 is output to the selectors 143 and 14.
4 is input.

Here, according to FIG.
Referring to the relationship between the cosine ROM output and the sine data and cosine data, when the control signal Θ is 0 to 2 / π, the sine data = sine ROM output cosine data = cosine ROM output When sine data = cosine ROM output cosine data =-(sine ROM output) When control signal Θ is π to 3 / 2π, sine data =-(cosine ROM output) cosine data =-(sine ROM output) When the control signal Θ is 3 / 2π to 2π, it can be seen that sine data = − (cosine ROM output) cosine data = sine ROM output.

Therefore, when the conversion control signal is 0 (control signal Θ is 0 to 2 / π), the selector 143 outputs the normal output: data a0 from the sign ROM to the selector 144.
Is a normal output from the cosine ROM: data b0
Select

When the conversion control signal is 1 (the control signal Θ is
In the case of (π), the selector 143 selects the normal output from the cosine ROM: data a1, and the selector 144 selects the inverted data from the sine ROM: data b1.

When the conversion control signal is 2 (the control signal Θ is π to 3 /
In the case of 2π), the selector 143 selects the data a2 whose output from the sine ROM is inverted, and the selector 144 selects the data b2 whose output from the cosine ROM is inverted.

When the conversion control signal is 3 (the control signal Θ is 3 / 2π
２2π), the selector 143 outputs the data a3 obtained by inverting the output from the cosine ROM, and the selector 144 outputs
The normal output data b3 from the sign ROM is selected.

In this way, the selector 143 outputs normal sine data and the selector 144 outputs normal cosine data in response to the input of the control signal Θ from 0 to 2π. That is, the same value as the sine data and cosine data shown in FIG. 5 is output.

Then, the sine ROM 12, the cosine RO
The addresses of M13 are each 1/4, and the number of bits of each address may be one bit smaller. Therefore, it is possible to output sine data and cosine data equivalent to those of the related art even with a smaller capacity of the sine ROM and the cosine ROM than in the related art.

[0034]

According to the present invention, the capacity of the sine and cosine ROM in the digital Costas loop circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a ROM according to the present invention.

FIG. 2 is a block diagram showing the configuration of FIG. 1 more specifically.

FIG. 3 is a block diagram illustrating a configuration of a conventional general phase demodulation circuit.

FIG. 4 is a block diagram illustrating a configuration of a conventional sine and cosine ROM.

FIG. 5 is a diagram showing the relationship between a control signal Θ and sine data and cosine data.

FIG. 6 is a diagram showing the relationship between a control signal Θ, an address Θ ', a sine ROM output, a cosine ROM output, sine data, and cosine data according to the present invention.

[Explanation of symbols]

11 address conversion circuit, 12 sign data ROM,
13 cosine data ROM, 14 data conversion circuit.

Claims (4)

[Claims] 1. A complex multiplier for complexly multiplying a digital complex signal by sine data and cosine data, and a carrier phase error for detecting a carrier phase error component of an output of the complex multiplier and generating a control signal based on the component. A detection circuit, and a sine cosine data generation circuit for generating sine data and cosine data to be supplied to the complex multiplier based on a control signal generated in the carrier phase error detection circuit, and obtained by quadrature detection. In a digital Costas loop circuit for removing a carrier component from a digital complex signal, the sine cosine data generation circuit includes an address conversion circuit that converts the control signal into a conversion control signal and an address signal to a sine ROM and a cosine ROM. Partial sine data and partial cosine data according to the address signal A sine ROM and a cosine ROM that respectively output the sine data and the cosine data to supply the partial sine data and the partial cosine data output from the sine ROM and the cosine ROM to the complex multiplication circuit based on the conversion control signal. A digital Costas loop circuit, comprising: a data conversion circuit that converts the data into a data. 2. The circuit according to claim 1, wherein the conversion control signal is upper 2 bits, and the sine ROM and the cosine ROM store only an output value corresponding to 1/4 of 0 to 2π. A digital Costas loop circuit characterized by: 3. The digital Costas loop according to claim 2, wherein the number of bits of each address of the sine ROM and the cosine ROM is one bit less than the sine data and the cosine data. circuit. 4. The circuit according to claim 2, wherein said data conversion circuit comprises a sine ROM and a cosine RO.
M, an inverting circuit for the output from the M, and a selector to which the outputs of the sine ROM and the cosine ROM and the output from the inverting circuit are input, and which selects and outputs the input according to a conversion control signal. Digital Costas loop circuit.