JP2000252368A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control a threshold valued voltage without changing an S-factor and to easily control the current-voltage characteristic of a CMOS inverter. SOLUTION: A polysilicon film which is to be used as the gate electrode of a CMOS inverter is formed. An Si0.4 Ge0.6 layer 28 is formed on an N-type region 24 forming a PMOS transistor while a gas mixed in such a way that its partial pressure ratio becomes SiH4:GeH4=4:6 is used. An Si0.6 Ge0.4 layer 29 is formed on a P-type region 22 forming an NMOS transistor while a gas mixed in such a way that its partial pressure ratio becomes SiH4:GeH4=6:4. A drop in the threshold value voltage of a CMOS transistor is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device of a CMOS type, and more particularly to a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to improve the characteristics of a large-scale integrated circuit composed of MOS transistors, it is important to control a threshold value to an optimum value. In particular, as the miniaturization progresses and the gate length becomes shorter, the short channel effect becomes more remarkable, and the threshold voltage of the MOS transistor becomes sharply lower.

Conventionally, as a method of suppressing a decrease in threshold voltage due to such a short channel effect, a dose of 1 × 10 ¹³ to 1 × 10 ^{13 is applied} to the surface of a semiconductor substrate before forming an element isolation region.
An impurity of the same conductivity type as that of the semiconductor substrate of about × 10 ¹⁴ cm ^-2 is implanted, and the distribution of the impurity concentration in the depth direction of the semiconductor substrate and in the direction parallel to the semiconductor substrate surface is controlled to increase the threshold voltage. There was a way to be done. Also, by increasing the thickness of the gate oxide film to reduce the capacitance of the gate oxide film,
There is also a method of increasing the threshold voltage.

[0004]

However, with the miniaturization of the element accompanying the increase in the degree of integration, the impurity to be implanted into the semiconductor surface requires a very shallow implantation, so that the impurity diffuses into the gate oxide film. There was a problem of doing it.

In addition, since it is difficult to control diffusion in the lateral direction, there is a problem that it is difficult to control the impurity concentration distribution near the source / drain regions. When a CMOS inverter as shown in FIG. 6 is formed, its characteristics are as shown in FIG.
Can be represented by a graph as shown in FIG. The horizontal axis of the graph in Figure 7 is the gate voltage V _G, the vertical axis is the logarithm of the drain current I _D.

As shown in FIG. 7, a drain current sometimes flows even when the gate voltage is zero, that is, when V _G = 0, and this is called I _off . Characteristics of the CMOS inverter as the I _off is small it can be said to be. I _off
For the smaller _{is, 0 ≦ V G ≦ V th} (V th is the threshold voltage) is necessary to increase the gradient of the graph of the range up, there is a S factor as change this inclination.
S factor is represented by the following equation 1.

[0007]

(Equation 1)

As can be seen from Equation 1, when the thickness of the gate oxide film is increased, the capacitance of the gate oxide film is reduced and the threshold voltage is increased, but the S factor is increased. Sfactor I _off is increased because is the gradient of the graph becomes small increases, there is a problem that the characteristics of the CMOS inverter is deteriorated.

The present invention takes the above circumstances into consideration and considers S f
The threshold voltage is controlled without changing the actor, and CMOS
It is intended to facilitate control of the current-voltage characteristics of the inverter.

[0010]

In order to achieve the above object, a semiconductor device according to the present invention has a first conductivity type first element region and a second conductivity type first element region formed on a semiconductor substrate and separated by an element isolation region. A first polysilicon gate electrode containing germanium formed on the first element region via an insulating film; and a second polysilicon gate electrode containing germanium formed on the second element region via an insulating film. A polysilicon gate electrode; a first source / drain region of a second conductivity type formed in the first element region; and a second source / drain region of a first conductivity type formed in the second element region. The amount of germanium contained in the first polysilicon gate electrode is larger than the amount of germanium contained in the second polysilicon gate electrode. .

Further, it is preferable that the first conductivity type is N-type and the second conductivity type is P-type. Note that the first conductivity type may be P-type, and the second conductivity type may be N-type.

A first conductive type first element region and a second conductive type second element type are separated from each other by a device isolation region in a semiconductor substrate.
Forming an element region; and forming a first element region in the first element region.
Forming a source / drain region, forming a second source / drain region in the second device region, and forming a first polysilicon film containing germanium on the first device region by a chemical vapor deposition method Forming a second polysilicon film containing a smaller amount of germanium than the first device region on the second device region by chemical vapor deposition; and forming the first polysilicon film on the second device region. And a step of etching the second polysilicon film to form first and second gate electrodes.

Further, a first conductive type first element region and a second conductive type second element type are separated from each other by a device isolation region in a semiconductor substrate.
Forming an element region; and forming a first element region in the first element region.
Forming a source / drain region; forming a second source / drain region in the second device region; forming a polysilicon film on the first and second device regions; Adding germanium to the polysilicon film on the device region; and adding germanium to the polysilicon film on the second device region in a smaller amount than that added to the polysilicon film on the first device region. ,
Forming a first and a second gate electrode by etching the polysilicon film.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a reference example of a semiconductor device according to the present invention will be described. FIG. 1 is a cross-sectional view illustrating a process for manufacturing a MOS transistor according to a reference example of the present invention. First, as shown in FIG. 1A, a field oxidation is performed on an N-type semiconductor substrate 1 at about 1100 ° C. to form a field oxide film 2, and an element region 3 and an element isolation region 4 are formed. I do. Thereafter, thermal oxidation is performed in a dry oxygen atmosphere at about 1000 ° C., and a thickness of about 5
A silicon oxide film 5 serving as a gate oxide film of about nm is formed.

Next, as shown in FIG.
And H ₄ gas and GeH ₄ gas, for example, partial pressure ratio SiH _4:
Mix and flow so that GeH ₄ = 4: 6, temperature: 6
Under the conditions of 30 ° C. and a pressure of 150 mT, a Si _0.4 Ge _0.6 film 6 having a thickness of about 0.25 μm is formed by a chemical vapor deposition method. Next, under the conditions of acceleration energy: about 20 keV and dose: about 1 × 10 ¹⁵ cm ⁻² , Si _0.4 Ge _0.6
Boron ions are implanted into the film 6 to perform an activation process.

Next, as shown in FIG. 1C, the Si _0.4 Ge _0.6 film 6 is etched using a mask to form a gate electrode 7 having a width of about 0.2 μm. Next, a silicon oxide film is formed by a chemical vapor deposition method and then etched to form a gate sidewall oxide film 8 having a thickness of about 100 nm on the sidewall of the gate electrode. Next, acceleration energy: 10
Boron is ion-implanted under the conditions of keV and a dose of 1 × 10 ¹⁵ cm ⁻² , and then an activation process is performed to form source and drain regions 9 and 10. Next, about 0.3
A source and drain electrode 1 is formed by forming an aluminum film of about μm and etching while leaving the aluminum film formed on the source and drain regions 9 and 10.
1 and 12 are formed. Thus, the manufacturing process of the P-type MOS transistor according to the reference example of the present invention is completed.

The absolute value of the threshold voltage of the P-type MOS transistor thus obtained was larger by about 0.25 V than when no germanium was contained. This is because the work function changes depending on the content of germanium, and the relationship between the work function and the threshold is expressed by the following equation 2.

[0018]

(Equation 2)

As shown in Equation 2, the work function φ _ms
Flat-band voltage V _FB becomes greater as determined by the difference in work function to become the gate electrode and the semiconductor substrate increases, as a result, the threshold voltage V _T increases.

Here, the amount of germanium contained in the gate electrode can be changed from 0% to 100% with respect to silicon. In the case of a P-type MOS transistor, the maximum threshold value is obtained when germanium is 100%. The absolute value of the voltage increases, and the amount of the change is about 0.4 V as compared with the case where germanium is not contained.

Similarly, when germanium is contained in the N-type MOS transistor, the threshold voltage decreases. The semiconductor device according to the present invention will be described with reference to this.

Hereinafter, a semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

First, as shown in FIG. 2A, a silicon oxide film is formed on the surface of an N-type semiconductor substrate 21 by a chemical vapor deposition method, and a predetermined portion is etched to have a width of about 1 μm. An opening is formed. Next, acceleration energy: 15 keV, dose amount: 1 × 10 ¹⁴ cm ⁻²
Boron is ion-implanted under the conditions described above to form a P-type well region 22 in a predetermined region. Next, oxidation is performed in a dry oxygen atmosphere at about 1000 ° C. to form a silicon oxide film, and a silicon nitride film is formed on the silicon oxide film by a chemical vapor deposition method.
(Not shown). After patterning this silicon nitride film, using this as a mask, field oxidation is performed in a dry oxygen atmosphere at about 1000 ° C. to form a field oxide film 23 on the semiconductor substrate 1,
Well region 22, N-type region 24 and element isolation region 26
And are formed. After that, the silicon nitride film is removed.

Next, as shown in FIG.
Oxidation is performed in a dry oxygen atmosphere at 000 ° C. to form a silicon oxide film 27 serving as a gate oxide film of about 5 nm. Thereafter, the SiH ₄ gas and GeH ₄ gas, for example, partial pressure ratio S
Mix and flow iH ₄ : GeH ₄ = 4: 6, and apply a thickness of about 0.2 to the surface of the semiconductor substrate 1 by chemical vapor deposition.
A Si _0.4 Ge _0.6 film of about 7 μm is formed. Next, acceleration energy: about 50 keV, dose amount: about 5 × 10
^Under a condition of ¹⁵ cm ^-2 , boron is ion-implanted into the Si _0.4 Ge _0.6 film to perform an activation process. Next, Si _0.4 Ge _0.6
A silicon nitride film having a thickness of about 10 nm is formed on the surface of the film, and is patterned with a resist. Using this silicon nitride film as a mask, Si _0.4 on P-type well region 22 is used.
The Ge _0.6 film is etched, and Si _0.4
A Ge _0.6 layer 28 is formed. Next, as shown in FIG. 2C, the SiH ₄ gas and the GeH ₄ gas are mixed and flown so that the partial pressure ratio becomes, for example, SiH ₄ : GeH ₄ = 6: 4, and the chemical vapor deposition A Si _0.6 Ge _0.4 film having a thickness of about 0.27 μm is formed on the surface of the semiconductor substrate 1 by the method.
Next, under the conditions of acceleration energy: about 50 keV and dose: about 5 × 10 ¹⁵ cm ⁻² , phosphorus is ion-implanted into the Si _0.6 Ge _0.4 film to perform an activation process. Next, patterning is performed using a resist to form Si _0.6 Ge on the N-type region 24.
_0.4 film is etched, and Si is
_{A 0.6} Ge _0.4 layer 29 is formed. After that, Si _0.4 Ge
The silicon nitride film on the _0.6 layer 28 is peeled off, and the N-type region 24 is removed.
And the step of the P-type well region 22 are eliminated.

Next, as shown in FIG. 2D, the Si _0.4 Ge _0.6 layer 28 and the Si _0.6 Ge
_0.4 layer 29 is etched to a P ⁺ gate electrode 30 and an N ⁺ gate electrode 31 having a thickness of about 0.27 μm and a width of about 0.2 μm.
To form Next, the P-type well region 22 is coated with a resist, and the N-type region 24 has acceleration energy: 10 k.
Boron is ion-implanted under the conditions of eV and a dose of 1 × 10 ¹⁵ cm ⁻² to form source and drain regions 32 and 33 of the PMOS transistor. After that, the resist is stripped. Next, the N-type region 24 is covered with a resist,
Acceleration energy: 10 keV in the P-type well region 22,
Phosphorus is ion-implanted under the condition of a dose of 1 × 10 ¹⁵ cm ⁻² , and the source and drain regions 3 of the NMOS transistor are implanted.
4, 35 are formed. Next, a silicon oxide film having a thickness of about 100 nm is formed by a chemical vapor deposition method, followed by etching to form a gate sidewall oxide film 36 on the sidewalls of the P ⁺ gate electrode 30 and the N ⁺ gate electrode 31. After that, about 0.3 μm thick aluminum is formed on the surface and then etched,
Source and drain electrodes 37, 38, 39, 40 are formed. Further, an interlayer insulating film and a wiring are formed, and the manufacturing process of the CMOS inverter as the semiconductor device according to the first embodiment of the present invention is completed. FIG. 3 is a top view of the CMOS inverter according to the first embodiment of the present invention.

According to the first embodiment of the present invention, by changing the amount of germanium contained in the gate electrodes 30 and 31, the threshold voltage of the NMOS transistor which determines the characteristics of the CMOS inverter and the threshold voltage of the PMOS transistor are determined. V _thN + | V which is the sum of the absolute values of the threshold voltages
The value of _thP | can be easily controlled. FIG. 4 shows the relationship between the PMOS transistor and N with respect to the germanium content.
This represents a change in the threshold voltage of a MOS transistor. The vertical axis represents the change amount ΔV _th (V) of the threshold voltage, and the horizontal axis represents the germanium content (%). As shown in FIG.
As the germanium content increases, NM
The threshold voltage of the OS transistor decreases, and the PMO
The absolute value of the threshold voltage of the S transistor increases.
By including germanium in the gate electrode,
Since the threshold voltage can be changed by about 0.4 V at the maximum, for example, a decrease in the value of V _thN + | V _thP | caused by a short channel effect caused by a shortened gate length is caused by the PMOS. This can be suppressed by making the germanium content of the gate electrode 30 of the transistor larger than that of the NMOS transistor. Also, NM
By making the germanium content of the gate electrode 31 of the OS transistor larger than that of the PMOS transistor, the value of V _thN + | V _thP | can be reduced, and the switching speed can be increased.

A CMOS according to the first embodiment of the present invention
Like the inverter, the germanium content of the gate electrode 30 of the PMOS transistor is set to 60%, and the germanium content of the gate electrode 31 of the NMOS transistor is set to 4%.
When it is set to 0%, the value of V _thN + | V _thP | is larger by 0.08 V than in the case where germanium is not included.

Therefore, there is no need to change the thickness of the gate oxide film as in the prior art, so that the value of Sfactor does not increase and only the threshold can be controlled, and the desired characteristics of the CMOS inverter can be improved. It is possible to get.

The present invention is not limited to the first embodiment, and the germanium content of the gate electrode of the PMOS transistor or the NMOS transistor can be arbitrarily set as required.

Next, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

The steps up to the step of forming an element region composed of a P-type well region, an N-type region and an element isolation region composed of a field oxide film are the same as in the method of manufacturing a semiconductor device according to the second embodiment of the present invention. Therefore, the description is omitted.

Next, as shown in FIG. 5 (a), a thickness of about 0.1 mm is formed on the surface of the semiconductor substrate 21 by using a chemical vapor deposition method.
A 27 μm polysilicon film 42 is formed. Next, the polysilicon film 42 on the N-type region 24 is covered with the resist 43, and the acceleration energy is 80 keV and the dose is 2
× 10 ¹⁸ cm ^-2 condition and acceleration energy: 30 ke
V, a dose of 2 × 10 ¹⁸ cm ^-2 , germanium was ion-implanted into the polysilicon film 42 on the P-type well region 22 twice, and acceleration energy: 50 k
An activation process is performed by implanting boron ions under the conditions of eV and a dose amount of 5 × 10 ¹⁵ cm ⁻² . After that, resist 4
3 is removed.

Next, as shown in FIG. 5B, the polysilicon film 42 on the P-type well region 22 is covered with a resist 44, and the acceleration energy is 80 keV and the dose is 3 × 10 ¹⁸ cm ^−2. Condition and acceleration energy: 3
Germanium is ion-implanted into the polysilicon film 42 on the N-type region 24 twice under the conditions of 0 keV and a dose of 3 × 10 ¹⁸ cm ⁻² , and acceleration energy: 60 k
Phosphorus is ion-implanted under the conditions of eV and a dose amount of 2 × 10 ¹⁵ cm ⁻² to perform an activation process. Then, the resist 44
Is removed.

Next, as shown in FIG. 5C, the polysilicon film 42 is etched using a mask to form a P ⁺ gate electrode 30 having a thickness of about 0.27 μm and a width of about 0.2 μm, and N ^+. A gate electrode 31 is formed. Next, the P-type well region 22 is coated with a resist, and the N-type region 24 has an acceleration energy of 10 keV and a dose of 1 × 10 ¹⁵ cm.
Boron is ion-implanted under the condition of ^-2 to form source and drain regions 32 and 33 of the PMOS transistor. After that, the resist is stripped. Next, the N-type region 24 is coated with a resist, and phosphorus is ion-implanted into the P-type well region 22 under the conditions of an acceleration energy of 10 keV and a dose of 1 × 10 ¹⁵ cm ⁻² , and the source and drain regions of the NMOS transistor are formed. 34 and 35 are formed. Next, a silicon oxide film having a thickness of about 100 nm is formed by a chemical vapor deposition method, followed by etching to form a gate sidewall oxide film 36 on the sidewalls of the P ⁺ gate electrode 30 and the N ⁺ gate electrode 31.
Thereafter, about 0.3 μm thick aluminum is formed on the surface and then etched to form source and drain electrodes 37 and 3.
8, 39 and 40 are formed. Further, an interlayer insulating film and a wiring are formed, and the manufacturing process of the semiconductor device according to the second embodiment of the present invention is completed.

According to the second embodiment of the present invention, by changing the conditions of germanium for ion implantation,
The value of V _thN + | V _thP | of the CMOS inverter can be arbitrarily controlled. For example, in a CMOS inverter manufactured under the conditions of the second embodiment of the present invention, V
_thN + | V _thP | value can be 0.05V to increase as compared with the case that does not contain germanium.

The present invention is not limited to the second embodiment. The germanium content of the gate electrode of the NMOS transistor can be made larger than the germanium content of the PMOS transistor.

[0037]

According to the present invention, by changing the amount of germanium added to the gate electrode of a PMOS transistor and the amount of germanium added to the gate electrode of an NMOS transistor in a CMOS inverter,
The threshold voltage of each transistor can be easily controlled.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a reference example of the invention.

FIG. 2 is a sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a top view of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a graph showing a change amount of a threshold voltage with respect to a germanium content.

FIG. 5 is a sectional view illustrating a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a circuit diagram of a CMOS inverter.

FIG. 7 is a characteristic diagram of a conventional CMOS inverter.

[Explanation of symbols]

1,21 ... semiconductor substrate, 2,23 ... field oxide film, 3,25 ... device region, 4,26 ... device isolation region, 5,27 ... silicon oxide film, 6 ... Si _0.4 Ge _0.6 film, 7 ... gate electrode 8, 36 ... gate side wall oxide film, 9, 32, 34 ... source region, 10, 33, 35 ... drain region, 11, 37, 39 ... source electrode, 12, 38, 40 ... drain electrode, 22 ... P-type well region, 24 ... N-type region, 28 ... Si _0.4 Ge _0.6 layer, 29 ... Si _0.6 Ge _0.4 layer, 30 ... P ⁺ gate electrode, 31 ... N ⁺ gate electrode, 41 ... wire, 42 ... polysilicon film, 43 , 44 ... resist

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 4M104 AA01 BB02 BB36 BB40 CC05 DD04 DD08 DD16 DD43 DD63 FF13 GG09 GG14 HH04 HH14 5F040 DA06 DB03 EC04 EH02 EK01 FA05 FC21 5F048 AA07 AB04 AC03 BA01 BB04 BB06 BB18 BB07 BB07 BB07 DA25

Claims (7)

[Claims] A first conductive type first element region and a second conductive type second element region formed on a semiconductor substrate by an element isolation region; and an insulating film over the first element region. A first polysilicon gate electrode containing germanium formed by forming, a second polysilicon gate electrode containing germanium formed on the second element region via an insulating film, and a first polysilicon gate electrode formed on the first element region A first source / drain region of the second conductivity type, and a second source / drain region of the first conductivity type formed in the second element region, and are contained in the first polysilicon gate electrode. The semiconductor device according to claim 1, wherein the amount of germanium is larger than the amount of germanium contained in the second polysilicon gate electrode. 2. The method according to claim 1, wherein the first conductivity type is N-type, and the second conductivity type is N-type.
2. The semiconductor device according to claim 1, wherein the conductivity type is P-type. 3. The method according to claim 2, wherein the first conductivity type is P-type, and the second conductivity type is P-type.
2. The semiconductor device according to claim 1, wherein the conductivity type is N-type. Forming a first element region of a first conductivity type and a second element region of a second conductivity type separated by an element isolation region on the semiconductor substrate; and forming a first source region in the first element region. Forming a drain region; forming a second source / drain region in the second device region; forming a first polysilicon film containing germanium on the first device region by a chemical vapor deposition method Forming a second polysilicon film containing a smaller amount of germanium than the first device region on the second device region by a chemical vapor deposition method; and forming the first polysilicon film and the second polysilicon film. Forming a first and a second gate electrode by etching the second polysilicon film. 5. A step of forming a first conductivity type first device region and a second conductivity type second device region separated by a device isolation region in a semiconductor substrate; and forming a first source region in the first device region. Forming a drain region; forming a second source / drain region in the second device region; forming a polysilicon film on the first and second device regions; Adding germanium to the upper polysilicon film; adding germanium to the polysilicon film on the second element region in a smaller amount than that added to the polysilicon film on the first element region; Forming a first gate electrode and a second gate electrode by etching a polysilicon film. 6. The first conductivity type is an N type, and the second conductivity type is an N type.
The method according to claim 4, wherein the conductivity type is a P-type. 7. The first conductivity type is a P type, and the second conductivity type is a P type.
The method according to claim 4, wherein the conductivity type is N-type.