JP2000252209A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress adverse effect of parasitic capacitance by providing a source-follower circuit region formed on a semiconductor substrate while being connected with pads and connecting the lower part of the pad with the output end of the source-follower circuit region. SOLUTION: A constant current source 5 is connected with the source of a J-FET 2 and a buffer circuit 6 is connected, at the input thereof, with the source of the J-FET 2 and, at the output thereof, with parasitic capacitors 3, 4. Since the buffer circuit 6 is provided, both poles of the parasitic capacitor 3 can be varied in in-phase. When charge/discharge of the parasitic capacitors 3, 4 is regulated by regulating the buffer circuit 6, variation of voltage at the joint of the parasitic capacitors 3, 4 can be regulated to the same level as the input signal. Since both pole voltages of the parasitic capacitor 3 can be amplified in-phase at the same level, variation of charges is eliminated in the parasitic capacitor 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device whose input is set to a high input impedance.

[0002]

2. Description of the Related Art Since a J-FET has a higher input impedance than a BIP type element and a higher electrostatic breakdown resistance than a MOS type FET element, it is used for a specific application such as a condenser microphone. I have. In addition, it has characteristics such as low low frequency noise and good high frequency characteristics for small signal amplification. In addition to the discrete type, a J-FET integrated on a BIP-IC has been developed.

In an integrated circuit in which J-FETs are integrated as shown in FIG. 6, a signal is applied from an external circuit to the gate of a J-FET 2 via a pad 1 provided on an integrated substrate. The gate voltage of J-FET2 changes due to an external input signal, and the amount of current flowing through J-FET2 changes. The current is converted to a voltage by the load resistor RL,
It is transmitted to the outside.

[0004]

When the circuit shown in FIG. 6 is integrated, the parasitic capacitance between the pad 1 and the substrate becomes two.
Occurs. That is, in the sectional view of the integrated pad shown in FIG. 7, an island region 102 is formed between two isolation regions 101, and a metal 103 as a pad is formed on the island region 102. I have. When integrated in this way, the MOS between the island region 102 and the metal 103
A capacitance is generated, and a junction capacitance is generated between the island region 102 and the substrate. When these parasitic capacitances are represented by a circuit, the connection point between the pad 1 and the gate of the J-FET 2 is grounded via the parasitic capacitances 3 and 4, as shown in FIG. When an element having a high output impedance, for example, a small-capacity capacitor is connected to the pad 1, the parasitic capacitances 3 and 4 have an extremely large value compared to the capacitance of the capacitor. In particular, when the area of the input pad 1 is increased by using the circuit of FIG. 7 for a specific purpose, the parasitic capacitance is further increased, so that the difference between the capacitance of the capacitor and the parasitic capacitance becomes more remarkable. Due to the parasitic capacitances 3 and 4, J-
The input signal applied to the gate of FET2 is greatly attenuated by pad 1, making it difficult to obtain a signal.

[0005]

SUMMARY OF THE INVENTION The present invention relates to a semiconductor device having a pad to which an input signal is externally applied.
A source follower circuit region is formed on the semiconductor substrate and connected to the pad, and a lower portion of the pad is connected to an output terminal of the source follower circuit region.

An island region surrounded by an isolation region with an insulating film interposed therebetween is formed below the pad, and an output end of the source follower circuit is connected to the island region. . In particular, the output end of the source follower circuit region and the island region are wired with metal.

In a semiconductor device having a pad to which an input signal is applied from the outside, an input stage circuit region formed on a semiconductor substrate and having an input end connected to the pad, and a semiconductor device formed on the semiconductor substrate. A buffer circuit region having an input terminal connected to the pad and an output terminal connected to the lower portion of the pad, and connecting the lower portion of the pad to an output terminal of the buffer circuit region. .

An island region surrounded by an isolation region with an insulating film interposed therebetween is formed below the pad, and an output terminal of the source follower circuit is connected to the island region. .

According to the present invention, by connecting the lower part of the pad and the output terminal of the source follower circuit with metal, the output terminal of the source follower circuit is connected to the connection point of the two parasitic capacitances generated below the pad. Therefore, the adverse effect of the parasitic capacitance can be suppressed.

[0010]

FIG. 1 is a diagram showing an embodiment of the present invention. The difference from FIG. 3 which is a conventional example is that a J-FET is used.
2 is connected to the constant current source 5 and the input is J-FET2
Is provided with a buffer circuit 6 whose output is connected to the connection point of the parasitic capacitances 3 and 4.

In FIG. 1, when a positive amplitude input signal is applied to the gate of J-FET 2, the current flowing through J-FET 2 increases. Then, an amount that is larger than the current of the constant current source 5 is supplied to the buffer circuit 6. Then, the output current of the buffer circuit 6 also increases, so that the parasitic capacitance 4
, And the parasitic capacitance 4 is charged. As the parasitic capacitance 4 is charged, the voltage at the connection point between the parasitic capacitances 3 and 4 increases. Therefore, when the gate voltage of the J-FET 2 increases, the connection point voltage of the parasitic capacitances 3 and 4 also increases.

Conversely, when a negative-amplitude input signal is applied to the gate of J-FET2, when a negative-amplitude input signal is applied to the gate of J-FET2, the current flowing through J-FET2 is changed to a constant current source. 5 is lower than the constant current. Then, the parasitic capacitance 4 is discharged by the output current of the buffer circuit 6. Since the voltage at the connection point between the parasitic capacitances 3 and 4 decreases due to the discharge, the connection point voltage between the parasitic capacitances 3 and 4 also decreases in accordance with the decrease in the gate voltage of the J-FET 2.

By providing the buffer circuit 6, both poles of the parasitic capacitance 3 can be changed in phase. Further, by adjusting the buffer circuit 6, the charge / discharge amount of the parasitic capacitances 3 and 4 can be adjusted, so that the voltage change at the connection point of the parasitic capacitances 3 and 4 can be adjusted to be equal to the level of the input signal. It is. Since the bipolar voltages of the parasitic capacitance 3 can be made to have the same phase and the same amplitude, the charge of the parasitic capacitance 3 does not change. Therefore, the parasitic capacitance 3 seen from the input pad 1 can be ignored equivalently. as a result,
The parasitic capacitance related to the attenuation of the input signal is only the parasitic capacitance 4, and the attenuation of the input signal can be reduced.

By the way, as the buffer circuit 6, J-
Like the FET 2, the input impedance is set to be high.
Further, since the capacitance of the parasitic capacitance 4 as a junction capacitance is relatively small in absolute value, the driving capability of the buffer circuit 6 need not be large. Therefore, since the buffer circuit 6 may have a simple configuration, the number of elements can be reduced, and when integrated, the chip area can be reduced.

Furthermore, since it is not necessary to increase the driving capability of the buffer circuit 6, the charging and discharging of the parasitic capacitance 4 is performed by J-FE
This can be performed by the source current of T. The parasitic capacitance 4 can be charged and discharged by a so-called J-FET source follower circuit. The charge / discharge by such a J-FET circuit enables the J-FET 2 of FIG.
And the buffer circuit 6. Figure 2 shows J
An embodiment in which the FET 2 and the buffer circuit 6 are shared is shown. In FIG. 2, an output signal is taken from the source of the J-FET 21, and the parasitic capacitance 4 is charged and discharged by the source follower circuit of the J-FET 21.

In FIGS. 1 and 2, the J-FET 2 is used as the input stage circuit of the integrated circuit. However, the present invention is not limited to this. 1 and 2 can be applied to an input stage circuit having a high input impedance or an amplifier having a high input impedance including, for example, a buffer circuit.

FIG. 3 is a cross-sectional view of the semiconductor integrated circuit of FIG. 2 when it is integrated on a semiconductor substrate. An N-channel type element as a field effect transistor J-FET is formed, and further integrated with the NPN transistor on the same substrate.

In FIG. 3, reference numeral 21 denotes a single crystal silicon semiconductor substrate. The specific resistance of a substrate used for a general bipolar integrated circuit is about 2 to 4 Ω · cm,
0-60 Ω · cm, the semiconductor substrate 2 of the present application
For 1, an extremely high specific resistance of 100 to 5000 Ω · cm is used.

First, the structure of the field effect transistor FET will be described. An N + buried layer 22 is formed on the surface of the semiconductor substrate, and a plurality of island regions 25 are formed by bonding and separating the N-type epitaxial layer 23 formed thereon on a P + isolation region 24. In one of the island regions 25, a P + buried layer 26 is provided so as to overlap the N + buried layer 22.
P + buried layer 26 is connected to P well region 27 formed by diffusion from the surface of island region 25. An N-type channel region 28 and a P + -type top gate region 29 are provided on the surface of the P-well region 27, and the channel-constituting region 28 is buried below the surface of the epitaxial layer 23. P well region 27 becomes a back gate.

Channel region 28 and top gate region 29
A P + type gate contact region 30 is formed so as to overlap the end of the well region 28 and cover the surface of the low concentration region of the well region 28. Furthermore, by penetrating the channel region,
An N + type source region 31 and a drain region 32 are formed. In this transistor, a depletion layer is formed in channel region 28 in accordance with the potential applied to the gate,
Controls channel current between drains. Reference numeral 33 denotes a source electrode, reference numeral 34 denotes a drain electrode, and reference numeral 35 denotes a gate electrode.

Next, a bipolar transistor will be described. The other island region 25 of the semiconductor substrate 21 has a P
A base region 36 is formed, and an N + emitter region 37 is formed on the surface of the base region 36 to form an NPN transistor using the island region 25 as a collector. 38 is N
+ Collector contact region. Reference numeral 39 denotes an emitter electrode, reference numeral 40 denotes a base electrode, and reference numeral 41 denotes a collector electrode.

These electrode groups make ohmic contact with the surface of the corresponding nuclear diffusion region,
The circuit extends over the silicon oxide film 42 covering the three surfaces and connects each circuit element to form an integrated circuit network. Among them, the gate electrode 35 connected to the gate of the J-FET
Is expanded on the oxide film 42 to have, for example, a diameter of 1.0
It is connected to a pad 43 having a circular pattern of about 1.5 mm. The pad 43 is the pad 1 in FIG.

Further, the structure below the pad 43 will be described. The lower part of the pad 43 is
+ One of the island regions 25 surrounded by the isolation regions 24 is located,
Further, a semiconductor substrate 21 having a high specific resistance is located below the semiconductor substrate 21. Then, a P-type diffusion region 44 is formed on the surface of the semiconductor substrate 21 except for the lower part of the pad 43 so as to obtain a higher specific resistance than the semiconductor substrate 21. In the P + isolation region 24, the P-type diffusion region 4
4 has been reached.

In FIG. 3, a contact 46 is formed so that the island region 25 below the pad 43 can be connected to the source electrode 31 of the J-FET. This contact 4
6 and the source electrode 31 are connected by metal wiring. This metal wiring is formed in the same layer as each electrode and pad 43. This metal wiring is shown in FIG.
Although not shown in FIG. 4, it will be described in detail with reference to a plan view of FIG.

FIG. 4 is a plan view showing an overall image of the semiconductor device. A semiconductor chip 50 having a chip size of about 2.5 × 3.0 mm has a diameter of 1.0 to
A pad 43 of about 1.5 mm is provided, and a part of the pad 43 extends and is connected to the gate electrode of the J-FET 51. In addition, the contact 4
6 and the contact 46 and the J-FET
The source electrode 51 is connected by a metal wiring 53. A plurality of external connection bonding pads 52 are arranged on the periphery of the semiconductor chip 50. Other circuit elements, for example, NPN transistors, resistance elements, capacitance elements, and the like are arranged so as to surround the pad 43 in a region excluding the pad 43. The constant current source of FIG. 2 is also arranged in the arrangement region, and the constant current source is the source electrode 31 of the J-FET.
Connected to

As described above, the source electrode 31 of the J-FET and the contact 46 are connected by the metal wiring, so that the connection point of the parasitic capacitances 3 and 4 is J
-A configuration capable of connecting the source electrode of the FET 31 can be realized. That is, as shown in FIG. 3, the parasitic capacitance 3 is formed by the pad 43 and the island region 25 using the oxide film 42 as a dielectric, and the parasitic capacitance 4 is formed by the PN junction between the island region 25 and the semiconductor substrate 21. , The island region 25 becomes a connection point of the parasitic capacitances 3 and 4. Therefore, the island region 25
Is connected to the source of the J-FET via the contact 46, whereby the configuration as shown in FIG. 1 can be obtained.

The P of the island region 25 and the P + isolation region 24
Although the parasitic capacitance C is also generated by the N-junction and connects the capacitor 3 to the ground potential, the parasitic capacitance C is within a negligible range when the area ratio is considered. While the conventional parasitic capacitance 4 is several tens pF, the capacitance C is several mpF.

Therefore, since it is only necessary to wire the lower part of the pad 43 and the source electrode of the J-FET with metal, it is possible to easily take a countermeasure for parasitic capacitance without adding any circuit element.

FIG. 5 is a plan view of a semiconductor device corresponding to the circuit of FIG. A buffer circuit 54 is provided outside the pad 43.
Are formed, the input end of the buffer circuit 54 is connected to the pad 43, and the output end is connected to the island region 25 below the pad 43 via the contact 46. External connection bonding pads 5 are provided around the semiconductor chip 50.
2 are arranged. Other circuit elements, such as NP
N transistor, resistance element, capacitance element, etc.
The pad 43 is arranged so as to surround the pad 43 in a region excluding 3. The constant current source of FIG. 1 is also arranged in the arrangement area,
The constant current source is connected to the source electrode 31 of the J-FET.
By connecting as shown in FIG. 5, it is possible to realize a configuration in which the buffer circuit 6 (54) can be connected to the connection point between the parasitic capacitances 3 and 4, as shown in FIG.

[0030]

According to the present invention, a pad having a high input impedance and a low capacitance can be formed, and the attenuation of an input signal at the pad can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a cross-sectional view of the semiconductor device when the circuit of FIG. 2 is integrated.

FIG. 4 is a plan view of the semiconductor device when the circuit of FIG. 2 is integrated.

FIG. 5 is a plan view of the semiconductor device when the circuit of FIG. 1 is integrated.

FIG. 6 is a circuit diagram showing a conventional example.

FIG. 7 is a sectional view of a semiconductor substrate on which an input pad is formed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pad 2 J-FET 3, 4 Parasitic capacitance 5 Constant current source 6 Buffer circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/06 21/337 29/808 F term (Reference) 5F038 BE07 CA09 CA10 CD05 CD14 DF01 EZ01 EZ20 5F082 AA06 AA25 AA36 BA02 BA12 BA48 BA50 BC01 BC08 BC13 DA06 FA11 GA04 5F102 FA10 GA12 GA17 GB01 GC01 GD04 GJ03 GL03 GR08 GV03 HC01

Claims (5)

[Claims] 1. A semiconductor device having a pad to which an input signal is applied from the outside, comprising: a source follower circuit region formed on a semiconductor substrate and connected to said pad; A semiconductor device connected to an output terminal of a circuit area. 2. An island region surrounded by an isolation region with an insulating film interposed therebetween is formed below the pad, and an output end of the source follower circuit is connected to the island region. 2. The semiconductor device according to claim 1, wherein 3. The semiconductor device according to claim 2, wherein an output end of said source follower circuit region and said island region are wired with metal. 4. A semiconductor device having a pad to which an input signal is applied from the outside, wherein the input device is formed on a semiconductor substrate, and an input terminal is formed on the semiconductor substrate; A buffer circuit region having an input terminal connected to the pad and an output terminal connected to the lower portion of the pad, and connecting the lower portion of the pad to an output terminal of the buffer circuit region. Semiconductor device. 5. An island region surrounded by an isolation region with an insulating film interposed therebetween is formed below the pad, and an output terminal of the source follower circuit is connected to the island region. The semiconductor device according to claim 4, wherein