JP2000251490A - Register circuit and semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which switching normal operation or standby operation of an internal circuit and reduction of a sub-thrshold current at the time of standby operation can be performed based on a common control signal. SOLUTION: A semiconductor integrated circuit device 110 is provided with internal circuits 51, 52, 60, register circuits 11-14, 20, and an internal block control circuit 30. The internal block control circuit 30 generates a control signal CKE1-CKE5 for shifting a corresponding internal circuit or a register circuit to a standby state. The register circuits 11-14, 20 receive control signals CKE1-CKE5 corresponding to each circuit, stop latch operation, and hold a state of output data. Each internal circuit reduces sub-threshold current by switching a level of a drive power source potential in accordance with corresponding control signals CKE1-CKE5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, to a register circuit capable of stopping a data latch operation in accordance with a control signal and fixing output data at a predetermined level, and using the register circuit. The present invention relates to a semiconductor integrated circuit device that can achieve low power consumption by performing the above operation.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, in order to create a large-scale circuit, it is important to design a synchronous system circuit that operates a plurality of circuits in synchronization using a clock signal serving as a reference for the entire circuit. is there. However, in the synchronous system circuit, since the latch functions of all related circuits operate in response to the clock signal, power consumption increases. For this reason, as the capacity of the semiconductor integrated circuit device increases, a technique for solving this problem and reducing power consumption is particularly required.

[0003] In a synchronous system, a method of processing a combinational logic circuit for each clock signal is generally used.

FIG. 9 shows a general synchronous system circuit 200.
FIG. 2 is a schematic block diagram showing the configuration of FIG.

Referring to FIG. 9, synchronous system circuit 200
Receive the input data Din, register circuits LA1 to LA3 and combinational logic circuits CL1,
This is a circuit which performs data transfer or data processing by CL2 and generates output data Dout.

A synchronous system circuit 200 operates in response to a clock signal CLK1, latches input data Din and outputs data D1, and a register circuit LA1.
1 and a predetermined logical operation is performed to obtain the operation result as data D
And a combinational logic circuit CL1 that outputs the data as 2. The synchronization system circuit 200 further includes a clock signal CLK.
2, a register circuit LA2 that receives data D2, latches the data D2, and outputs data D3, a combinational logic circuit CL2 that receives data D3, performs a predetermined logical operation, and outputs data D4, and a clock signal CLK1. It operates based on the data D4 and latches it to output data D
and a register circuit LA3 for outputting as out.

The clock signals CLK1 and CLK2 are
This is a two-phase non-overlapping clock signal, which is repeatedly activated and deactivated with a shift of 周期 cycle. Clock signal C
LK1 is a register circuit LA1 and a register circuit LA.
3 and the clock signal CLK2 is input to the register circuit LA2.

Register circuits LA1 to LA3 take in data applied to the input terminal when the clock signal input to the clock terminal is at the H level, and output data latched while the clock signal is at the L level from the output terminal. . That is, the register circuits LA1 to LA3 play a role of sequentially transferring data every clock based on the clock signal.

Next, the operation of the synchronous system circuit 200 will be described with reference to a timing chart.

FIG. 10 is a timing chart for explaining the operation of synchronous system circuit 200.

Referring to FIG. 10, clock signal CLK1
And CLK2 do not go to the H level at the same time, that is, repeat the H level and the L level with a timing margin given to maintain a non-overlapping state.

First, at the falling timing of clock signal CLK1 at time ta, input data Din is taken into register circuit LA1 and latched. The register circuit LA1 outputs the latched data as data D1, and supplies the data D1 to the combinational logic circuit CL1. Combinational logic circuit C
L1 receives data D1, performs a predetermined logical operation, and outputs data D2. However, data D2 is not transferred first by register circuit 2 until the timing when clock signal CLK2 falls.

Next, at time tb when clock signal CLK2 falls from H level to L level, output data D2 of combinational logic circuit CL1 is taken into register circuit LA2 and latched. The register circuit LA2 outputs the latched data as data D3. Data D3 is sent to combinational logic circuit CL2, and a predetermined logical operation process is performed. The combinational logic circuit CL2 outputs data D4 as a result of the logical operation.

Next, at time tc when clock signal CLK1 falls from H level to L level again, register circuit LA3 is activated to take in and latch data D4, and output output data Dout. By arranging the register circuit for transferring data based on the clock signal at the input portion and the output portion of the combinational logic circuit, the combinational logic circuit also performs the logical operation processing in synchronization with the clock signal. Becomes

In the synchronous system circuit, data processing is executed in synchronization with the clock signal as described above.
However, in a large-scale semiconductor integrated circuit device having a large number of synchronous system circuits, it is not necessary to operate all the synchronous system circuits when performing a predetermined data processing operation. In many cases, it is possible to perform a predetermined operation simply by activating the circuit. Therefore, in order to reduce the current consumption of the semiconductor integrated circuit device, a method of partially activating the synchronous system circuit has been developed.

In this method, even if a clock signal provided as a reference signal for the entire semiconductor integrated circuit device is operating, the operation of the related synchronous system circuit is interrupted by interrupting the latch operation of the register circuit. Is generally adopted to reduce power consumption.

FIG. 11 is adopted in such a case.
FIG. 9 is a block diagram for explaining a configuration of a conventional register circuit with a clock gate.

Referring to FIG. 11, a register circuit 120 with a clock gate includes a NAND gate 12 having two inputs of a clock signal CLK and a clock enable signal CKE.
2 and a D flip-flop 121 receiving the output of the NAND gate 122 at the clock terminal.

As is well known, the D flip-flop outputs the input data supplied to the D terminal as it is from the Q terminal when the L level is supplied to the clock terminal CL. On the other hand, when the state of the clock terminal CL is at the H level, the state of the output terminal Q is maintained.

The clock signal CLK is a reference clock signal commonly applied to the entire semiconductor integrated circuit device. The clock enable signal CKE is provided for each partial block in the semiconductor integrated circuit device. This is a signal for inactivating the operation.

By applying the NAND operation result of the clock signal CLK and the clock enable signal CKE to the clock terminal CL of the D flip-flop, the operation of the register circuit 120 with a clock gate is as follows.

FIG. 12 shows input signals DAT, CLK and CK in register circuit 120 with clock gate.
FIG. 4 is a diagram for explaining a relationship between E and an output signal Y.

Referring to FIG. 12, when clock signal CLK and clock enable signal CKE are both at H level, the input to clock terminal CL is at L level, so that the output signal of D flip-flop 121 is Y is a form in which the input data DAT is transferred as it is.

On the other hand, when one of the clock signal CLK and the clock enable signal CKE goes low, the input of the clock terminal CL goes high, so that the output signal Y of the output terminal Q remains unchanged. Will be held.

That is, in the register circuit with clock gate 120, the latch operation of the register circuit 120 is interrupted by forcibly setting the clock enable signal CKE to L level even when the clock signal CLK is operating. be able to. The interruption of the latch operation of the register circuit eliminates the need for the combinational logic circuit receiving the output of the register circuit to operate, so that a series of these internal system circuits can be brought into a standby state.

As described above, with respect to the operation of the entire semiconductor integrated circuit device, only the synchronous system circuit that needs to operate is operated as a partial block, and for each partial block,
By setting the standby state and the operation state finely, it is possible to reduce power consumption as a whole.

On the other hand, as the miniaturization technology advances, the transistor size is reduced, and the operating power supply voltage tends to be set lower in conjunction with the decrease in transistor breakdown voltage. In addition, in application fields such as portable devices, in which demand is rapidly increasing in recent years, battery driving is a prerequisite, and it is indispensable to reduce power consumption by lowering operating voltage.

In order to realize a low voltage operation while maintaining the operation speed of the transistor, it is necessary to lower the threshold voltage of the transistor. However, as the threshold voltage decreases, the transistor cannot be cut off sufficiently, and the leakage current at the time of OFF, that is, the current consumption during the standby operation due to an increase in the subthreshold current tends to increase. Various techniques have been proposed to address this problem.

FIG. 13 is a circuit diagram showing a configuration of an internal circuit 150 to which a configuration to which power supply wiring provided in a hierarchy is applied (hereinafter, referred to as an SCRC configuration) is applied.

Referring to FIG. 13, an internal circuit 150 is a circuit that performs predetermined arithmetic processing on input data by a logic circuit 156 and outputs the result.

The logic circuit 156 includes, for example, four inverters each composed of a set of a P-channel MOS transistor and an N-channel MOS transistor. P channel MOS transistors QSP1 to QSP4 in the logic circuit
Receives the power supply voltage from the wiring 151 transmitting the power supply voltage Vdd or the wiring 152 connected to the wiring 151 through the transistor QHP1. Similarly, N-channel MOS transistors QSN1 to QSN in the inverter
4 receives the supply of the ground potential from either the wiring 154 for supplying the ground potential Vss or the wiring 153 connected to the wiring 154 and the transistor QHN1.

Transistors QHP and QHN1 operate according to hierarchical power supply control signal SCR. The hierarchical power supply control signal SCR is a signal that is activated (H level) during the normal operation of the internal circuit 150 and is inactivated (L level) during the standby operation.

In FIG. 13, during normal operation, that is,
A case where the control signal SCR is activated (H level) is shown. In this case, transistor QHN1
And QHN are turned on, the potential of the wiring 152 becomes equal to the power supply potential Vdd, and the potential Vn of the wiring 153 becomes equal to the ground potential Vss.

As a result, each transistor constituting the logic circuit 156 is connected to the power supply potential Vdd or the ground potential Vss.
As a result, it is possible to execute a predetermined logic operation at a high speed under the supply of a sufficient drive current.

FIG. 14 is a circuit diagram for explaining the operation of internal circuit 150 during standby operation, that is, when hierarchical power supply control signal SCR is inactive (L level).

Referring to FIG. 14, during the standby operation, transistors QHP1 and QHN1 are turned off, so that potential Vp of wiring 152 drops below power supply potential Vdd by the threshold voltage of transistor QHP, and wiring 1
The potential Vn of the transistor 53 is higher than the ground potential Vss by
It rises by the threshold voltage of HN1.

Here, assuming that the level of the input signal during the standby operation is previously determined to be L level, the source of transistor QSP1 is connected to wiring 151, and the source of transistor QSN1 is connected to wiring 153. Thereby, the transistor QSP1 which is turned on can be driven by the power supply potential Vdd, and the gate-source voltage of the transistor QSN1 which is turned off can be reduced by the threshold voltage of the transistor QHN1. Thus, the sub-threshold current can be reduced by cutting off the transistor that is turned off more strongly.

Similarly, in transistors QSP2 and QSN2 having node n1 as an input, the source of transistor QSN2 turned on is connected to wiring 154 transmitting ground potential Vss, and the source of transistor QSP2 turned off. Is connected to the wiring 152 transmitting Vp, the transistor QSP2 is turned off more strongly, and the subthreshold current can be reduced even under low voltage operation.

In the following, the same connection form is applied to the inverter constituted by transistors QSP3 and QSN3 and transistors QSP4 and QSN4, whereby the potential of each output node can be maintained and the subthreshold current can be reduced. Become.

As described above, in the standby state, when the level of the input signal is known in advance, the sub-threshold current is reduced by applying a circuit connection according to the state of the input signal to the logic circuit. Becomes possible. That is, in an internal circuit, such as a memory circuit, which needs to fix the logic level of an input signal in a standby state, in order to reduce a leak current during a standby operation under a low voltage operation, the above-described SCRC is used. It is necessary to apply the configuration.

FIG. 15 shows another technique for reducing the leakage current during the standby operation, ie, Multi-Threshho.
FIG. 3 is a circuit diagram showing a configuration of an internal circuit 160 to which an ld-CMOS configuration (hereinafter, referred to as an MT-CMOS configuration) is applied.

Referring to FIG. 15, internal circuit 160 includes, for example, logic circuit 165 composed of four stages of inverters, similarly to internal circuit 150. The logic circuit 165 includes transistors QMP1 to QMP4 and a transistor QMN1.
To QMN4. Sources of transistors QMP1 to QMP4 are connected to a wiring 162 transmitting potential Vp. Similarly, the sources of transistors QMN1-QMN4 are connected to wiring 163 transmitting voltage Vn. On the other hand, substrate regions (hereinafter, referred to as body regions) immediately below the gates of transistors QMP1 to QMP4 are connected to wiring 161 and the substrate potentials of these P-channel MOS transistors are set to power supply potential Vdd. Similarly, transistor Q
The body regions of MN1 to QMN4 are connected to wiring 164, and the substrate potentials of these N-channel MOS transistors are set to ground potential Vss.

The wiring 16 for transmitting the power supply potential Vdd
1 and a wiring 162 transmitting voltage Vp, a transistor QH receiving at its gate an inverted signal of control signal SCR
P2 and a diode DP connected with the direction from the wiring 161 to the wiring 162 as a forward direction are provided. Similarly, a transistor QHN2 and a diode DN are provided between the wiring 163 and the wiring 164.

In the internal circuit 160, the control signal SC
The activation and deactivation of R changes depending on the normal operation and the standby operation.

FIG. 16 shows the potential Vp of the wiring 162 and the potential Vn of the wiring 163 between the normal operation and the standby operation.
It is a conceptual diagram for explaining the change of.

In normal operation, control signal SCR is activated (H level), so that potential V
p is equal to the power supply potential Vdd, and the potential V
n becomes equal to the ground potential Vss.

On the other hand, in a standby operation in which control signal SCR is inactivated (L level), potential Vp falls below Vdd by the action of diode DP. Similarly, due to the action of diode DN, potential Vn rises above ground potential Vss.

The substrate potential of transistors QMP1 to QMP4 is equal to power supply potential Vd regardless of the state of control signal SCR.
d level. Similarly, transistors QMN1 to QMN
The substrate potential of N4 is also always at the level of the ground potential Vss. Therefore, during the standby operation, the source potential of each transistor rises or falls according to the change of the control signal SCR, and accordingly, the substrate potential becomes relatively deep, and the transistor is turned off more strongly. As a result, the subthreshold current is reduced.

The internal circuit employing the MT-CMOS structure has an effect that the reduction of the subthreshold current can be suppressed even when the signal level of the input node during standby operation cannot be predicted in advance. For an internal circuit such as a combinational logic circuit that does not need to fix the logic level of the input signal in the standby state, the above-described MT- A CMOS configuration can be applied.

However, the potential Vp of the wiring 162 and the potential Vn of the wiring 163 can be reduced only to the extent that each inverter can continue to operate. Therefore, the effect of reducing the sub-threshold current is reduced by the internal circuit using the SCRC structure. It is inferior.

[0051]

As described above, a technique for selectively operating a register circuit in a necessary area to reduce current consumption during normal operation, and
There has been proposed a technique for reducing a standby current by reducing a subthreshold current of a transistor in an off state during a standby operation.

However, it is not possible to efficiently reduce power consumption only by applying both technologies independently. That is, the latch operation of the register circuit is stopped by the clock enable signal, and when the output data does not change, the subsequent combinational logic circuit does not need to operate, and can shift to the standby operation. Reducing the current
This is necessary under the recent trend of low voltage operation.

On the other hand, for an internal circuit having an SCRC configuration or an MT-CMOS configuration capable of reducing current consumption during standby operation, a new control signal for instructing transition to standby operation is required. Become. That is, a new control circuit that activates the control signal SCR shown in FIGS. 13 and 15 at a desired timing after synchronizing with the other control signals is required. This arrangement of the new control circuit has disadvantages such as an increase in circuit elements and an increase in layout area.

An object of the present invention is to solve the above-mentioned problems, and more specifically, a normal operation and a standby operation of an internal circuit (combinational logic circuit) based on a single control signal. It is an object of the present invention to provide a semiconductor integrated circuit device capable of switching between the above and controlling the reduction of the subthreshold current during the standby operation.

[0055]

According to a first aspect of the present invention, there is provided a register circuit that operates based on two control clock signals and temporarily stores an input digital signal. And when both of the first and second control clock signals are inactivated, a storage data signal having the same signal level as that of the input digital signal is output. When one of them is activated, the first signal processing circuit holding the state of the storage data signal, and the level of the output data signal is changed according to the storage data signal and the first control clock signal. One of a first process for setting the same signal level as the signal and a second process for fixing the level of the output data signal to a predetermined one of the digital signal levels Selected and and a second signal processing circuit to perform.

According to a second aspect of the present invention, there is provided a register circuit according to the first aspect.
The register circuit according to claim 1, wherein the first signal processing circuit includes:
When activation is instructed, the level of the storage data signal is made the same as the input digital signal, and when deactivation is instructed, a storage circuit that holds the level of the storage data signal, And a storage operation activating circuit for instructing activation of the storage circuit in accordance with the level of the second control clock signal, wherein the second signal processing circuit is provided when the first control clock signal is activated. Has an output data signal generating circuit for performing a first process, and when the first control clock signal is inactive, performing a second process to generate an output data signal.

According to a third aspect of the present invention, there is provided a register circuit.
The register circuit according to claim 1, wherein the storage operation activation circuit comprises:
NAN with first and second control clock signals as inputs
D has a first logical operation gate for outputting a logical operation result, the storage circuit receives an output of the first logical operation gate at a clock terminal, receives a digital signal at an input terminal, and outputs a storage data signal from an output terminal. And a second flip-flop circuit for generating a NAND logic operation result as an output data signal using the first control clock signal and the inverted signal of the storage data signal as inputs. It has a logical operation gate.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device for executing predetermined data processing based on a clock signal, comprising: an internal block including a circuit group required for predetermined data processing; An internal block control circuit that generates an operation control signal for instructing either a standby operation or a normal operation on the block,
When a normal operation is instructed by the operation control signal, the internal block outputs a register circuit that outputs an input data signal having the same signal level as the input digital signal in response to the clock signal, and an input from the register circuit. An internal circuit for receiving a data signal and performing predetermined data processing to generate an output data signal; an internal circuit receiving the input data signal and performing predetermined data processing; and a logical operation circuit And a power supply switching circuit that drives the first potential and a second potential lower than the first potential when the normal operation is instructed by the operation control signal. The potential is supplied to the logic operation circuit as a potential, and when a standby operation is instructed by the operation control signal, the potential is lower than the first potential and higher than the second potential. Third potential and further supplied to the logic circuit and a fourth potential lower than the third potential higher than the second potential as a driving power source potential.

A semiconductor integrated circuit device according to a fifth aspect is the semiconductor integrated circuit device according to the fourth aspect, wherein the logic operation circuit is supplied with the first and fourth power supply potentials during a standby operation. It includes a first logic gate and a second logic gate supplied with the second and third power supply potentials during a standby operation, and the first logic gate is known to be turned on during a standby operation. A first M of the first conductivity type
An OS transistor; and a second MOS transistor of a second conductivity type that is known to be turned off during the standby operation, and the second logic gate is known to be turned on during the standby operation. A third MOS transistor of a conductivity type and a fourth MOS transistor of a first conductivity type, which is known to be turned off during the standby operation, wherein the register circuit is instructed to perform a standby operation by an operation control signal; If so, the level of the data signal is fixed to one of the predetermined states.

A semiconductor integrated circuit device according to a sixth aspect is the semiconductor integrated circuit device according to the fifth aspect, wherein the power supply switching circuit includes a first power supply line for supplying a first potential, and a second potential. A first power supply line, a first power supply line, a second power supply line, a first power supply line, a first power supply line, a first power supply line, and a second power supply line. A third power supply line connected to the power supply line; and a fourth power supply line connected to the second power supply line via the second control transistor, wherein a source terminal of the first MOS transistor is provided. Is connected to the first power supply line, and the source terminal of the second MOS transistor is
The source terminal of the third MOS transistor is connected to the fourth power supply line, and the source terminal of the third MOS transistor is connected to the second power supply line.
The source terminal of the OS transistor is connected to a third power supply wiring.

A semiconductor integrated circuit device according to a seventh aspect of the present invention is the semiconductor integrated circuit device according to the fourth aspect, wherein the logical operation circuit has a first conductivity type M for performing predetermined data processing.
An OS transistor and a second conductivity type MOS transistor, wherein the power supply switching circuit supplies a first potential as a substrate potential to the first conductivity type MOS transistor, and supplies a first potential to the second conductivity type MOS transistor. Second
Is supplied as a substrate potential, and during a standby operation, a third potential is supplied to the source terminal of the first conductivity type MOS transistor and the second conductivity type MO transistor is supplied.
A fourth potential is supplied to the source terminal of the S transistor.

The semiconductor integrated circuit device according to claim 8 is the semiconductor integrated circuit device according to claim 7, wherein the power supply switching circuit comprises a first power supply line for supplying a first potential, and a second potential supply line. And a second power supply line for supplying power during normal operation and turning off during standby operation according to an operation control signal.
And a second control transistor, a third power supply line connected to the first power supply line via the first control transistor, and a second power supply line connected to the third power supply line via the second control transistor. A fourth power supply wiring, a first diode connecting the first power supply wiring to the second power supply wiring with a direction from the first power supply wiring toward the second power supply wiring being a forward direction, And a second diode connecting the third power supply line and the fourth power supply line, with the direction from the power supply line to the fourth power supply line as a forward direction, , The source terminal is connected to the third power supply line, the region immediately below the gate is connected to the first power supply line, and the source terminal of the second conductivity type MOS transistor is connected to the fourth power supply line; The area immediately below the gate is the second power supply. It is connected to the wiring.

[0063]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[First Embodiment] First, in order to explain the configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention, a semiconductor integrated circuit device 100 in which the above two conventional techniques are simply combined will be described. explain.

FIG. 1 is a schematic block diagram illustrating the overall configuration of a semiconductor integrated circuit device 100.

Referring to FIG. 1, semiconductor integrated circuit device 10
0 denotes registers 11, 12, and 13 provided for converting input data Di into output data Do1 and internal circuit 5;
1 and 52. Here, the internal circuits 51 and 52
Is a circuit represented by a combinational logic circuit, which does not need to fix the logic of the input node during the standby operation. The sub-threshold current during the standby operation is reduced by applying the MT-CMOS configuration described in FIG. 15 to the internal circuits 51 and 52.

The semiconductor integrated circuit device 100 is a circuit for converting input data Di to output data Do2.
It further includes registers 14 and 15 and an internal circuit 60 arranged at a subsequent stage of the internal circuit 51. The internal circuit 60 is a circuit, such as a memory circuit, which needs to fix the signal state of the input node during a standby operation. Therefore, the SCRC configuration described with reference to FIG. 13 is applied to the internal circuit 60 to reduce the sub-threshold current during the standby operation.

The configuration and operation of the registers 11 to 15 are as follows.
Since it is as described in FIGS. 11 and 12, the description will not be repeated.

Semiconductor integrated circuit device 100 has a clock for selectively instructing the normal operation and the standby operation of each register and internal circuit in order to operate only the necessary register circuit and internal circuit according to the control signal. Internal block control circuit 3 for generating enable signals CKE1 to CKE5
0 and a sub-threshold current control circuit 40 that generates a control signal SCR for controlling the operation of the MT-CMOS component included in the internal circuits 51 and 52 and the SCRC component included in the internal circuit 60.

In the semiconductor integrated circuit device 100, for example, when it is desired to output only the output data Do1, the register circuit 11 → the internal circuit 51 → the register circuit 12 → the internal circuit 52 → the register circuit 13 can be operated as desired. An output signal is obtained. At this time, the register circuit 1
4, 15 and the internal circuit 60 need not operate. However, clock signals CLK1 and CLK2 input to register circuits 14 and 15 are
13 is common to the clock signal used in FIG.

When only the data Do1 is required as described above, the internal block control circuit 30 sets the clock enable signals CKE4 and CKE5 in order to set the register circuits 14, 15 and the internal circuit 60 to the standby operation.
Activate. Thereby, the register circuits 14 and 15
Is in a holding state, so that the internal circuit 60 does not need to operate, and these circuits can be put into a standby operation, so that the power consumption of the entire semiconductor integrated circuit device can be reduced.

Further, the internal circuit 60 during the standby operation
In order to further reduce the subthreshold current and further reduce the power, the SCRC component in the internal circuit 60 is operated. At this time, for example, a sub-threshold current control circuit 40 that specially generates a control signal SCR activated after a lapse of a predetermined time in synchronization with the timing of the clock enable signals CKE and CKE5 is required.

Similarly, when only the output data Do2 is required, only the operation of the register circuit 11 → the internal circuit 51 → the register circuit 15 → the internal circuit 60 → the register circuit 14 is required, and the register circuits 12, 13 and The internal circuit 52 does not need to operate. Therefore, in this case, by activating the clock enable signals CKE2 and CKE3 by the internal block control circuit 30, these unnecessary circuits can be put into a standby operation and the power consumption of the entire semiconductor integrated circuit device can be reduced.

Further, in order to reduce the sub-threshold current in the standby operation of internal circuit 52, a control signal SCR is applied to internal circuit 52 from sub-threshold current control circuit 40.

As described above, the semiconductor integrated circuit device 100
By operating only the necessary internal circuits in accordance with the data signals to be output, the power consumption of the entire semiconductor integrated circuit device is reduced, and the sub-threshold current is reduced for the internal circuits in the standby operation. Further, lower power consumption can be achieved.

However, it is necessary to newly generate a control signal SCR for controlling the operation of the SCRC component or the MT-CMOS component for reducing the subthreshold current included in the internal circuit. The sub-threshold current control circuit 40 which is a new control signal generation circuit is required.

In general, a complicated timing design tends to be required for the control signal generated when the mode is switched between the normal operation and the standby operation, and the sub-threshold current control circuit 40 provided for this purpose is required to have a complicated timing design. The configuration also tends to be complicated. Therefore, if the control of the circuit for reducing the subthreshold current can be performed more simply, for example, by a clock enable signal designating selection between the normal operation and the standby operation of the internal circuit, the above-described complicated control signal Is unnecessary, and the configuration of the entire semiconductor integrated circuit device can be made efficient.

FIG. 2 is a block diagram for explaining the overall configuration of semiconductor integrated circuit device 110 according to the first embodiment of the present invention.

Referring to FIG. 2, semiconductor integrated circuit device 110
Has five register circuits and three internal circuits similarly to the semiconductor integrated circuit device 100 of FIG.
This is a circuit for generating output data Do1 and Do2 from i.

The semiconductor integrated circuit device 110 performs the same operation as the semiconductor integrated circuit device 100 and achieves low power consumption. However, the semiconductor integrated circuit device 110 does not require the subthreshold current control circuit 40. Is characterized in that the configuration of the register circuit 20 provided corresponding to the internal circuit 60 which needs to fix the data state of the input node is different from the register circuits 11 to 14 described above.

FIG. 3 is a circuit diagram for describing the configuration of register circuit 20. Referring to FIG. 3, register circuit 20 includes a NAND gate 22 having two inputs of clock signal CLK and clock enable signal CKE, and NAN
The D flip-flop 21 receives the output of the D gate 22 at the clock terminal CL and latches and transfers the data DAT input to the data terminal D. The terminal QC and the clock enable signal CKE output the inverted signal NY of the latch data. And a NAND gate 23 as an input. The output of the NAND gate 23 becomes the output signal Y of the register circuit 20.

D flip-flop 21 and NAND gate 22 perform the same operation as conventional register circuit 120. The register circuit 20 is further characterized in that it has a NAND gate 23 to which one of the inputs is the clock enable signal CKE.

FIG. 4 is a diagram showing the correspondence between the state of each input signal and the state of an output signal in the register circuit 20.

Referring to FIG. 4, when both clock signal CLK and clock enable signal CKE are at H level, D flip-flop 21 sets input data D
AT is latched and output. The inverted signal NY of the latch data and the clock enable signal C
In this case, the output signal Y is a result of latching and outputting the input data DAT.

Next, when the clock signal CLK goes low, the input of the clock terminal CL of the D flip-flop 21 goes low, so that the output data of the D flip-flop is held and should be held. An inverted signal of the data is output as signal NY. The signal N
A signal Y, which is an output of a NAND gate having two inputs of Y and a clock enable signal CKE at H level, is an inverted state of the signal NY and becomes equal to data to be held.

On the other hand, when the clock enable signal CKE is L
When the level is set to the level, the D flip-flop 2
Since one of the input of the clock terminal 1 and the input of the NAND gate 23 is forcibly set to the L level, the output signal Y of the register circuit 20 is fixed at the H level regardless of the state of the other input signals. Is done.

As described above, with respect to register circuit 20, when clock enable signal CKE is at H level, the data latch operation by the normal D flip-flop is performed, while when the CKE signal is at L level. Has a function of forcibly fixing the output signal Y to the H level irrespective of the state of other input data.

FIG. 5 is a circuit diagram for describing an operation of arranging register circuit 20 at a stage preceding internal circuit 60 to reduce a subthreshold current.

Referring to FIG. 5, when the state of input node NC1 at the time of standby operation is at the H level, internal circuit 60 determines the connection of the SCRC configuration so that the subthreshold current can be reduced more effectively. Circuit.

Output signal Y of register circuit 20 is applied to input node NC 1 of internal circuit 60. That is,
When the clock enable signal CKE is set to the L level, the register circuit 20 stops the latch operation, holds the data of the output node, and outputs the output signal Y.
Is fixed to the H level.

During the standby operation of the register circuit 20,
Clock enable signal CKE is at L level. At this time, the data at the input node CL1 is simultaneously fixed to the H level in response to the activation of the clock enable signal CKE, so that the internal circuit 60 does not need to operate. Therefore, the transistors QHP1 and QHN1 of the SCRC component described with reference to FIG.
E enables common control.

Thus, the clock enable signal CK
E causes the register circuit 20 to shift to the standby operation, and the internal circuit 60 that no longer needs to operate.
, It is possible to start switching of the power supply wiring for reducing the subthreshold current.

FIG. 6 is a timing chart for explaining the operation of register circuit 20 and internal circuit 60 described above.

Referring to FIG. 6, at time t11, internal circuit 60 is performing a normal operation, and clock enable signal CKE is at H level. At this timing, when clock signal CLK falls from H level to L level, register circuit 20 latches input signal DAT and holds data in output signal Y.

At time t12 when internal circuit 60 continues the normal operation, the operation of register circuit 20 is the same even when the clock signal shifts from the H level to the L level again.

Next, at time t13, when the clock enable signal CKE shifts from the H level to the L level, the register circuit 20 stops the latch operation. Further, in the register circuit 20, the signal NY at the inverted output terminal QC of the D flip-flop 21 maintains the inverted state of the held data at t12, while the output signal Y shifts to the H level and is fixed.

Accordingly, in internal circuit 60, S
By turning off the transistors QHP1 and QHN1 in the CRC component, the subthreshold current is reduced.

Further, while clock enable signal CKE is at L level, register circuit 20 does not perform a latch operation even when clock signal CLK shifts from H level to L level at times t14 and t15, and at time t14.
In step 12, the inverted signal of the held data is held in the signal NY. Therefore, during this period, the register circuit 20 enters a standby operation and stops operating, and the internal circuit 60 reduces the subthreshold current during the standby operation.

Thereafter, when clock enable signal CKE rises from L level to H level at time t16, while clock signal CLK is at L level, ie, D
By obtaining the inverted signal of the signal NY as the output signal Y by the NAND gate 23 until the flip-flop 21 resumes the latch operation, the latch data originally held at the time t12 can be reduced. As a result, the clock signal CLK rises to the H level, and the clock input terminal C of the D flip-flop 21
The state before the transition to the standby operation can be recovered until L goes low again and the data latch operation is started.

[Second Embodiment] In a second embodiment, the operation of the register circuits in internal circuits 51 and 52 in which the signal state of the input node is not fixed during the standby operation will be described.

FIG. 7 shows the register circuit 11 and the internal circuit 51.
FIG. 11 is a circuit diagram for describing an operation of reducing a sub-threshold current by a combination with.

Referring to FIG. 7, input node NC2 of internal circuit 51 is connected to the output node of register circuit 11.

The configuration of register circuit 11 is the same as that of register circuit with clock gate 120 described with reference to FIG. 11, and when either clock enable signal CLK or CKE goes to L level, the data latch operation is performed. It stops the operation and holds the signal state of the output node at that time.

That is, in the register circuit 11,
Even when the latch operation is interrupted by clock enable signal CKE, the state of output signal Y is undefined. Therefore, internal circuit 51 receiving output signal Y has a circuit configuration for reducing the subthreshold current by the MT-CMOS configuration.

In the internal circuit 51, the MT-C
Clock enable signal CKE is applied to the gates of transistors QHP2 and QNP2 in the MOS component.
Thereby, the internal circuit 51 can reduce the subthreshold current at the same timing as when the register circuit 11 stops the latch operation.

With such a configuration, the control signal CKE for instructing the latch circuit 11 to stop the latch operation is commonly used without using a special control circuit, so that the standby operation of the internal circuit 51 can be performed. The sub-threshold current at the time can be reduced.

FIG. 8 is an operation waveform diagram for describing the overall operation of register circuit 11 and internal circuit 51.

Referring to FIG. 8, clock signal CLK is a reference signal in the entire semiconductor integrated circuit device.
It is always activated irrespective of the operation mode of the internal circuit 51, and repeats the H level and the L level at a constant cycle.

At times t21 and t22, clock enable signal CKE is at the H level, and internal circuit 51 is in a period during which normal operation is performed. Therefore, at the falling timing of clock signal CLK, input data DAT is applied to register circuit 11 is latched by the output signal Y.

Next, at time t23, clock enable signal CKE shifts from the H level to the L level, and a standby operation is instructed to register circuit 11 and internal circuit 51. Further, with the transition of clock enable signal CKE to L level, register circuit 11 stops the latch operation, and output signal Y holds the data latched at time t22.

Thereafter, while signal CKE is at L level, input data DAT is not taken into register circuit 11 even at falling timings t24 and t25 of clock signal CLK, and output signal Y is maintained. is there. Further, in this period, since transistors QHP2 and QNP2 are off in internal circuit 51, the subthreshold current is reduced.

Further, after clock enable signal CKE returns to the H level at time t26, register circuit 11 performs a latch operation of input data DAT in accordance with clock signal CLK, and can perform a normal operation. . Similarly, in internal circuit 51, normal logic operation can be performed by turning on transistors QHP2 and QNP2.

With such a configuration, the interrupt of the latch operation of the register circuit and the interruption of the standby operation can be performed by the common clock enable signal CKE even for the internal circuit in which the state of the input node is not fixed during the standby operation. , The switching control of the power supply potential for reducing the subthreshold current can be performed at the same time.

It should be noted that the embodiment disclosed this time is an example in all respects and is not intended to be limiting. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0115]

According to the first, second, and third register circuits, the output signal can be fixed in accordance with the activation of the first control clock signal. During the standby operation, the output signal can be fixed at a desired state.

In the semiconductor integrated circuit device according to the fourth, seventh and eighth aspects, either the standby operation or the normal operation can be set for each internal block that needs to be operated for each predetermined data processing,
Since the power supply for driving the internal circuit is switched during the standby operation, it is possible to reduce power consumption during both the normal operation and the standby operation.

According to the semiconductor integrated circuit device of the fifth and sixth aspects, in addition to the effect of the semiconductor integrated circuit device of the fourth aspect, the semiconductor integrated circuit device waits for an internal circuit that needs to fix an input signal during a standby operation. Power consumption during operation can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a semiconductor integrated circuit device 100 for describing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a schematic block diagram illustrating an overall configuration of a semiconductor integrated circuit device 110 according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a register circuit 20.

FIG. 4 is a diagram showing the correspondence between the state of each input signal and the state of an output signal of the register circuit 20;

FIG. 5 is a circuit diagram for explaining an operation of reducing a subthreshold current by a combination of an internal circuit 60 in which a signal state of an input node is fixed during a standby operation and a register circuit 20;

FIG. 6 is a timing chart for explaining the overall operation of the circuit of FIG. 5;

FIG. 7 is a circuit diagram illustrating an operation of reducing a subthreshold current by a combination of an internal circuit and a register circuit in which the state of an input node is not fixed during a standby operation;

FIG. 8 is a timing chart for explaining the overall operation of the circuit of FIG. 7;

FIG. 9 is a schematic block diagram showing a configuration of a general synchronization system circuit 200.

10 is a timing chart for explaining the operation of the synchronization system circuit 200. FIG.

FIG. 11 is a circuit diagram showing a configuration of a register circuit 120 with a clock gate.

FIG. 12 is a diagram for explaining a relationship between each input signal and an output signal of the register circuit with a clock gate 120;

FIG. 13 is a circuit diagram for describing a configuration of an internal circuit 150 to which an SCRC configuration is applied and a state in a normal operation.

FIG. 14 is a diagram illustrating a state of the internal circuit 150 to which the SCRC configuration is applied during a standby operation.

FIG. 15 is an internal circuit 1 to which an MT-CMOS configuration is applied.
FIG. 6 is a circuit diagram showing a configuration of the embodiment.

16 shows potentials Vp and V in internal circuit 160.
FIG. 9 is a diagram for explaining a change between n during a normal operation and during a standby operation.

[Explanation of symbols]

11, 12, 14, 20 register circuit, 30 internal block control circuit, 40 subthreshold current control circuit, 51, 52, 60 internal circuit.

Claims (8)

[Claims] 1. A register circuit that operates based on two control clock signals and temporarily stores an input digital signal, wherein both the first and second control clock signals are inactivated. Output a stored data signal having the same signal level as the input digital signal, and when one of the first and second control clock signals is activated, A first signal processing circuit for holding a state of a storage data signal; and a level of an output data signal set to the same signal level as the storage data signal according to the storage data signal and the first control clock signal. One of a first process and a second process of fixing the level of the output data signal to a predetermined one of the digital signal levels is selected and executed. And a second signal processing circuit, a register circuit. 2. The first signal processing circuit, when activation is instructed, sets the level of the storage data signal to be the same as the input digital signal,
When deactivation is instructed, a storage circuit for holding the level of the storage data signal, and a storage for instructing activation of the storage circuit in accordance with the levels of the first and second control clock signals An operation activation circuit, wherein the second signal processing circuit performs the first processing when the first control clock signal is activated, and inactivates the first control clock signal. 2. The register circuit according to claim 1, further comprising an output data signal generation circuit for performing said second processing when said operation has been performed to generate said output data signal. 3. The storage operation activating circuit includes a first logical operation gate that receives the first and second control clock signals and outputs a NAND logical operation result, and wherein the storage circuit includes A D flip-flop circuit that receives an output of one logical operation gate at a clock terminal, receives the digital signal at an input terminal, and outputs the storage data signal from an output terminal; 3. The register circuit according to claim 2, further comprising a second logical operation gate that receives the first control clock signal and an inverted signal of the storage data signal and generates a NAND logical operation result as the output data signal. 4. A semiconductor integrated circuit device for performing predetermined data processing based on a clock signal, comprising: an internal block including a circuit group required for the predetermined data processing; and a standby operation for the internal block. Or an internal block control circuit that generates an operation control signal for instructing one of the normal operations. The internal block is configured to receive the clock signal when the normal operation is instructed by the operation control signal. A register circuit for outputting an input data signal having the same signal level as the input digital signal, and receiving the input data signal from the register circuit and performing the predetermined data processing to generate an output data signal An internal circuit that receives the input data signal and performs the predetermined data processing. An operation circuit; and a power supply switching circuit that drives the logical operation circuit, wherein the power supply switching circuit is configured to control a first potential and the first potential when the normal operation is instructed by the operation control signal. A second potential lower than the potential is supplied to the logical operation circuit as a drive power supply potential, and when the standby operation is instructed by the operation control signal,
The logical operation is further performed using a third potential lower than the first potential and higher than the second potential and a fourth potential higher than the second potential and lower than the third potential as a drive power supply potential. A semiconductor integrated circuit device that supplies a circuit. 5. The logic operation circuit comprises: a first logic gate supplied with the first and fourth power supply potentials during the standby operation; and a second logic gate during the standby operation. And a second logic gate to which a power supply potential of 3 is supplied, wherein the first logic gate is known to be turned on during the standby operation.
A conductive first MOS transistor; and a second MOS transistor known to be turned off during the standby operation.
A second MOS transistor of a conductivity type, wherein the second logic gate is a third MOS transistor of the second conductivity type, which is known to be turned on during the standby operation; And the fourth MOS transistor of the first conductivity type, which is known to be turned off at the time, wherein the level of the data signal is increased when the standby operation is instructed by the operation control signal. 5. The semiconductor integrated circuit device according to claim 4, wherein the first fixed state is fixed to one of predetermined states. 6. A power supply switching circuit comprising: a first power supply line for supplying the first potential; a second power supply line for supplying the second potential; Turns on during normal operation,
First and second control transistors that are turned off during the standby operation, a third power supply line connected to the first power supply line via the first control transistor, and a second control transistor. And a fourth power supply line connected to the second power supply line via a second power supply line, wherein a source terminal of the first MOS transistor is connected to the first power supply line; A source terminal of the transistor is connected to the fourth power supply line, a source terminal of the third MOS transistor is connected to the second power supply line, and a source terminal of the fourth MOS transistor is connected to the fourth power supply line. The semiconductor integrated circuit device according to claim 5, wherein the semiconductor integrated circuit device is connected to the third power supply wiring. 7. The logic operation circuit includes a first conductivity type MOS transistor and a second conductivity type MOS transistor for performing the predetermined data processing, and the power supply switching circuit includes the first conductivity type MOS transistor. The first potential is supplied as the substrate potential to the MOS transistor of the second conductivity type, and the second potential is supplied as the substrate potential to the second conductivity type MOS transistor. 5. The semiconductor according to claim 4, wherein the third potential is supplied to a source terminal of the first conductivity type MOS transistor, and the fourth potential is supplied to a source terminal of the second conductivity type MOS transistor. Integrated circuit device. 8. The power supply switching circuit, comprising: a first power supply line for supplying the first potential; a second power supply line for supplying the second potential; First and second control transistors that are turned on during the normal operation and turned off during the standby operation; a third power supply line connected to the first power supply line via the first control transistor; A fourth power supply line connected to the second power supply line via the second control transistor; and a fourth direction in which a direction from the first power supply line to the second power supply line is a forward direction. A first diode connecting the first power supply line to the second power supply line; and a third direction from the third power supply line toward the fourth power supply line, wherein the third power supply line is connected to the third power supply line. A second power supply connecting to a fourth power supply wiring A source terminal of the first conductivity type MOS transistor is connected to the third power supply line, and a region immediately below a gate is connected to the first power supply line; 8. The semiconductor integrated circuit device according to claim 7, wherein a source terminal of the conductive type MOS transistor is connected to said fourth power supply line, and a region immediately below a gate is connected to said second power supply line.