JP2000251465A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress reduction of access speed even if an address signal is incremented or decremented by accessing a memory cell array with the prescribed interval when an address signal has been successively incremented or decremented. SOLUTION: When an address signal of (n) bits has been successively incremented or decremented, a memory cell array is accessed by every physical address ±M (M: add number of 3 or more that is 2n-3 or less). Namely, when address signals A2, A1, A0 are successively incremented, a cell array M/A is accessed by every physical address '+3'. By using this constitution, even if address signals A2, A1, A0 are successively incremented, an adjacent array M/A never be accessed continuously. Thereby, reduction of access speed caused when access is switched from one bank to another bank is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-independent bank type semiconductor memory device, and more particularly to an improvement in access speed.

[0002]

2. Description of the Related Art High-speed DRAMs are being developed to improve the data transfer speed.

As one of high-speed DRAMs having improved data transfer speed, there is a DRAM that accesses a single-chip DRAM as if it were a multiple-chip DRAM independently. This is a DRAM called a bank system. Banking DR
In the AM, one chip is divided into a plurality of banks, and while data is read from one bank, word lines are activated and bit lines are precharged in another bank. . This enables high-speed data access.

[0004] The bank type DRAM system has two main types.
It is roughly divided into two. One is a “completely independent bank system” shown in FIG. 19A, and the other is a “non-independent bank system” shown in FIG. 19B.

[0005] The "completely independent bank system" is shown in FIG.
As shown in (1), the parts for configuring the memory core, that is, the memory cell array M / A, the row decoder R / D, the column decoder C / D, the sense amplifier S / A, etc. are completely independent for each bank. However, since these parts are required for each bank, the chip area increases and the manufacturing cost increases.

On the other hand, the "non-independent bank system"
As shown in FIG. 19B, especially the sense amplifier S / A
Is shared between adjacent banks. As a result, the "non-independent bank method" has advantages in that the chip area can be reduced and the manufacturing cost can be reduced as compared with the "completely independent bank method". A typical example of a "non-independent bank" is Rambus D
RAM. However, the "non-independent bank method" has a disadvantage in that, when adjacent banks are continuously accessed, access cannot be performed at the shortest access speed. This is because the data of the shared sense amplifier S / A must be once written back to the memory cell and the bit line must be precharged.

In recent years, demands for transferring a huge amount of data at high speed have been increasing, for example, mainly for DRAMs used for graphical applications. As one solution to satisfy this requirement, it has been considered to use the bank while sequentially incrementing or decrementing it. That is, the memory cell array is continuously accessed. However, at present, as shown in FIGS. 19A and 19B, the assignment of the address signal for selecting the bank is simply 0, as in the order of the physical address of the cell array M / A. 1, 2, ..., 2 ⁿ -1. Therefore, if the address signal is incremented or decremented, adjacent cell arrays M / A are continuously accessed, and the access speed is reduced.

[0008]

As described above, in the DRAM of the "non-independent bank type", if the address signal is incremented or decremented to continuously access the banks, the access speed is reduced. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to suppress a decrease in access speed even if an address signal is incremented or decremented in order to continuously access a bank. An object of the present invention is to provide a semiconductor integrated circuit device having a "non-independent bank type" memory.

[0010]

In order to achieve the above object, according to the present invention, a plurality of memory cells arranged in a matrix, a bit line connected to the memory cells in the same column, and the memory in the same row are provided. K = including the word line connected to the cell
2 and ⁿ memory cell arrays, one of the K = 2 ⁿ memory cell array, the first, is provided in a region sandwiched between the second memory cell array, at least the first, shared by the second memory cell array each other A circuit area in which a sense amplifier is formed and an n-bit address signal are supplied, and based on the logic of the n-bit address signal,
A selection circuit for selecting a memory cell array to be accessed from the K = 2 ⁿ memory cell arrays. Then, when the selection circuit sequentially increments or decrements the n-bit address signal,
The memory cell array is divided into physical addresses ± M (M is 3
It is characterized in that access to the 2 ⁿ -3 following odd) intervals over.

In the semiconductor integrated circuit device having the above-described structure, when the n-bit address signal is sequentially incremented or decremented, the memory cell array is set at every physical address ± M (M is an odd number of 3 or more and 2 ⁿ -3 or less). To access. Therefore, even if the address signal is sequentially incremented or decremented, adjacent memory cell arrays are not continuously accessed. By preventing adjacent memory cell arrays from being continuously accessed in this manner, it is possible to suppress a decrease in access speed.

The n-bit address signal may be supplied from, for example, a memory controller provided separately from the memory according to the present invention. Thus, n
Even when the bit address signal is supplied from, for example, a memory controller provided separately from the memory according to the present invention, the n-bit address signal may be sequentially incremented or decremented.

That is, in the present invention, the output specification of, for example, an address signal of the memory controller is changed so that the memory cell array is accessed at every physical address ± M (M is an odd number of 3 or more and 2 ⁿ -3 or less). Also, it is not necessary to incorporate a new device such as an address converter into the system board apart from the memory and the memory controller. As a result, it is possible to obtain an advantage that it is not necessary to impose an economic burden on a user or the like.

Further, K = 2 ⁿ memory cell arrays are
Physical address ± M (M is an odd number from 3 to 2 ⁿ -3)
The configuration for accessing every other row is such that, when K = 2 ⁿ memory cell arrays are arranged in one row, the memory cell array arranged at one end of this column is a top array, and the memory cell array arranged at the other end is a bottom array, When the first access is started from the top array, the K-th access is to a memory cell array other than the bottom array.

[0015] This configuration means that the top array and the bottom array are not accessed consecutively with each other.
Therefore, even if the sense amplifier is shared by the bottom array and the top array, a decrease in access speed can be suppressed.

Therefore, if K = 2 ⁿ memory cell arrays are repeatedly arranged while sharing the sense amplifier between the bottom array and the top array, the memory capacity is theoretically infinite without impairing the advantages of the present invention. Can be increased. This means that a very large memory capacity (1 giga, 4 giga,
Giga, 16 giga,...), For example, in an ultra-large-scale memory in which circuit design is a concern, an advantage that the load of circuit design can be reduced can be obtained.

[0017]

Embodiments of the present invention will be described below.

[First Embodiment] FIG. 1 is a block diagram showing a configuration example of a DRAM chip according to a first embodiment of the present invention. This first embodiment shows a DRAM having an 8-bank configuration.

As shown in FIG. 1, a DRAM chip 1 is formed with eight memory cell arrays M / A arranged in a line. In this specification, a column of a memory cell array is referred to as a memory unit 2 for convenience. The eight cell arrays M / A are numbered sequentially from one end to the other end of the unit 2 from 0 to 7 (M / A0 to M / A
7). In this specification, numbers 0 to 7 assigned to the cell array M / A are called physical addresses.

There are eight row decoders R / D, one for each cell array M / A (R / D0 to R / D0).
7) Provided. The row decoder M / A decodes an address signal for selecting a row, and
/ A low (word line) is selected.

A circuit area S / A0 is provided at one end of the unit 2.
And a circuit area area S / A7 is provided at the other end. The cell arrays M / A0 and M / A1
, Between M / A1 and M / A2, ..., M / A6 and M
/ A7, the circuit areas S / A01, S
/ A12,..., S / A67. Area S
/ A0, S / A7, S / A01, S / A12, ..., S /
A67 is provided with a column circuit connected to the bit line. The column circuit includes a bit line sense amplifier, a bit line equalizing circuit, and the like. In particular, the sense amplifiers arranged in the areas S / A01, S / A12,..., S / A67 are shared sense amplifiers commonly used between adjacent cell arrays M / A.

The column decoder C / D is commonly used in eight cell arrays M / A0 to M / A7. The column decoder C / D decodes an address signal for selecting a column, and selects a column (bit line) of the cell array M / A.

The eight frames BANK0 to BANK shown in FIG.
Reference numerals 7 each indicate a bank. Area S / A0
1, S / A12,..., S / A67 straddle two banks, respectively, and the sense amplifiers arranged in these areas are shared sense amplifiers commonly used in the two banks. Therefore, the first embodiment is
This is a "non-independent bank type" DRAM.

FIG. 2A is a block diagram showing an example of the configuration of the cell array M / A0, and FIG. 2B is a block diagram showing the cell array M / A1.
FIG. 3 is a block diagram showing an example of the configuration of FIG.

As shown in FIG. 2A, the cell array M /
In A0, memory cells MC are formed in a matrix.
The memory cell MC is a dynamic memory cell that stores data based on the amount of charge stored in a capacitor. FIG. 2C is an equivalent circuit diagram thereof. Word line W
L (WL0, WL1,...) Are connected to the gates of the plurality of memory cells MC, respectively. The plurality of memory cells MC connected to the word line WL constitute a row of the cell array M / A. Bit lines BL (BL0L to BL3R,
..), Inverted bit lines bBL (bBL0L to bBL3R,
…). The bit lines BL and bBL are connected to the drains of the plurality of memory cells MC, respectively. The plurality of memory cells MC connected to the bit lines BL and bBL form a column of the cell array M / A.

The bit lines BL and bBL are connected to left bit lines BLL and bBLL and right bit lines BLR and bBL.
R. The left bit lines BLL and bBLL are
The right bit lines BLR and bBLR are drawn out to the right side (RIGHT) of the cell array M / A. The cell array M / A0 in the first embodiment includes bit lines BL0L, bBL
0L, BL2L, bBL2L are left bit lines, respectively, and bit lines BL1R, bBL1R, BL3R, b
BL3R is a right bit line.

As shown in FIG. 2B, the cell array M / A1 has substantially the same configuration as the cell array M / A0. The difference is that in the cell array M / A1, the bit lines BL0R, bBL0R, BL2R, and bBL2R are right bit lines, respectively, and the bit lines BL1L, bBL
1L, BL3L and bBL3L are left bit lines, respectively.

The cell arrays M / A2, M / A4, M
/ A6 has the same configuration as the cell array M / A0, and the cell arrays M / A3, M / A5, and M / A7 have the same configuration as the cell array M / A1.

FIG. 3A is a block diagram showing a configuration example of the area S / A01.

The shared bit line BLRL shown in FIG.
(BLRL1, BLRL3, ...), bBLRL (bBL
RL1, bBLRL3,...) Are shared by the cell array M / A0 and the cell array M / A1.

The transfer circuit PHITR receives the signal PH
In response to IT0, shared bit lines BLRL, bBLRL
To the right bit line BLR (BLR) of the cell array M / A0.
1, BLR3, ...), bBLR (bBLR1, bBLR)
3, ...).

In response to signal PHIT1, transfer circuit PHITL responds to signal PHIT1 by sharing bit lines BLRL, bB.
LRL is connected to the left bit line BLL of the cell array M / A1.
(BLL1, BLL3, ...), bBLR (bBLL1,
bBLL3,...).

The equalizer circuit EQLR outputs the signal EQL0.
In response to the right bit line BL of the cell array M / A0.
R and bBLR are charged or discharged to the precharge potential VPR, and the potential difference between the right bit lines BLR and bBLR is equalized. FIG. 3B shows an equalizing circuit E.
1 shows a circuit example of QL.

The equalizing circuit EQLL outputs the signal EQL1
In response to the left bit line BL of the cell array M / A1.
R and bBLR are charged or discharged to the precharge potential VPR, and the potential difference between the right bit lines BLR and bBLR is equalized. The equalizing circuit EQLL is a circuit similar to the equalizing circuit EQRL shown in FIG.

The column gate circuit CG outputs the signal CSL (C
SL1, CSL2,...), The shared bit line BL
RL and bBLRL are connected to data lines LDQ and bLDQ.

The sense amplifier S / ARL amplifies and latches the potential difference between the shared bit lines BLRL and bBLRL. The sense amplifier S / ARL is used commonly by the cell arrays M / A0 and M / A1, and belongs to two banks. The sense amplifier S / ARL shown in FIG.
Belong to banks BANK0 and BANK3.
FIG. 3C illustrates a circuit example of the sense amplifier.

The areas S / A12, S / A23, S
/ A34, S / A45, S / A56, S / A67 are S
/ A01.

Which of the banks BANK0 to BANK7 is accessed is determined by the bank selection circuit BS shown in FIG.

Bank selection circuit BS receives 3-bit address signals A2, A1, A0 for selecting a bank. The bank selection circuit BS supplies the address signals A2, A1, A
Based on the logic of 0, eight banks BANK0-BANK
From 7, select one bank to access.

When some or all of the banks BANK0 to BANK7 are successively accessed, the address signals A2, A1, A0 are incremented. As a result of the address signals A2, A1, A0 being incremented,
The banks BANK0 to BANK7 are continuously accessed one by one.

According to the present invention, the address signals A2, A1, A
When 0 is incremented, cell arrays adjacent to each other are prevented from being continuously selected.

FIG. 4 is a diagram showing a relationship between a cell array and an access order according to the first embodiment.

As shown in FIG. 4, in the first embodiment,
The logic of the 3-bit address signals A2, A1, A0 is "00".
When "0", the cell array M / A0 is accessed and "0"
01 ", the cell array M / A3 is accessed,
, "111", the cell array M / A5 is accessed.

That is, the address signals A2, A1, A0 are set to 0
00 → 001 → 010 → 011 → 100 → 101 → 11
When the bank selection circuit BS increments from 0 → 111 → 000 →..., The bank selection circuit BS changes the cell array M / A0 → M / A3 →
M / A6 → M / A1 → M / A4 → M / A7 → M / A2 →
Access is performed in the order of M / A5 → M / A0 →.

In this specification, the relationship shown in FIG. 4 is expressed as accessing the cell array M / A every physical address "+3" when a 3-bit address signal is sequentially incremented.

In the first embodiment, the cell array has eight cells.
Individual. Here, it is defined that when "+1" is added to the physical address "7", the physical address becomes "0". According to this definition, if the physical address "5" is "+3", the physical address is "0". Similarly, when the physical address “6” is “+3”, the physical address is “1”, and when the physical address “7” is “+3”, the physical address is “2”.

In addition, eight banks BANK0-BANK
The numbers “0 to 7” assigned to 7 are assigned in the order of access. In this specification, it is called a bank number. Since the bank numbers are assigned in the order of access, the logic “000, 001, 01” of the address signals A2, A1, A0
0,011,100,101,110,111 "is 10
Corresponds to those expressed in hexadecimal.

When the relationship shown in FIG. 4 is expressed by using a bank number instead of a physical address, it can be expressed that there is a "± 3" relationship between bank numbers of adjacent banks.

According to the DRAM of the first embodiment, when the address signals A2, A1, and A0 are sequentially incremented, the cell array M / A stores the physical address "+".
Access is performed every 3 ″. With this configuration, even if the address signals A2, A1, and A0 are sequentially incremented, the adjacent cell arrays M / A are not continuously accessed. Fit cell array M /
A is not accessed consecutively, so that an access occurs when switching from one bank to another,
A decrease in access speed can be suppressed.

The address signals A2, A1, A0 are D
It is supplied from, for example, a memory controller provided separately from the RAM chip 1. Thus, the address signal A
Even when 2, A1 and A0 are supplied from the memory controller, the n-bit address signal may be sequentially incremented or decremented.

That is, in the DRAM according to the first embodiment, the output specification of the address signal of the memory controller is changed or the DRAM is changed so that the cell array M / A is accessed every physical address "+3".
Apart from the chip 1 and the memory controller, it is not necessary to incorporate a new device such as an address converter into the system board. As a result, it is possible to obtain an advantage that it is not necessary to impose an economic burden on a user or the like.

In the first embodiment, an example is shown in which the address signals A2, A1, A0 are incremented. However, the address signals A2, A1, A0 may be decremented. This is the same in other embodiments described below. In the first embodiment, when the address signals A2, A1, A0 are decremented, the cell array M / A is accessed every physical address "-3".

[Second Embodiment] In the first embodiment,
Eight cell arrays divided into eight banks are accessed at every physical address "+3".

However, according to the present invention, the physical address "+
It is not limited to accessing every 3 ",
The same effect as in the first embodiment can be obtained by accessing every physical address “+5”.

The second embodiment is an example in which, when eight cell arrays divided into eight banks are successively accessed, access is made every physical address "+5".

[0056]

FIG. 5 is a diagram showing a relationship between a cell array and an access order according to the second embodiment.

As shown in FIG. 5, in the second embodiment,
When the logic of the address signals A2, A1, A0 is "000", the cell array M / A0 is accessed. When the logic is "001", the cell array M / A5 is accessed.
When 1 ", the cell array M / A3 is accessed.

That is, if the address signals A2, A1, A0 are 0
00 → 001 → 010 → 011 → 100 → 101 → 11
When 0 → 111 → 000 → ... is incremented,
The bank selection circuit BS has a cell array M / A0 → M / A5.
→ M / A2 → M / A7 → M / A4 → M / A1 → M / A6
Access is performed in the order of → M / A3 → M / A0 →.

If the relationship shown in FIG. 5 is expressed using bank numbers instead of physical addresses, it can be expressed that there is a "± 5" relationship between bank numbers of adjacent banks.

Also in the second embodiment, when the address signals A2, A1, A0 are incremented, the cell arrays adjacent to each other are not continuously selected.
Therefore, it is possible to suppress a decrease in access speed that occurs when access is switched from one bank to another bank.

[Third Embodiment] In the first and second embodiments, an 8-bank DRAM has been described.

However, according to the present invention, except for the 8-bank configuration,
For example, the present invention can be applied to a 16-bank DRAM.

The third embodiment is an example in which, when 16 cell arrays divided into 16 banks are successively accessed, access is made every physical address “+3”.

FIG. 6 is a diagram showing a relationship between a cell array and an access order according to the third embodiment.

As shown in FIG. 6, in the third embodiment,
The logic of the address signals A3, A2, A1, A0 is "000".
When "0", the cell array M / A0 is accessed and "0"
001 ", the cell array M / A3 is accessed,
.., “1111”, the cell array M / A 13 is accessed.

That is, the address signals A3, A2, A1, A
0 is 0000 → 0001 → 0010 → 0011 → 01
00 → 0101 → 0110 → 0111 → 1000 → 10
01 → 1010 → 1011 → 1100 → 1101 → 11
When the number is incremented from 10 → 1111 → 0000 →..., The bank selection circuit BS sets the cell array M / A0 → M
/ A3 → M / A6 → M / A9 → M / A12 → M / A15
→ M / A2 → M / A5 → M / A8 → M / A11 → M / A
14 → M / A1 → M / A4 → M / A7 → M / A10 → M
/ A13 → M / A0 →...

If the relationship shown in FIG. 6 is expressed using bank numbers instead of physical addresses, it can be expressed that there is a "± 11" relationship between bank numbers of adjacent banks.

Also in the third embodiment, when the address signals A3, A2, A1, A0 are incremented, the cell arrays adjacent to each other are not continuously selected. Therefore, it is possible to suppress a decrease in access speed that occurs when access is switched from one bank to another bank.

[Fourth Embodiment] In the third embodiment,
When successively accessing 16 cell arrays divided into 16 banks, access was made at every physical address "+3".

However, as described in the second embodiment, access may be made at every physical address "+5".

The fourth embodiment is an example in which, when continuously accessing 16 cell arrays divided into 16 banks, access is made at every physical address "+5".

FIG. 7 is a diagram showing a relationship between a cell array and an access order according to the fourth embodiment.

As shown in FIG. 7, in the fourth embodiment,
The logic of the address signals A3, A2, A1, A0 is "000".
When "0", the cell array M / A0 is accessed and "0"
001 ", the cell array M / A5 is accessed,
, "1111", the cell array M / A11 is accessed.

That is, the address signals A3, A2, A1, A
0 is 0000 → 0001 → 0010 → 0011 → 01
00 → 0101 → 0110 → 0111 → 1000 → 10
01 → 1010 → 1011 → 1100 → 1101 → 11
When the number is incremented from 10 → 1111 → 0000 →..., The bank selection circuit BS sets the cell array M / A0 → M
/ A5 → M / A10 → M / A15 → M / A4 → M / A9
→ M / A14 → M / A3 → M / A8 → M / A13 → M /
A2 → M / A7 → M / A12 → M / A1 → M / A6 → M
/ A11 → M / A0 →...

If the relationship shown in FIG. 7 is expressed using bank numbers instead of physical addresses, it can be expressed that there is a "± 13" relationship between bank numbers of adjacent banks.

In the fourth embodiment, when the address signals A3, A2, A1, and A0 are incremented, the cell arrays adjacent to each other are not continuously selected. Therefore, it is possible to suppress a decrease in access speed that occurs when access is switched from one bank to another bank.

In the case of a 16-bank configuration, in addition to the physical address "+3" or "+5", the "1", "+7", "+9", "+11" and "+13" are also used. The same effects as in the second, third, and third embodiments can be obtained.

Although not particularly shown, the physical address “+7”
In other cases, there is a relationship of “± 7” between the bank numbers of adjacent banks. Similarly, in the case of every physical address “+9”, the relationship of “± 9” between the bank numbers of the adjacent banks and the physical address “+11”
In every other bank, there is a relationship of “± 3” between the bank numbers of adjacent banks, and in the case of every physical address “+13”, there is a “± 3” between the bank numbers of adjacent banks.
5 "relationship.

As described above, the first to fourth embodiments are changed to 8 (= 2
³ ) While a DRAM having a 16 (= 2 ⁴ ) bank configuration has been described as an example, the present invention is also applicable to a 32 (= 2 ⁵ ) bank configuration, a 64 (= 2 ⁶ ) bank configuration, and so on. Of course, it can be applied.

The DRAM according to the present invention is expressed as follows.

When K = 2 ⁿ cell arrays M / A are successively accessed, the physical address ± M (M is 3 or more and 2
⁽ an odd number equal to or less than ^n- 3).

Alternatively, when K = 2 ⁿ cell arrays M / A are composed of K = 2 ⁿ banks, ± M (M is 3 or more and 2 ⁿ
-3 or less).

A DRAM that satisfies such a relationship can provide the same effects as those described in the first to fourth embodiments.

[Fifth Embodiment] Prior to the fifth embodiment, the cell array M / A0 arranged at one end of the unit 2 shown in FIG. 1 is replaced with a top array (TOP), and the cell array M / A0 arranged at the other end. A7 is called a bottom array (BTM).

The K described in the first to fourth embodiments,
= 2 ⁿ cell arrays M / A are assigned physical addresses ± M (M
In the configuration in which access is made every 3 or more and 2 ⁿ -3 or less, when K = 2 ⁿ cell arrays M / A are arranged in a line, the first access is performed in the top array (M / A).
Starting from 0), the K-th access is to a cell array other than the bottom array (M / AK-1).

More specifically, referring to FIG. 4, if the first access is a cell array M / A0 (top array), the eighth access is a cell array M / A5, and the cell array M / A7 ( (Bottom array). This relationship is maintained in the second, third, and fourth embodiments shown in FIGS. 5, 6, and 7.

In the configuration in which the K-th access is performed for a cell array other than the bottom array (M / AK-1), when the address signal is incremented or decremented, the top array (M / A0) and the bottom array (M / AK-1) are used. M
/ AK-1) are not continuously accessed. That is, even if the bottom array (M / AK-1) and the top array (M / A0) share a sense amplifier, the access speed does not decrease.

In the fifth embodiment, the above-mentioned items are used.
This is an example in which the number of cell arrays M / A is increased, or an example in which data is read / written from / to a plurality of cell arrays M / A in one access.

FIG. 8 is a block diagram showing a configuration example of a DRAM chip according to a fifth embodiment of the present invention. In FIG. 8, portions common to FIG. 1 are denoted by common reference numerals.

As shown in FIG. 8, a circuit area S / A 78 is provided between the cell array M / A 7 and the cell array M / A 8.
Is provided. In the area S / A 78, a sense amplifier shared by the cell arrays M / A7 and M / A8 is arranged.

The cell array M / A7 has a cell array M / A
0 to M / A7 unit 2 bottom array (BT
M), and the cell array M / A8 is the cell array M / A
8 is a top array (TOP) of a unit 2 ′ including 8 to M / A 15.

The column decoder C / D is commonly used by the 16 cell arrays M / A0 to M / A15.

As described above, by repeatedly arranging K = 2 ⁿ cell arrays while sharing the sense amplifier between the bottom array (BTM) and the top array (TOP), the advantages of the present invention are not impaired. In theory, the memory capacity can be increased indefinitely. This is useful for an ultra-large memory capacity (1 giga, 4 giga, 16 giga,...). For example, in a very large-scale memory for which circuit design is difficult, an advantage that the load of circuit design can be reduced can be obtained.

Further, the sense amplifier is connected to the bottom array (B
TM) and the top array (TOP), there is also an advantage that an increase in chip area can be suppressed.

If the first access is the top array (TOP), the relationship that the K-th access does not become the bottom array (BTM) is as shown in FIG. 5, FIG. 6 and FIG. The same holds for the third and fourth embodiments.
Therefore, the DRAMs according to the second, third, and fourth embodiments can be modified as in the fifth embodiment.

[Sixth Embodiment] The sixth embodiment relates to a circuit example of the bank selection circuit BS used in the first embodiment or the fifth embodiment.

FIG. 10 is a circuit diagram showing a bank selection circuit BS according to the sixth embodiment.

As shown in FIG. 10, bank selection circuit BS
Has eight AND circuits 10 (10-0 to 10-7). Each AND circuit 10 is of a three-input one-output type, and has three input wires 12 (12-0 to 12-7) and one
The output wirings 14 (14-0 to 14-7) are connected. The output wirings 14 are each a row decoder R / D
(R / D0 to R / D7).

Each of the input lines 12 intersects with six address signal lines 16. Address signals A2, bA2, A1, bA1, A0, bA0 are supplied to the address signal line 16. The input wiring 12 is connected to three of the six address signal lines 16 via a contact formed at the intersection 18. Output signal BL of AND circuit 10
Only one of the OCKs (BLOCK0 to BLOCK7) is at the “H” level according to the logic of the address signals A2, A1, and A0. The row decoder R / D is “H”
It is activated when it receives a level output signal BLOCK. As described above, one of the eight row decoders R / D is activated in accordance with the logic of the address signals A2, A1, and A0, so that one of the eight cell arrays M / A is accessed. You.

In such a bank selection circuit BS,
In the sixth embodiment, when the address signals A2, A1, A0 are 0
00 → 001 → 010 → 011 → 100 → 101 → 11
When the output signal BLOCK is incremented as 0 → 111 → 000 →..., The output signal BLOCK0 becomes BLOCK0 → BLOCK.
3 → BLOCK6 → BLOCK1 → BLOCK4 → BL
OCK7 → BLOCK2 → BLOCK5 → BLOCK0
The address signal line 16 is brought into contact with the input wiring 12 so as to become “H” level in the order of →.
FIG. 11 shows address signals A2 and A according to the sixth embodiment.
1, A0, output signals BLOCK0 to BLOCK7, and activated row decoders R / D0 to R / D7.

As described above, by changing the position of the contact between the address signal line 16 and the input wiring 12 of the bank selection circuit BS, the bank selection for realizing the operation described in the first or fifth embodiment is achieved. A circuit BS can be obtained.

In order to realize the operation described in the second embodiment, the position of the contact between the address signal line 16 and the input wiring 12 may be changed.

Further, in order to realize the operations described in the third and fourth embodiments, the number of the address signal lines 16 and the positions of the contacts between the address signal lines 16 and the input lines 12 can be changed. Good.

[Seventh Embodiment] The seventh embodiment relates to another circuit example of the bank selection circuit BS.

FIG. 12 is a circuit diagram showing a bank selection circuit BS according to the seventh embodiment.

As shown in FIG. 12, row decoder R / D
(R / D0 to R / 7) each have one input wiring 2
0 (20-0 to 20-7) is connected. The input wirings 20 are output wirings 14 (14-0 to 14-7), respectively.
Intersect with The output signal BLOCK0 is output to the output line 14.
To BLOCK7 are supplied. The input wiring 20 is connected to one of the eight output wirings 14 via a contact formed at the intersection 22.

In the seventh embodiment, the address signals A2, A
1, A0 is 000 → 001 → 010 → 011 → 100 →
When the output signal BLOCK is incremented as 101 → 110 → 111 → 000 →..., The output signal BLOCK0 becomes BLOCK0 →
BLOCK1 → BLOCK2 → BLOCK3 → BLOCK
K4 → BLOCK5 → BLOCK6 → BLOCK7 → B
LOCK0 →... Become “H” level in this order.

Further, the output signal BLOCK becomes BLOCK.
0 → BLOCK1 → BLOCK2 → BLOCK3 → BL
OCK4 → BLOCK5 → BLOCK6 → BLOCK7
When going to “H” level in the order of → BLOCK0 →..., The row decoder R / D outputs R / D0 → R / D3 → R /
D6 → R / D1 → R / D4 → R / D7 → R / D2 → R /
The output wiring 14 is brought into contact with the input wiring 20 so as to be accessed in the order of D5 → R / D0 →. FIG. 13 shows an address signal A according to the seventh embodiment.
2, A1, A0, output signals BLOCK0 to BLOCK7
And the relationship with activated row decoders R / D0 to R / D7.

The output wiring 14 to which the output signal BLOCK is supplied and the input wiring 2 to the row decoder R / D
By changing the position of the contact with 0, the bank selection circuit BS that realizes the operation described in the first embodiment or the fifth embodiment can be obtained.

In order to realize the operations described in the second to fourth embodiments, the positions of the contacts between the output wiring 14 and the input wiring 20 may be changed.

[Eighth Embodiment] The eighth embodiment relates to another example of the bit line related circuits arranged in the circuit areas S / A01,..., S / A67.
This is an example applied to a high-speed DRAM called M (Low Latency DRAM).

In the LLDRAM, the command execution time from the input of an operation command to the execution of the operation differs depending on the access location of the bank. For more information,
The command execution time is different for continuous access to the same bank, continuous access to an adjacent bank, and continuous access to one or more distant banks (hereinafter referred to as independent banks). Since the command execution times are different as described above, the access time is such that continuous access to the independent bank has the highest speed, continuous access to the next adjacent bank, and finally continuous access to the same bank take time. Will be.

In such an LLDRAM, if the address signal is simply incremented or decremented, an access is made to an adjacent bank, and an effectively highest access speed cannot be achieved. However, if the present invention is applied to such an LLDRAM,
Effectively the highest access speed can be achieved. The details will be described below.

FIG. 14 shows an LLDR according to the eighth embodiment.
It is a block diagram showing AM. FIG. 14 shows an example of a configuration of a bit line circuit arranged particularly in the circuit area S / A01.

As shown in FIG. 14, the feature of the circuit of the LLDRAM is that the shared bit line BLRL (BLRL1, BLRL
RL3, ...), bBLRL (bBLRL1, bBLRL
3,...) Is connected to the equalizing circuit EQLRL. The equalizing circuit EQLRL outputs the signal EQ
In response to L2, the common bit lines BLRL and bBLRL are charged or discharged to the precharge potential VPR, and the potential difference between the shared bit lines BLRL and bBLRL is equalized. Thereby, the left bit lines BLL, bB
LL, right bit lines BLR, bBLR and shared bit lines BLRL, bBLRL can be independently precharged / equalized. Equalizing circuit E
QLL is the equalizer circuit EQRL shown in FIG.
Is a circuit similar to.

Next, the operation will be described.

FIG. 15 shows an LLDR according to the eighth embodiment.
FIG. 4 is a block diagram for explaining the operation of AM. Also,
16, 17, and 18 are operation waveform diagrams showing the operation, respectively.

[Consecutive Access to Independent Bank] FIG.
Means that after the cell array M / A0 (BANK0) is accessed for the first time, the cell array M / A2 (BANK0) is
6) shows the operation when the access is made.

As shown in FIG. 16, at time t1ACT., BANK0 is selected by the first access request, and signal EQL0 changes from "H" to "L". Next, the selected word line WL0 rises, and the right bit lines BL1R and bBL1R in the cell array M / A0 are
Data stored in the memory cell MC is read as a minute potential difference.

Next, the signal PHIT0 changes from “L” to “H” and the signal EQL2 changes from “H” to “L”, and the right bit lines BL1R and bBL1R are changed to the shared bit line BL1RL in the area S / A01. , BBL1R
Connect to L. As a result, the data is
L1RL and bBL1RL. Next, using the sense amplifier S / ARL in the area S / A01, the data transmitted to the shared bit lines BL1RL and bBL1RL is amplified / latched.

Next, at time t2ACT., BANK6 is selected by the second access request, and signal EQL is output.
4 changes from “H” to “L”. Next, the selected word line WL2 rises, and the memory cells MC are connected to the left bit lines BL2L and bBL2L in the cell array M / A2.
Is read as a minute potential difference.

Next, the signal PHIT3 changes from “L” to “H” and the signal EQL5 changes from “H” to “L”, and the left bit lines BL2L and bBL2L are changed to the shared bit line BL2RL in the area S / A12. , BBL2R
Connect to L. As a result, the data is
Transferred to L2RL and bBL2RL. Next, the data transmitted to the shared bit lines BL2RL and bBL2RL is amplified / latched using the sense amplifier S / ARL in the area S / A12.

Next, the signal PHIT0 changes from “H” to “L” and the signal EQL2 changes from “L” to “H”, and the shared bit lines BL1RL and bBL1RL are changed to
It is separated from the right bit lines BL1R and bBL1R. As a result, the shared bit lines BL1RL and bBL1RL are precharged / equalized independently of the right bit lines BL1R and bBL1R.

Next, the signal PHIT3 changes from “H” to “L” and the signal EQL5 changes from “L” to “H”, and the shared bit lines BL2RL and bBL2RL are changed to
It is separated from the left bit lines BL2L and bBL2L. As a result, the shared bit lines BL2RL and bBL2RL are precharged / equalized independently of the left bit lines BL2L and bBL2L.

[Consecutive Access to Adjacent Banks] FIG. 17 shows that the cell array M / A0 (BANK0) is accessed for the first time and then the cell array M / A1 (BA
NK3) is accessed.

As shown in FIG. 17, at time t1ACT., BANK0 is selected by the first access request, and signal EQL0 changes from "H" to "L". Next, the selected word line WL0 rises, and the right bit lines BL1R and bBL1R in the cell array M / A0 are
Data stored in the memory cell MC is read as a minute potential difference.

Next, the signal PHIT0 changes from “L” to “H” and the signal EQL2 changes from “H” to “L”, and the right bit lines BL1R and bBL1R are changed to the shared bit line BL1RL in the area S / A01. , BBL1R
Connect to L. As a result, the data is
L1RL and bBL1RL. Next, using the sense amplifier S / ARL in the area S / A01, the data transmitted to the shared bit lines BL1RL and bBL1RL is amplified / latched.

Next, at time t2ACT., BANK3 is selected by the second access request, and signal EQL is selected.
1 changes from “H” to “L”. Next, the selected word line WL1 rises, and the memory cells MC are connected to the left bit lines BL1L and bBL1L in the cell array M / A1.
Is read as a minute potential difference.

Next, the signal PHIT0 is changed from “H” to “L” and the signal EQL2 is changed from “L” to “H”, and the shared bit lines BL1RL and bBL1RL are changed to
It is separated from the right bit lines BL1R and bBL1R. As a result, the shared bit lines BL1RL and bBL1RL are precharged / equalized independently of the right bit lines BL1R and bBL1R.

Next, the signal PHIT1 changes from “L” to “H” and the signal EQL2 changes from “H” to “L”, and the left bit lines BL1L and bBL1L are changed to the shared bit line BL1RL in the area S / A01. , BBL1R
Connect to L. As a result, the data is
L1RL and bBL1RL. Next, using the sense amplifier S / ARL in the area S / A01, the data transmitted to the shared bit lines BL1RL and bBL1RL is amplified / latched.

Next, the signal PHIT1 transitions from “H” to “L” and the signal EQL2 transitions from “L” to “H”, and the shared bit lines BL1RL and bBL1RL are
It is separated from the left bit lines BL1L and bBL1L. Thus, the shared bit lines BL1RL and bBL1RL are precharged / equalized independently of the left bit lines BL1L and bBL1L.

[Consecutive Access to the Same Bank] FIG.
Shows an operation when the cell array M / A0 (BANK0) is continuously accessed.

As shown in FIG. 18, at time t1ACT., BANK0 is selected by the first access request, and signal EQL0 changes from "H" to "L". Next, the selected word line WL0 rises, and the right bit lines BL1R and bBL1R in the cell array M / A0 are
Data stored in the memory cell MC is read as a minute potential difference.

Next, the signal PHIT0 changes from “L” to “H” and the signal EQL2 changes from “H” to “L”, and the right bit lines BL1R and bBL1R are changed to the shared bit line BL1RL in the area S / A01. , BBL1R
Connect to L. As a result, the data is
L1RL and bBL1RL. Next, using the sense amplifier S / ARL in the area S / A01, the data transmitted to the shared bit lines BL1RL and bBL1RL is amplified / latched.

Next, the signal PHIT0 changes from “H” to “L” and the signal EQL2 changes from “L” to “H”, and the shared bit lines BL1RL and bBL1RL are changed to
It is separated from the right bit lines BL1R and bBL1R. As a result, the shared bit lines BL1RL and bBL1RL are precharged / equalized independently of the right bit lines BL1R and bBL1R.

Next, at time t2ACT., BANK0 is selected by the second access request, and signal EQL is selected.
0 changes from “H” to “L”. Thereafter, the same operation as in the first access is performed.

Comparing the above three operations, the command execution time becomes shorter in the order of continuous access to the same bank, continuous access to the adjacent bank, and continuous access to the independent bank.

By applying the present invention to such an LLDRAM, when the address signal for selecting a bank is simply incremented or decremented, the independent banks are continuously accessed, so that it is effective. The highest access speed can be achieved.

It should be noted that D described in the first to seventh embodiments is not limited to D.
The advantage of the LLDRAM over the RAM is that when accessing an adjacent bank shown in FIG.
1R and bBL1R are active, and these right bit lines B
L1R and bBL1R are shared bit lines BL1RL and bBL
Separate from 1RL. And an equalizer circuit EQLR
L and the shared bit lines BL1RL, bBL1RL
Can be equalized / precharged independently of the right bit lines BL1R and bBL1R. Thereby, as shown in "OVERLAP" in FIG. 17, while the right bit lines BL1R, bBL1R are active, the data on the left bit lines BL1L, bBL1L are transferred to the shared bit lines BL1RL, bBL1RL, and Can be amplified / latched.

Therefore, according to the eighth embodiment, the first to first embodiments
An effect similar to that of the seventh embodiment can be obtained, and an address signal for selecting a bank is input, for example, at random, as compared with the first to seventh embodiments.
Even when adjacent banks are continuously accessed, a reduction in access speed can be suppressed.

[0142]

According to the present invention, a semiconductor integrated circuit having a "non-independent bank type" memory capable of suppressing a decrease in access speed even if an address signal is incremented or decremented in order to continuously access a bank. A circuit device can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a DRA according to a first embodiment of the present invention;
FIG. 3 is a block diagram illustrating a configuration example of an M chip.

2A is a block diagram illustrating a configuration example of a cell array M / A0, FIG. 2B is a block diagram illustrating a configuration example of a cell array M / A1, and FIG. 2C is a memory cell FIG.

FIG. 3A is a block diagram illustrating a configuration example of a circuit area S / A01, and FIG. 3B is a diagram illustrating an equalizing circuit EQL;
FIG. 3C is a circuit diagram illustrating one circuit example of a sense amplifier.

FIG. 4 is a diagram showing a relationship between a cell array and an access order according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a relationship between a cell array and an access order according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between a cell array and an access order according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a relationship between a cell array and an access order according to a fourth embodiment of the present invention.

FIG. 8 is a diagram illustrating a DRA according to a fifth embodiment of the present invention;
FIG. 3 is a block diagram illustrating a configuration example of an M chip.

FIG. 9 is a diagram showing a relationship between a cell array and an access order according to a fifth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a bank selection circuit BS according to a sixth embodiment of the present invention.

FIG. 11 is a diagram showing a relationship between an address signal, an output signal, and an activated row decoder according to a sixth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a bank selection circuit BS according to a seventh embodiment of the present invention.

FIG. 13 is a diagram showing a relationship between an address signal, an output signal, and an activated row decoder according to a seventh embodiment of the present invention;

FIG. 14 is a diagram showing an L according to an eighth embodiment of the present invention;
FIG. 2 is a block diagram showing a bit line circuit of the LDRAM.

FIG. 15 is an LLDRAM according to an eighth embodiment;
FIG. 3 is a block diagram for explaining the operation of FIG.

FIG. 16 is an LLDRAM according to an eighth embodiment;
FIG. 4 is an operation waveform diagram showing the operation of FIG.

FIG. 17 is an LLDRAM according to an eighth embodiment;
FIG. 4 is an operation waveform diagram showing the operation of FIG.

FIG. 18 is an LLDRAM according to an eighth embodiment;
FIG. 4 is an operation waveform diagram showing the operation of FIG.

FIG. 19A shows a DRA of a completely independent bank system.
FIG. 19B is a block diagram illustrating a non-independent bank type DRAM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... DRAM chip, 2 ... unit, 10 ... AND circuit, 12 ... Input wiring to AND circuit, 14 ... Output wiring from AND circuit, 16 ... Address signal line, 18 ... Input wiring to address signal line and AND circuit 20: Input wiring to the row decoder, 22: Intersection of the output wiring from the AND circuit and the input wiring to the row decoder.

Claims (6)

[Claims] A plurality of memory cells arranged in a matrix;
K = 2 ⁿ including bit lines connected to the memory cells in the same column and word lines connected to the memory cells in the same row
Memory cell arrays, and the first and second memory cells of the K = 2 ⁿ memory cell arrays.
And a circuit area including a sense amplifier shared by at least the first and second memory cell arrays, an n-bit address signal is supplied, and a logic of the n-bit address signal is provided. A selection circuit for selecting a memory cell array to be accessed from the K = 2 ⁿ memory cell arrays. The selection circuit, when the n-bit address signal is sequentially incremented or decremented, sets the memory cell array to a physical address. Address ± M
(M is an odd number not less than 3 and not more than 2 ⁿ -3). 2. The memory system according to claim 2, wherein said K = 2 ⁿ memory cell arrays are K
= 2 ⁿ banks, ± M between adjacent bank numbers (M is 3 or more and 2 ⁿ −
2. An odd number of 3 or less.
3. The semiconductor integrated circuit device according to 1. 3. The K = 2 ⁿ memory cell arrays are arranged in a line, and a memory cell array arranged at one end of the column is a top array, and a memory cell array arranged at the other end is a bottom array. 3. The semiconductor integrated circuit device according to claim 1, wherein when the access is started from the top array, the K-th access is to a memory cell array other than the bottom array. 4. The semiconductor integrated circuit according to claim 3, wherein said K = 2 ⁿ memory cell arrays are repeatedly arranged while sharing said sense amplifier with said bottom array and said top array. apparatus. 5. A first equalizer circuit connected to a bit line of the first memory cell array; a second equalizer circuit connected to a bit line of the second memory cell array; 5. The device according to claim 1, further comprising: the sense amplifier and a third equalizing circuit connected to a shared bit line shared between the two memory cell arrays. 6. Semiconductor integrated circuit device. 6. The apparatus according to claim 1, further comprising a column decoder for selecting the bit line, wherein the column decoder has the K = 2 ⁿ
The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is common to a plurality of memory cell arrays.