JP2000250949A - Simulation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the increase of manhour due to the second execution of simulation and also to suppress the storage capacity that is required for a computer. SOLUTION: This device includes a simulation execution means 1, a FIFO means 2 which stores successively the simulation states and a storage control means 3 which stores the simulation states every time the simulation time is updated. If an abnormal simulation result is detected and the simulation is discontinued, the simulation result can be analyzed according to the information stored in the means 2 without executing again the simulation. Plural abnormal states are sometimes detected by the simulation of a single time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a functional logic simulation apparatus used for design verification of a large-scale system LSI integrating a plurality of functional modules. In particular, the present invention relates to a simulation device that efficiently analyzes a failure of a large-scale system LSI.

[0002]

2. Description of the Related Art With the miniaturization of LSIs and the development of integration technologies, it has become possible to integrate large-scale circuits at the system level in one-chip LSI. On the other hand, it is necessary to design from the processing method in the system LSI design to the function, logic, and layout in a short period of time, and to commercialize the product early. Therefore, with the increase in the design scale, there is a strong demand for a technology capable of improving design productivity and increasing design efficiency. In particular, in design verification, an increase in the design scale and the complexity of the verification case require a long verification man-hour.

In the conventional functional logic design verification, a circuit description using a hardware description language and its test vector description are mainly performed, and the circuit operation is simulated on a computer. In the verification of the circuit operation, a signal on a specific circuit is observed during the execution of the simulation, and it is confirmed that there is no error in the design by comparing the signal with an expected value to be taken in the design specification. Alternatively, a condition of an operation state which can be taken in specifications during the execution of the simulation is set, and it is confirmed that the operation is performed within the range of the condition.

[0004] At this time, if a design defect that appears as a mismatch with an expected value or a violation of operating conditions occurs, the defective element and the state immediately before the input side of the signal line are searched sequentially from the defective element and the signal. Then, the cause of the failure is specified, and necessary circuit correction is performed. In this debugging work,
The simulation is re-executed at least once in order to reproduce the operation state causing the failure. Further, the debugging work is repeated until no trouble occurs through all the simulations.

In the conventional simulation apparatus or simulation method, in order to perform a failure analysis and a debugging operation, the operation state of the circuit during the simulation is monitored, and when a state determined to be a failure such as an expected value violation occurs. The system is provided with means for temporarily stopping the simulation, analyzing the operation state, and performing step execution per unit time. Large-scale LSI requiring a long processing time
The one-chip simulation includes means for periodically saving the simulation state during the execution of the simulation, restoring the saved simulation state after completion of all simulations, and re-executing and debugging the simulation from a specific time. .

[0006]

However, in the conventional simulation apparatus or simulation method, when a failure is detected, the simulation can be temporarily stopped and the debugging operation can be started. Has a problem that a large amount of processing time and man-hours are required to re-execute the simulation because it is necessary to search for a past state. Large L
Simulation of SI requires simulation time ranging from several tens of hours to several days. In particular, if a problem occurs after such a long simulation run, a period for re-executing the simulation for debugging and analysis has been developed. The impact on the schedule was fatal and a major problem.

On the other hand, by using means for periodically saving the simulation state, if a failure occurs, the state saved immediately before can be restored, and the circuit operation and its state change can be tracked. There is a possibility that man-hours can be relatively reduced by debugging. But,
Because we ca n’t predict when a failure will occur,
It is necessary to repeatedly save the simulation state immediately after the start of the simulation, and a large-scale LSI simulation requires a large storage capacity on a computer. In particular, in the simulation of a large-scale LSI, even in the simulation state at one time, a large storage area is required to save the state, and it is difficult to secure a storage area that enables efficient debugging and analysis. There was a problem that there is.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a simulation apparatus capable of preventing an increase in man-hours due to re-execution of a simulation and suppressing a storage capacity required on a computer.

[0009]

According to a first aspect of the present invention, there is provided a simulation apparatus for use in verifying a functional logic design of an LSI, which simulates a circuit operation based on LSI design information and input signal information. Simulation execution means for saving and restoring the simulation state at any point in time, FIFO means for sequentially storing the simulation state and deleting a certain amount of memory in a first-in first-out manner, and simulation every time the simulation time is updated during simulation execution Storage control means for storing the state in the FIFO means.

According to the first aspect of the present invention, during the execution of the simulation, the simulation result can be stored in the storage area of a fixed capacity used by the FIFO means. As a result, even if the simulation is interrupted at any point, such as at the point where a failure occurs, the simulation can be analyzed retrospectively for a certain simulation period without re-executing the simulation, thus improving the efficiency of design verification work. Can be. Even if multiple break points are set, the FIFO
By storing the means information at each of the breakpoints, the circuit operation can be analyzed for each. As a result, large-scale system LSI function simulation,
Function verification can be performed efficiently.

According to a second aspect of the present invention, there is provided a simulation apparatus comprising:
2. The method according to claim 1, wherein the FIFO means compares the change in the simulation state and generates difference state information by extracting only the changed signal state; a difference information storage means for storing the difference state information; And a simulation state synthesis means for generating a series of simulation states from the difference state information at each time stored in the difference information storage means. After being converted into state information, the state information is stored in a difference information storage means, a certain state or more of the difference state information is deleted by a first-in first-out method using a deletion means, and a series of simulation states is generated by a simulation state synthesis means.

According to the simulation apparatus of the second aspect, in addition to the same effects as those of the first aspect, the information to be stored in the FIFO means is sampled to be converted into differential information, compressed, and decimated to reduce the FIFO required for the simulation. The storage area used by the means can be reduced and the simulation state can be reproduced.

According to a third aspect of the present invention, there is provided a simulation apparatus comprising:
In claim 1, the storage control means controls the storage of the simulation state in the FIFO means on a designated schedule.

According to the simulation apparatus of the third aspect, in addition to the same effects as those of the first aspect, the simulation state is not stored at every simulation unit time but the simulation state is stored at a period required for analysis. The storage area required by the FIFO means can be reduced.

According to a fourth aspect of the present invention, there is provided a simulation apparatus comprising:
In claim 1, the storage control means controls whether or not the simulation state is stored in the FIFO means in synchronization with a state change of the specific signal of the circuit to be simulated.

According to the simulation apparatus of the fourth aspect, in addition to the same effects as those of the first aspect, the storage control means can synchronize the simulation state with a synchronous circuit or the like in synchronization with the state change of the specific signal of the circuit to be simulated. FIFO
The storage area can be reduced by controlling the presence or absence of storage in the means.

According to a fifth aspect of the present invention, there is provided a simulation apparatus comprising:
In the first aspect, there is provided means for storing only the state value of the storage element of the circuit to be simulated, and only the state of the storage element is stored in the FIFO means.

According to the simulation apparatus of the fifth aspect, in addition to the same effects as those of the first aspect, the storage area used by the FIFO unit can be reduced by storing only the state of the storage element in the FIFO unit.

According to a sixth aspect of the present invention, there is provided a simulation apparatus comprising:
2. The apparatus according to claim 1, further comprising a stop control unit that monitors an operation state of the simulated circuit during the execution of the simulation, stops the simulation execution based on the stop condition, and saves a series of simulation states stored in the FIFO unit. .

According to the simulation device of the sixth aspect, in addition to the same effects as those of the first aspect, the stop conditions include:
When the occurrence of a defect such as an expected value violation is set, the simulation is interrupted at the same time that the defect is detected, and the necessary analysis can be immediately performed based on the information stored in the FIFO means.

According to a seventh aspect of the present invention, there is provided a simulation apparatus comprising:
2. A storage control unit according to claim 1, further comprising: a storage control unit that monitors an operation state of the circuit to be simulated during a simulation, and sequentially stores a series of simulation states stored in the FIFO unit in the FIFO storage unit when a predetermined condition is satisfied. is there.

According to the simulation apparatus of the seventh aspect, in addition to the same effects as those of the first aspect, when the occurrence of a failure such as an expected value violation is set as a predetermined condition and the simulation is executed, the failure occurs. Then, the information stored in the FIFO means is separately saved, and the simulation is continued. . When the simulation is completed, individual information for performing an analysis for each of a plurality of different failures can be obtained from the FIFO storage unit. Thus, for verification of a design including several different defects, the defects can be analyzed by executing a single simulation, and the design verification can be made more efficient.

[0023] The simulation device according to claim 8 is
2. The simulation method according to claim 1, wherein during the execution of the simulation, the operation state of the circuit to be simulated is monitored, and when a predetermined condition is satisfied, the simulation is executed for a predetermined time, and then a series of simulation states stored in the FIFO means are sequentially added to the FIFO storage means. It is provided with storage control means for storing.

According to the simulation apparatus of the eighth aspect, in addition to the same effects as those of the first aspect, it is possible to observe the circuit operation before and after the simulation at which the failure occurred as information for analyzing a plurality of failures. It is possible to analyze and determine the status of the fault, including the effect of the fault on the circuit operation.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a configuration diagram of a simulation device according to a first embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes an input of LSI circuit information 5 and a test vector 6 described in a hardware description language,
Simulation execution means for performing SI simulation. The simulation executing means 1 starts a simulation at a simulation time 0, simulates an operation state per unit time, and ends the simulation at a predetermined time. Simulation execution means 1
Has a function of outputting the simulation state 8 at the time during the execution of the simulation.

FIG. 2 shows a configuration of a simulation state stored by the simulation executing means 1 in the first embodiment. The information shown in FIG. 2 includes time information 81 for storing a simulation time at which the simulation state is stored, a signal state 82 including identifiers indicating input / output or internal signals of the simulated circuit and signal values thereof.
Consists of In the first embodiment, the simulation executing means 1 is realized by an event-driven logic simulator.

FIG. 1 shows a simulation execution means 1.
That sequentially store the simulation state 8 output by the
FO means. The FIFO unit 2 stores the simulation states 8 in a first-in first-out manner, deletes the simulation states stored in the storage order, and keeps the storage size of the simulation states constant.

FIG. 1 shows a simulation execution means 1.
Is a storage control means for controlling the updating of the simulation time and the output of the simulation state 8 and the storage of the output in the FIFO means 2. Reference numeral 4 in FIG. 1 denotes stop control means for inputting stop condition information 7, observing the state of the circuit to be simulated based on the stop condition information 7, and controlling the execution stop of the simulation. The stop control unit 4 controls output of the analysis information 9 from the FIFO unit 2. The analysis information 9 is F
This is a series of simulation states stored by the IFO means 2. The stop condition information 7 is information representing a logical expression having the simulation time, the input / output of the circuit to be simulated, and the identifiers of the internal signals and their signal values as arguments.

Next, the flow of the simulation execution and the simulation method in the first embodiment of FIG. 1 will be described with reference to FIG. In the first step of FIG. 3, the simulation executing means 1 reads LSI circuit information and a test vector as a setup for a simulation, and sets up internal data. At this time, the simulation start time is set, and the event of the input signal is also registered. Next, after the second step, the operation of the circuit at each time is calculated while updating the simulation time, and the simulation proceeds. In the second step, the simulation time is updated first, and it is determined in the third step whether the simulation end time is met. If the simulation end time is not reached, the process proceeds to the fourth step, and the circuit state at the simulation time is changed. calculate. In the fourth step, an event scheduled at the simulation time is extracted based on the event driving method, the simulation state is updated, and a newly generated event is registered. Next, in a fifth step, the storage control unit 3 outputs a simulation state, and the FIFO unit 2 performs control 301 for storing the simulation state. At this time, the FIFO unit 2 stores the simulation state output from the simulation execution unit 1 and deletes the oldest information. Next, in a sixth step, the stop control means 4 reads the stop information, evaluates a logical expression indicating the stop condition, and determines whether to stop. If the stop condition is not satisfied, the process returns to the second step and the simulation is continued. When the stop condition is satisfied and when the simulation end time is determined in the third step, the process proceeds to a seventh step, and the control 401 of the stop control means 4 controls a series of simulation states stored in the FIFO means 2. All are output as the analysis information 9, and the simulation ends.

Next, a simulation of the first embodiment will be described using a specific example. In a specific example, a simulation in which the number of simulation states stored in the FIFO unit 2 is 6 in a simulation of 15 unit time will be described. At this time, a logical expression indicating that the output expected values do not match is given as a stop condition, and stop control is performed.

FIG. 4 is a diagram showing the structure of the circuit to be simulated. The circuit in FIG. 4 includes three stages of flip-flops 51, 52, 55, 56 and OR gates 53, 54. 501, 502, 503, 504 in FIG.
Is an input signal, and 501 is a clock signal. 50
5, 506, 507, 508, 509 are internal signals, 50
10 is an output signal. The input signals 501, 50 of FIG.
The signal values of 2, 503 and 504 are provided as test vectors.

FIG. 5 is a timing chart showing changes in signal values when a 15-unit time simulation is executed in the circuit of FIG. FIG. 5 shows the change of each element and signal and the expected output value at each simulation time. FIG.
In the simulation shown in (1), a clock signal having a period of 2 unit time is input to 501. At the unit time 8, the signal value of the input signal 502 changes from H to L. The signal value of the input signal 503 changes from H to L at the unit time 2, and changes to H again at the unit time 4. Input signal 504
Is fixed to H. On the other hand, the change of the input signal 502 is latched by the flip-flop 51 at the next rising edge of the clock signal 501 and the unit time 3, and the L signal is input to the OR gate 53 from 505, but the OR signal from the 504 side is input. Since the gate input signal 506 is H, the output signal 507
Is always H. Also, at unit time 8, the input signal 502 changes and the signal value L is input to the OR gate 54. Since the input signal 507 of the OR gate is also H, the output signal 508 is fixed at H. . Here, in the simulation example of FIG. 5, the flip-flops 51, 52, 5
The initial values of 5, 56 are H.

On the other hand, the expected value shown in FIG. 5 indicates a change in the output signal 5010 of the circuit in which the OR gates 53 and 54 in FIG. 4 are both AND gates. In the expected value, the change of the input signal 503 at the unit times 2 and 4 propagates, and the signal value changes at the unit times 7 and 9. Also, the change of the input signal 502 at the unit time 8 causes the output signal 5 to change at the unit time 11.
010 changes to L.

Next, the stop condition is given in the form of "value (5010, T)! = E" as a logical expression indicating an expected value mismatch of the output signal 5010 at each time of the simulation. Here, value (5010, T) indicates a signal value of the output signal 5010 at the unit time T, and E indicates an expected value. "! =" Is the inequality logical operator.

With respect to the above simulation execution example,
In the operation example of the first embodiment, the simulation is sequentially performed from the unit time 0, and the state value of each signal of the circuit is calculated as shown in FIG. The simulation time is updated until the unit time 7 at which the stop condition is satisfied. At unit time 7,
Since “value (5010,7) is H,“ value (5010,7)
10, 7)! = L "is established, the simulation is stopped, and the stored contents of the FIFO means 2 are output as analysis information. FIG. 6 shows a simulation state at unit times 1, 2, and 7 stored in the FIFO unit 2 for each unit time by the storage control unit 3 during the unit time 1 to the unit time 7.
Reference numerals 201, 202, and 207 denote storage contents of the FIFO means 2 at simulation times 1, 2, and 7, respectively. 80
1, 802, 803, 804, 805, 806, 807
Are simulation states at unit times 1, 2, 3, 4, 5, 6, and 7, respectively. The simulation state of the unit time 1 is stored in the content 201 of the FIFO unit 2 at the unit time 1, and the simulation state of the unit time 2 is added in the order 202. In the content 207 of the FIFO means 2 at the unit time 7, the number of storable simulation states exceeds 6, so the simulation state at the unit time 1 is deleted, and the simulation state at the unit time 7 is stored from the unit times 2 to 7. The six simulation states at each time are stored. Since the stop condition is satisfied at the unit time 7, the contents 207 of the FIFO unit 2 are output as analysis information.

In the first embodiment, the FIFO means 2 always stores the simulation result from the simulation time to a predetermined period before the simulation in the functional logic simulation apparatus.
When a failure is detected in the simulation result and the simulation is stopped, the analysis of the simulation result can be performed without executing the simulation again by using the information stored in the FIFO unit 2.

As described above, according to the present invention, when the simulation is executed, a defect is detected as an expected value error, and when the simulation is stopped, the analysis information 207 can be obtained. By analyzing this, the input side of the output signal 5010 is
509, 55 of unit time 5 one clock before, and 508, 54, 502, 50 of unit time 3 one clock before.
7, 53, 505 and 506 are traced back to the simulation time, and 53 is an OR gate instead of an AND gate.
A gate design error can be detected. In the simulation at this time, by using the FIFO means 2, the storage area required for storing the analysis information can be reduced to the size required for the simulation state for six unit times.

In the first embodiment, the simulation control information and the event information are saved as the simulation state, so that even after the simulation is stopped once, the latest simulation state in the analysis information 9 is restored again. And the simulation can be restarted.

(Second Embodiment) A second embodiment of the present invention will be described with reference to FIGS. FIF of FIG.
A description will be given of a simulation apparatus including a FIFO unit having the configuration shown in FIG. Reference numeral 21 in FIG. 7 denotes state difference means for comparing changes in the simulation state 8 and generating difference state information by extracting only the changed signal state. Reference numeral 22 denotes difference information storage means for storing difference state information. Reference numeral 23 denotes a deletion unit that deletes the difference state information at a specific time, and reference numeral 24 denotes a simulation state synthesis unit that generates a series of simulation states 8 from the difference state information at each time stored in the difference information storage unit 22.

FIG. 8 shows the structure of the difference state information generated by the state difference means 21 and stored in the difference state information storage means 22. The difference state information 2003 shown in FIG.
It is composed of a time 2001 for storing a simulation time at which the simulation state is stored, and a signal state 2002 including signal values indicating respective identifiers indicating input / output or internal signals of the circuit under simulation.

The latest simulation time T (2
001) stores the signal values of all the signals, and the differential state information at time T−1 one time earlier indicates the time T
The state information of only the signal having a different signal value is stored for the corresponding signal. Thereafter, the state information at each time is stored only when the signal after the time has a value different from the signal value stored for the signal. Therefore, at the latest time, the signal states of all the signals are stored.

Next, a procedure for storing and deleting a simulation state in the FIFO means of the second embodiment is shown in FIG.
This will be described with reference to FIG. First, in a fifty-first step, a simulation state at the simulation time is input.
Next, in a 52nd step, it is determined whether or not the number of pieces of differential state information stored in the difference state information storage means 22 is a limited number. To delete. The deletion unit 23 searches the difference state information at the oldest time stored in the difference information storage unit 24, and deletes all signal states classified into the difference state information. Next, in a fifty-fourth step, the difference state information storage means 2
4 is empty (that is, there is no information already),
If it is empty, the process proceeds to step 56, where the simulation state input in step 51 is stored in the difference state information storage means 22 as difference state information. If the difference state information storage means 22 is not empty, the process proceeds to a 55th step, and the state difference means 21 is used to generate difference state information.

This procedure will be described with reference to FIG. First, in step 551, the state difference means 21 searches for difference state information at the latest time T stored in the difference state information storage means 22, and in step 552, simulation is performed for each signal state divided into time T. The signal value of the same signal at the current time T + 1 input as the state is searched. If the signal value of the same signal at time T + 1 matches the signal value at time T in step 553, the process proceeds to step 554, where the signal state at time T is deleted, and the process proceeds to step 555. If there is no match in the 553th step, the process directly proceeds to the 555th step to search for uncompared signal state information. If there is an uncompared signal state, the processing from the 552th step is repeated, and all signals at time T are repeated. When the states are compared, the process ends. Next, returning to the procedure of FIG. 9, the process proceeds to step 56, where the simulation state input in step 51 is stored as difference state information in the difference state information storage means 22, and the processing is terminated.

Next, a procedure for generating a series of simulation states from the difference state information stored in the difference information storage means 22 in the simulation state synthesis means 24 is shown in FIG.
This will be described with reference to FIG. First, in step 57, a list of signal state information included in the simulation state is created. The list of signal status information is created from the latest time difference status information stored in the FIFO means. Next, the process proceeds to a step 58, where the simulation state information at the time is generated from the difference state information in the order of time. The detailed procedure of the fifty-eighth step will be described with reference to FIG. First, in step 581, a list of signal state information is searched for corresponding signal state information from the differential state information. At step 582, the presence or absence of the corresponding signal state information is determined. If there is the corresponding signal state information, the process proceeds to step 584. If there is no corresponding signal state information, the difference state information one time later is obtained. The search is repeated, and the time is advanced until the corresponding signal state information is obtained. In the 584th step, the corresponding signal state information is output as the signal state information of the simulation information at the time.

Next, proceeding to step 585, the procedure from step 581 is repeated until all the signal state information in the signal state information list is obtained. Next, returning to FIG.
The process proceeds from the 8th step to the 59th step, where it is determined whether or not there is difference state information.

Next, a description will be given of a simulation of the second embodiment, in particular, a specific example of storing a difference state by the FIFO means. In a specific example, it is assumed that the number of simulation states stored in the FIFO means is 4 in a simulation of 15 unit times. Using the circuit of FIG. 4 as the circuit to be simulated, the operation shown in the timing chart of FIG. 5 is simulated. FIG. 13 shows each difference information storage means 2 at unit times 1, 2, and 3 in the simulation of FIG.
FIG. 4 is a diagram showing the contents stored in No. 4; 221 in FIG.
Indicates the content stored in the difference information storage means 24 at unit time 1, and 2211 indicates difference state information at unit time 1. The difference state information 2211 is stored in the difference information storage unit 2 at the unit time 0.
Since 4 is empty, the input simulation state is stored as it is. Reference numeral 222 in FIG. 13 indicates the storage contents of the difference information storage unit 24 at unit time 2,
Reference numeral 2 denotes difference state information at unit times 1 and 2, respectively. When storing the simulation state at the unit time 2, the difference state information 2221 is a difference state generated by comparing the corresponding signal state with the difference state information 2211 stored at the unit time 1 in the difference information storage unit 22. Information. The difference state information 2221 is the difference state information 221 of the unit time 1.
Signal states having signal values different from the simulation state from 1 to the unit time 2 are left. The simulation state at the unit time 2 is stored as it is as the difference state information 2222 in the difference information storage unit 24. Similarly, at the unit time 3, the difference state information 2222 of the unit time 2 is replaced with the difference state information 2232, and the difference state information 2223
1 and 2233. Thereafter, the FIFO means similarly stores the difference state information for four unit times.

Next, at unit time 7, the simulation is stopped by the stop control means 4, and the difference information storage means 22
The simulation state combining unit 24 combines the simulation states at the unit times 7, 6, 5, and 4 from the difference state information stored in the simulation state information, and outputs the result as the analysis information 9.
FIG. 14 shows the input and output of this processing. The simulation state synthesizing unit 24 first creates a signal list 220, and synthesizes the simulation state at each unit time for the signals 501 to 5010 in the list. In the synthesis of the simulation state at the unit time 4, the difference information storage unit 24
The signal state corresponding to each signal of the signal list 220 is searched from the difference state information 2274 of the content 227 stored in the. As for the signal 501, the signal state information of the signal value L of the difference state information 2274 is obtained. For signal 502,
Since it is not stored in the difference state information 2274, the difference state information 2275 at the unit time 5 is searched by going back one unit time. Also here, since the signal state information of the signal 502 cannot be obtained, the difference state information 2276 at the unit time 6 is searched further one unit time. Similarly, since the signal state information of the signal 502 cannot be obtained, the difference state information 2277 at the unit time 7 is searched to obtain the signal state information of the signal value H. Hereinafter, the same processing is performed for each signal.
The simulation state 804 at the unit time 4 is output.
Similarly, with respect to the unit times 5, 6, and 7, the simulation states 805, 806, and 8 corresponding to the difference state information 2275, 2276, and 2277 of the difference information storage unit 24 in this order.
07 are synthesized.

As described above, when the second embodiment is used, the state difference means 21, the difference information storage means 22, and the deletion means 2
3, when the simulation state is stored in the fixed time range by the FIFO unit including the simulation state synthesis unit 24, only the difference information indicating only the change point can be stored, and the storage area required for this can be reduced.
Thus, efficient analysis and debugging can be performed for a large-scale circuit simulation.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIGS. FIG. 15 shows a configuration in which a storage timing definition unit 10 and a storage element selection unit 11 are added to the configuration of FIG.

The save timing defining means 10 is a means for defining control conditions for outputting the simulation state to the FIFO means 2 using the save control means 3, and outputs the simulation state at the simulation time as a specified schedule. Describe the timing to perform. The storage timing definition is described based on the signal value and the event of the simulated circuit. The storage control means 3 determines the presence or absence of storage according to the simulation execution result, and controls the output of the simulation state. The storage element selection means 11 calculates the simulation state information 8
Information that selects only the state of the storage element, that is, storage element state information 12, is transferred to the FIFO unit 2. The configuration of the storage element state information 12 has the same configuration as that of the simulation state information 8 on which it is based.

FIG. 1 shows the procedure of the above simulation method.
6 will be described. In the first step of FIG. 16, the simulation executing means 1 reads LSI circuit information and test vectors as a simulation setup, and sets up internal data. At this time, the simulation start time is set, and the event of the input signal is also registered. Further, the storage timing of the simulation state defined by the storage timing definition means 10 is also input.

Next, after the second step, the operation of the circuit at each time is calculated while updating the simulation time.
Proceed with the simulation. In the second step, the simulation time is updated first, and it is determined in the third step whether the simulation end time is met. If the simulation end time is not reached, the process proceeds to the fourth step, and the circuit state at the simulation time is changed. calculate. In the fourth step, an event scheduled at the simulation time is extracted based on the event driving method, the simulation state is updated, and a newly generated event is registered.

Next, in the fifth step, the storage control means 3
It is determined whether or not it is the save timing, and if it is the save timing, the simulation state is output in the sixth step. In the simulation state output from the simulation execution means 1, only the information of the storage element is selected through the storage element selection means 11, and the storage element state is selected.
It is stored in the FIFO means 2.

Next, in a seventh step, the stop control means 4 reads the stop information, evaluates a logical expression indicating the stop condition, and determines whether to stop. If the stop condition is not satisfied, the process returns to the second step and the simulation is continued.

When the stop condition is satisfied, and when it is determined in the third step that the simulation end time is reached,
Then, the control 401 of the stop control means 4 outputs all the series of simulation states stored in the FIFO means 2 as the analysis information 9 and ends the simulation.

Next, a specific operation example of the simulation apparatus according to the third embodiment will be described. This operation example executes the same simulation as the operation example of the first embodiment,
Using the circuit of FIG. 4 as the circuit to be simulated, FIG.
The operation for 15 unit time shown in the timing chart of FIG. On this occasion,
The storage timing defining means 10 defines the storage timing according to the description shown in FIG. In the description of FIG.
01 is the clock signal 5 of the simulated circuit of FIG.
01, and the variable save is an event variable that specifies saving of the simulation state. In the description of FIG. 17, when 501 changes to 1 at the changing point of the clock signal 501, save is set to 1 and the output of the simulation state is defined.

When the saving of the simulation state is executed at the above timing, the simulation state is output at times 1, 3, 5, and 7 of the rising edge of the clock signal 501 in the timing chart of FIG. In this operation example, the operation is performed until the unit time 7 when the simulation stops at the unit time 7. FIG. 18 shows simulation states 8001, 8003, and 800 at unit times 1, 3, 5, and 7.
5,8007. 1201, 1203, and 1 in FIG.
205 and 1207 each represent a simulation state 800
The storage element state information selected by the storage element selection unit 11 from 1, 8003, 8005, and 8007 is shown. In each storage element state, the flip-flops 51, 5 in FIG.
Only states 2, 55 and 56 are selected. The FIFO unit 2 stores the storage element states for three unit times, and
In 1, the storage element state information 1201 is stored, and the unit time 3
Stores the storage element status information 1201 and 1203, and at the unit time 5, the storage element status information 1201, 1203 and 1
When the simulation is stopped at the unit time 7, the storage element state information 1203, 1205, and 1 are stored.
207 is stored. The analysis information includes the FIF of unit time 7
The contents of the O means 2 are output.

When the simulation is stopped at the unit time 7, the output 501 is obtained by analyzing the analysis information 9.
The reason why 0 does not match the expected value can be analyzed retroactively in the clock cycle. It is found that the value of the flip-flop 55 is H at the unit time 5 even though the flip-flop 51 is L at the unit time 3, and the logic element 53 having the inputs 51 and 52 is not an AND gate specified in the specification. Can be analyzed.

As described above, in the third embodiment, when the simulation is stopped, the design failure can be analyzed by the analysis information 9, the simulation state stored in the FIFO means 2 is thinned out at the clock cycle, and the simulation state other than the storage element is used. The required storage area can be greatly reduced by thinning out the signal states of the above. Alternatively, even if the number of simulation states stored in the FIFO storage unit 2 is the same, information in a wide time zone can be stored.

An embodiment in which the storage element selection means 11 is used as selection control means and a designated signal is selected to adjust the storage area of the FIFO storage means 2 or the number of simulation state storages according to the purpose of simulation analysis. Is possible.

(Fourth Embodiment) A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 20 shows a configuration diagram of a simulation apparatus according to a fourth embodiment of the present invention. In the configuration of FIG. 20, a FIFO storage unit 13 is added to the configuration of FIG. 1, and a FIFO storage control unit 14 is provided instead of the stop control unit 4 of FIG.

The FIFO storage means 13 receives the storage signal 1401 from the FIFO storage control means 14, and
Is a storage unit for sequentially and additionally storing the analysis information 9 output by. The FIFO storage control unit 14 receives the FIFO storage control information 15, observes the state of the circuit to be simulated based on the input, and controls the output of the analysis information 9 of the FIFO unit 2. The FIFO storage control information 15 outputs simulation information based on the simulation time, the simulation state condition for outputting the analysis information 9 using the identifiers of the input / output of the circuit to be simulated and the internal signal and their signal values as arguments, and the time when the condition is satisfied. This is information that defines a delay time of a unit time unit until it is performed. FIFO storage control means 14
Has an internal counter for performing control at a specified timing, and enables control to output a save signal 1401 with a delay from the time of a simulation state in which a predetermined state is detected.

Next, the flow of simulation execution and the simulation method in the fourth embodiment of FIG. 20 will be described with reference to FIG.

In the first step of FIG. 21, the simulation executing means 1 reads the LSI circuit information 5 and the test vector 6 as a simulation setup, and sets up internal data. On this occasion,
The simulation start time is set and the event of the input signal is registered. Next, after the second step, the operation of the circuit at each time is calculated while updating the simulation time, and the simulation proceeds.

In the second step, the simulation time is updated first, and in the third step, it is determined whether the simulation end time is reached. If the simulation end time is not reached, the process proceeds to the fourth step. The circuit state at the simulation time is calculated. In the fourth step, an event scheduled at the simulation time is extracted based on the event driving method, the simulation state is updated, and a newly generated event is registered.

Next, in the fifth step, the storage control means 3
The simulation state is output by F
The control 301 for storing the simulation state is performed on the IFO means 2. At this time, the FIFO unit 2 stores the simulation state output from the simulation execution unit 1 and deletes the oldest information.

Next, in a sixth step, the FIFO storage control unit 14 reads the FIFO storage control information, and determines the time at which the analysis information 9 is output and stored in the FIFO storage unit 13. If the time corresponds to the time when the analysis information 9 is stored in the sixth step, the output of the analysis information 9 and the storage in the FIFO storage unit 13 are executed in the seventh step, and the process returns to the second step. If it does not correspond to the sixth step, the process returns to the second step and the simulation is continued.

The FIFO storage control means 14 has an internal counter and repeats the procedure of FIG. 22 at each simulation time. First, in step 61, the presence or absence of a unit time count using an internal counter is determined by a count flag, and if not counting, in step 62, the storage condition is determined from the simulation state at the time. Here, if the storage condition is satisfied, a designated delay time is set in the counter in a 63rd step, and a count flag is set. On the other hand, if counting is being performed in the 61st step, the process proceeds to the 64th step, and the count value is decremented.

Next, in step 65, the count value is determined. If the count value, that is, the delay time is 0, the save signal 1401 is output in step 66, the count flag is reset, and the process ends. If the count value is not 0 in the 65th step, the process ends.

In the above-described procedure of the FIFO storage control means 14, if the storage conditions are satisfied at successive simulation times, the count flag is set at the previous time, so that the storage conditions are satisfied at the subsequent time. Is also ignored. In this case, by providing a plurality of counters, it is possible to adopt a configuration in which a plurality of storage control timings are determined in parallel.

Next, a simulation of the fourth embodiment will be described using a specific example. In a specific example, a simulation for 15 units of time shown in the timing chart of FIG. 5 will be described for the circuit shown in FIG. In the simulation of FIG. 5, the logic gates 53 and 54 in the circuit of FIG.
In this example, the D gate is erroneously replaced with the OR gate, and the expected value does not match twice.

Here, the number of simulation states stored in the FIFO means 2 is six. It is assumed that a logical expression “value (5010, T)! = E” representing the mismatch of the expected value of the output signal 5010 in FIG. 4 at each time of the simulation is given to the FIFO storage control information as the storage condition.

Here, value (5010, T) indicates the signal value of the output signal 5010 at the unit time T, and E indicates the expected value. "! =" Is the inequality logical operator. Further, it is assumed that two unit times are input as the delay time.

In the above simulation, the timing at which the storage condition is satisfied and the storage signal 140 are shown in FIG.
1 shows the output timing. First, the expected value mismatch is established at the unit time 7, and the logical expression “value (5010, T)! = E”
Becomes H, and the count value 2 is set in step 62. Two unit times after this, the count value becomes 0, and the save signal 1401 becomes H at unit time 9. Similarly, the expected value does not match at unit time 11 and the stored signal 1 at unit time 13
401 becomes H. FIG. 24 shows the analysis information stored in the FIFO storage unit 13 at the unit times 9 and 13. FIG.
FIG. 24 is a diagram illustrating signal values output as analysis information on the timing chart of FIG. 130 in FIG.
Reference numerals 9 and 1313 denote the contents of the FIFO storage unit 13 at the unit times 9 and 13, respectively, and are the analysis information 9 stored at the unit times 9 and 13, respectively. The above analysis information is stored in the FIFO storage unit 1 when the simulation ends at the unit time 15.
Obtained from 3. The analysis information 1309 indicates a simulation state from the unit time 4 to the unit time 9 obtained at the unit time 9, and the cause of the expected value mismatch at the unit time 7 is as follows.
At unit time 4, it can be analyzed that there is an error in the output of the OR gate 53. Further, at unit time 5, the input signal 505 of the OR gate 53 becomes H. As a result, it can be confirmed that the expected value mismatch of the output 5010 at unit time 9 is resolved. The analysis information 1313 indicates a simulation state from the unit time 8 to the unit time 13 obtained at the unit time 13. When the expected value mismatch that occurs at the unit time 11 changes the input signal 502 at the unit time 8, the OR gate 54
Can be analyzed that there was an error in the output.

In the fourth embodiment, when a defect is detected, the simulation is not stopped, the information of the FIFO means 2 is separately stored, the simulation is continued, and a plurality of defects are detected in one simulation. In addition, it is possible to analyze each defect based on information stored in the FIFO means 2.

As described above, according to the present invention, it is possible to analyze two design failures that have mismatched expected values by executing a single simulation. For this reason, it is possible to reduce the number of steps for repeating the simulation for each defect. Further, the operation after the expected value error time can be confirmed after the simulation is completed, and the effect of the failure can be analyzed efficiently.

[0079]

According to the simulation apparatus of the first aspect, during the execution of the simulation, the simulation result can be stored in the storage area of a fixed capacity used by the FIFO means. As a result, even if the simulation is interrupted at any point, such as at the point where a failure occurs, the simulation can be analyzed retrospectively for a certain simulation period without re-executing the simulation, thus improving the efficiency of design verification work. Can be. In addition, even if multiple interruption points are set,
By storing the information of the FO means at each of the break points,
The circuit operation can be analyzed for each. As a result, large-scale system LSI function simulation,
Function verification can be performed efficiently.

According to the simulation apparatus of the second aspect, in addition to the same effects as those of the first aspect, the information to be stored in the FIFO means is sampled and converted to differential information, compressed, and decimated. The storage area used by the means can be reduced and the simulation state can be reproduced.

According to the simulation apparatus of the third aspect, in addition to the same effect as the first aspect, the simulation state is not always stored for each simulation unit time, but the simulation state is stored at a period required for analysis. The storage area required by the FIFO means can be reduced.

According to the simulation apparatus of the fourth aspect, in addition to the same effects as those of the first aspect, the storage control means may synchronize the simulation state with a synchronous circuit or the like in synchronization with a state change of a specific signal of the circuit to be simulated. FIFO
The storage area can be reduced by controlling the presence or absence of storage in the means.

According to the simulation apparatus of the fifth aspect, in addition to the same effects as those of the first aspect, the storage area used by the FIFO means can be reduced by storing only the state of the storage element in the FIFO means.

According to the simulation apparatus of the sixth aspect, in addition to the same effects as those of the first aspect, the stop condition is
When the occurrence of a defect such as an expected value violation is set, the simulation is interrupted at the same time that the defect is detected, and the necessary analysis can be immediately performed based on the information stored in the FIFO means.

According to the simulation apparatus of the seventh aspect, in addition to the same effects as those of the first aspect, if a failure such as an expected value violation is set as a predetermined condition and the simulation is executed, the failure occurs. Then, the information stored in the FIFO means is separately saved, and the simulation is continued. . When the simulation is completed, individual information for performing an analysis for each of a plurality of different failures can be obtained from the FIFO storage unit. Thus, for verification of a design including several different defects, the defects can be analyzed by executing a single simulation, and the design verification can be made more efficient.

According to the simulation apparatus of the eighth aspect, in addition to the same effects as those of the first aspect, it is possible to observe the circuit operation before and after the time when the failure occurred as information for analyzing a plurality of failures, It is possible to analyze and determine the status of the fault, including the effect of the fault on the circuit operation.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a simulation device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of simulation state information according to the first embodiment of the present invention.

FIG. 3 is a flowchart of simulation control according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram used in a simulation example according to the first embodiment of the present invention.

FIG. 5 is a timing chart of a simulation example according to the first embodiment of the present invention.

FIG. 6 is a diagram showing information of FIFO means in a simulation example according to the first embodiment of the present invention.

FIG. 7 is a configuration diagram of FIFO means according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram of difference state information according to the second embodiment of the present invention.

FIG. 9 is a flowchart of control of storage / deletion of a simulation state according to the second embodiment of the present invention.

FIG. 10 is a flowchart of control of differential state information generation according to the second embodiment of the present invention.

FIG. 11 is a flowchart of simulation control according to the second embodiment of the present invention.

FIG. 12 is a flowchart of a detailed procedure of a fifty-eighth step in FIG. 11 of the simulation apparatus according to the second embodiment of the present invention;

FIG. 13 is an explanatory diagram showing contents of difference state information stored in a storage unit according to the second embodiment of the present invention.

FIG. 14 is an explanatory diagram illustrating an example of simulation analysis information according to the second embodiment of the present invention;

FIG. 15 is a configuration diagram of a simulation device according to a third embodiment of the present invention.

FIG. 16 is a flowchart of simulation control according to the third embodiment of the present invention.

FIG. 17 is an explanatory diagram showing an example of a storage timing description according to the third embodiment of the present invention;

FIG. 18 is a diagram illustrating a simulation example according to the third embodiment of the present invention.

FIG. 19 is an explanatory diagram showing storage element state information selected by the storage element selecting means from each of the simulation states of FIG. 8 showing a simulation example according to the third embodiment of the present invention.

FIG. 20 is a configuration diagram of a simulation device according to a fourth embodiment of the present invention.

FIG. 21 is a flowchart of simulation control according to a fourth embodiment of the present invention.

FIG. 22 is a diagram illustrating a FIFO according to a fourth embodiment of the present invention;
5 is a flowchart of control at each simulation time in a storage control unit.

23 is a timing chart showing a timing chart of a simulation example according to the first embodiment in the fourth embodiment of the present invention, and is a timing chart showing a timing at which a storage condition is satisfied and an output timing of a storage signal in FIG. 5; is there.

FIG. 24 is an explanatory diagram illustrating signal values output as analysis information on the timing chart of FIG. 23;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Simulation execution means 2 FIFO means 3 Save control means 4 Stop control means 11 Storage element selection means 13 FIFO save means 14 FIFO save control means 21 State difference means 22 Difference information storage means 23 Deletion means 24 Simulation state synthesis means

Claims (8)

[Claims] 1. A simulation device for use in verifying a functional logic design of an LSI, wherein the simulation simulates a circuit operation based on LSI design information and input signal information, and saves and restores a simulation state at an arbitrary time. Executing means, FIFO means for sequentially storing the simulation state and deleting a certain amount of storage in a first-in-first-out manner, and storage control means for storing a simulation state in the FIFO means every time a simulation time is updated during simulation execution. Simulation device equipped with. The FIFO means compares state changes of the simulation state and generates difference state information by extracting only the changed signal state; a difference information storage means storing the difference state information; And a simulation state synthesizing unit that generates a series of simulation states from the difference state information at each time stored in the difference information storage unit. The simulation state is calculated using the state difference unit. After being converted into difference state information, the difference state information is stored in the difference information storage means, a certain state or more of the difference state information is deleted by a first-in first-out method using the deletion means, and a series of simulation states is generated by the simulation state synthesis means. Claim 1
The simulation device according to the above. 3. The simulation apparatus according to claim 1, wherein the saving control means controls saving of the simulation state in the FIFO means on a designated schedule. 4. The simulation apparatus according to claim 1, wherein the storage control means controls whether or not the simulation state is stored in the FIFO means in synchronization with a state change of a specific signal of the circuit to be simulated. 5. The simulation apparatus according to claim 1, further comprising means for storing only the state value of the storage element of the circuit to be simulated, and storing only the state of the storage element in the FIFO means. 6. A simulation system according to claim 1, further comprising a stop control unit for monitoring an operation state of the simulated circuit during the simulation, stopping the simulation based on the stop condition, and storing a series of simulation states stored in the FIFO unit. The simulation device according to the above. 7. During the execution of the simulation, the operation state of the circuit to be simulated is monitored, and when a predetermined condition is satisfied, a series of simulation states stored in the FIFO means is stored in the FIFO unit.
2. The simulation apparatus according to claim 1, further comprising a storage control unit for sequentially storing the FO storage unit. 8. During the execution of the simulation, the operation state of the circuit to be simulated is monitored, and when a predetermined condition is satisfied, the simulation is executed for a predetermined time, and then a series of simulation states stored in the FIFO means are sequentially added to the FIFO storage means. The simulation device according to claim 7, further comprising a storage control unit for storing.