JP2000250785A - Device and method for monitoring system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the efficiency of fault analysis from being lowered by suppressing the write-out of effective data for analysis in a processor by deciding whether it is an infinite self-loop instruction or not from the decided result of a branch destination address. SOLUTION: A non-conditional branch deciding circuit 3 decides whether an instruction word is a branching instruction or not from the OP code of that instruction word, discriminates whether all the bits of CF bits are '1' or not and discriminates whether the branching condition is non-conditional or not. Addresses held in the AS field of the instruction word and an address register 2 are outputted to a branch destination address deciding circuit 4. These two values are compared an decided and it is decided whether the branch destination address of the branching instruction is branch to that instruction word itself or not. While inputting discriminate signals from the non-conditional blanch deciding circuit 3 and the branch destination address deciding circuit 4, an infinite self-loop deciding circuit 5 decides whether the instruction word accompanied with processing is branched without conditions or not and whether it is the infinite self-loop instruction to be branched to the instruction word itself or not.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system fault monitoring apparatus, and more particularly to a system monitoring apparatus capable of quickly and accurately collecting fault information when an infinite loop occurs due to a program failure or hardware failure.

[0002]

2. Description of the Related Art Conventionally, this type of system monitoring method is disclosed in Japanese Patent Laid-Open No. 6-236299 and Japanese Patent No. 277.
As described in Japanese Patent No. 6765, a timer is used to confirm whether or not the process is completed within a predetermined time. This is based on the premise that a normally operating process ends within a preset time, and detects that a specific process does not end within a predetermined time by timeout. When this timeout is detected, abnormality detection is performed by determining that the process has entered an infinite loop due to a processor system failure or the like.

[0003] Japanese Patent Application Laid-Open No. 9-62520 discloses that
In a system that executes a plurality of tasks according to their respective priorities, the system periodically recognizes a task that is being executed, and determines that an infinite loop has occurred when the same task is being executed a predetermined number of times. Is described.

In general, the following two types of infinite loops are detected. The first is an accidental case in which the condition for branching is not satisfied forever due to a program failure or an unexpected hardware failure.
Second, an infinite self-loop is intentionally embedded in a flow that cannot be reached when the program is operating normally, and when a problem occurs in the execution of the program, the flow is executed and a failure is generated by the monitoring method described above. Is intentional.

[0005]

However, in the above-mentioned prior art, the same operation by the infinite loop is performed endlessly until a certain time when it is determined that a system failure has occurred regardless of the type of the infinite loop. Was. For this reason, there is a problem that the analysis data group such as trace data held in the processor is overwritten. this is,
Because the data for analysis is held by finite hardware (registers, etc.), when the storage destination goes round, the held contents are overwritten in chronological order, leaving more recent information It is. For this reason, desired data cannot be obtained even if internal data is extracted during failure analysis.
There was a problem that it took time to analyze at the time of debugging.

In the conventional system monitoring method, monitoring is performed based on the execution time of a process.
Anomaly detection can be performed only after operation for a specific time, and a certain time until it is determined that a system failure has occurred,
There is also a problem that the processor is wasted unnecessarily.

An object of the present invention is to detect the occurrence of an infinite self-loop at an early stage when a system failure occurs due to an infinite loop, particularly when a system failure occurs due to an intentional infinite self-loop due to an unconditional branch to its own address. In this way, the execution of an infinite self-loop prevents the data for valid analysis in the processor from being overwritten, thereby preventing the efficiency of failure analysis from deteriorating, and further minimizing the wasteful occupation of resources by executing the infinite self-loop. It is an object of the present invention to provide a device that can provide efficient resources by preventing such a situation.

[0008]

In order to solve the above-mentioned problems, a system monitoring apparatus according to the present invention provides an unconditional branch determination for determining whether an instruction to be executed is an instruction for unconditionally branching. Means, a branch destination address determining means for determining whether a branch destination of the executed instruction word is the instruction word itself, the unconditional branch instruction determining means, and the branch destination address determining means And infinite self-loop determining means for determining whether or not the instruction to be executed is an infinite self-loop instruction from the result of the determination.

The instruction word includes an operation code, a branch determination reference bit referred to for branch determination, and an address designator indicating an address of operand data or a branch destination address for a branch instruction. Determining means for inputting the operation code and the branch determination reference bit to determine whether or not the instruction word is an instruction for unconditionally branching; the branch destination address determining means includes: The address of the instruction to be executed on the storage device is input to determine whether the instruction is a self-loop instruction that branches to its own instruction.

Further, the unconditional branch determination means detects that the operation code indicates a branch instruction and that all the branch determination reference bits indicate a branch, so that the instruction word to be executed is determined. It is determined that the instruction branches unconditionally.

Further, the branch destination address judging means includes:
The address indicated by the address instruction word is compared with the address of the executed instruction word on the storage device, and if they match, it is determined that the executed instruction word is a self-loop instruction.

When the self-loop determining means determines that the command to be executed is an unconditional self-loop command, it notifies the software management program.

When the self-loop determining means determines that the command to be executed is an unconditional self-loop command, the self-loop determining means notifies the diagnostic program to execute a fault handling process.

Further, a system monitoring method according to the present invention for solving the above-mentioned problem determines whether or not the instruction word is a branch instruction from an operation code of the instruction word,
It is determined whether or not the instruction word indicates an unconditional branch from a branch determination reference bit referred to in branch determination of the instruction word, and an address of operand data of the instruction word or a branch destination address for a branch instruction is determined. It is determined whether or not the indicated address denoting indicates the address on the storage device of the instruction word itself, the instruction word is a branch instruction, the branch is unconditionally performed, and the branch destination is the instruction. When it is determined that the word is the word itself, a notification is sent to a predetermined device.

The notification to the predetermined device is a signal for prompting the diagnostic unit to start a failure processing process.

Further, the notification to the predetermined device is a signal for inhibiting the new writing into the tracer memory storing the processing history of the instruction.

[0017]

Embodiments of the present invention will now be described with reference to the drawings.

Referring to FIG. 1, a system monitoring apparatus according to the present invention includes an instruction register 1 for receiving an instruction word of an instruction to be processed, and an address indicating the location of the instruction word held in the instruction register 1 in main memory. An address register 2 for holding a branch instruction, an unconditional branch determination circuit 3 for determining whether an instruction to be processed is a branch instruction to branch unconditionally, and an instruction word for processing a branch destination address of the branch instruction Branch destination address determination circuit 4 for determining whether or not the address is its own
And an infinite self-loop determining circuit 5 that determines whether the instruction word is an infinite self-loop instruction that is an unconditional branch and performs a self-branch.

Referring to FIG. 2, an instruction word 10 includes an operation code 11 (hereinafter referred to as an OP code), a branch determination reference bit 12 (hereinafter referred to as a CF (Condition Flag) bit), and an address instruction word 13 (hereinafter referred to as an CF code). , AS
(Address Sillable) field. ). The OP code 11 is an operation code indicating which instruction the instruction word 10 is.
The CF bit 12 is a flag composed of a plurality of bits and referred to to determine whether or not to branch at the time of a branch instruction. The AS field 13 is an instruction word indicating an address of operand data in an operation instruction or the like or a branch destination address for a branch instruction.

Normally, when the instruction word 10 is a branch instruction,
A branch is determined based on the value of the CF bit 12 of the instruction word 10 and the condition code (hereinafter, referred to as CC) set by the preceding instruction. CC is a value for making a branch determination set by a preceding instruction,
This indicates which bit of the CF bit 12 of 0 is used for branch determination.

When the CF bit 12 is composed of 4 bits, the possible values of CC are "0", "1",
There are four values “2” and “3”, which correspond to the first, second, third and fourth bits of the CF bit 12, respectively. For example, if the CC is “0”, the 0th bit of the CF bit 12 is referred to as a flag for branch determination. here,
If the 0th bit is “1”, it is determined that the branch is to be executed, and the branch is performed to the branch destination address obtained by the AS field 13. On the other hand, the 0th bit is “0”
In this case, it is determined that the branch is not to be executed, and the processing of the subsequent instruction is performed without performing the branch.

Therefore, the values of the CF bits are all "1".
In this case, the flag referred to in the branch determination is always "1" regardless of the value of CC, which means that the instruction is unconditionally branched. Conversely, if at least one “0” is included in the value of the CF bit, it means that the instruction may not branch depending on the bit to be referred to.

The OP code 11 and the CF bit 12 of the instruction word 10 held in the instruction register 1 are output to the unconditional branch determination circuit 3 to determine whether the instruction word 10 is an instruction that unconditionally branches. Is performed.

The unconditional determination circuit 3 first determines from the OP code 11 of the instruction word 10 whether the instruction word is a branch instruction. At the same time, it is determined whether or not all the bits of the CF bit 12 are “1” to determine whether or not the branch condition is unconditionally performed. Thereby, the instruction word 10
Is a branch instruction and an instruction for unconditionally branching.

The branch destination address judging circuit 4 outputs the AS field 13 of the instruction word 10 and the address held in the address register 2. Here, the AS field 13 indicates the branch destination address in the branch instruction, and the address held in the address register 2 indicates the address of the instruction word 10 held in the instruction register 1 on the main memory. The branch destination address determination circuit 4 compares these two values to determine whether the branch destination address in the branch instruction is a branch to the instruction word itself.

The infinite self-loop judgment circuit 5 receives the judgment signals from the unconditional branch judgment circuit 3 and the branch destination address judgment circuit 4 and unconditionally branches the instruction word 10 to be processed. It is determined whether the instruction is an infinite self-loop instruction that branches to a word. For example, when the unconditional branch determination circuit 3 determines that the instruction is an unconditional branch instruction, "1"
When the branch destination address determination circuit 4 determines that the branch destination address is the same as the address of its own instruction word,
If "1" is to be output, a logical AND of these signals is output to output "1", whereby it can be determined and detected that the given instruction is an infinite self-loop instruction.

Next, the operation of the embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG.
The processor (not shown) supplies the instruction word 10 to the instruction register 1 according to the processing status (S1). The instruction word 10 received in the instruction register 1 is sent to an instruction execution processing circuit (not shown), and is sequentially processed.

Here, in the present invention, when the instruction word 10 is supplied to the instruction register 1, the OP code 11 and the CF bit 12 of the instruction word 10 held in the instruction register 1 are stored.
Is output to the unconditional branch determination circuit 3, and the AS field 13 and the address in the main memory of the instruction word held in the address register 2 are output to the branch destination address determination circuit 4 (S2).

The unconditional branch determination circuit 3 first determines from the OP code 11 of the input instruction word 10 whether or not the instruction word 10 is a branch instruction. Further, the value of each bit of the CF bit 12 is read, and it is determined whether or not all bits are "1" (S3).

On the other hand, the branch destination address determination circuit 4
It is determined whether or not the address of the branch destination indicated by the field 13 matches the address on the main memory of the instruction word 10 held in the address register 2 (S4).

The infinite self-loop determination circuit 5 determines whether or not the instruction word 10 to be executed is an infinite self-loop instruction based on the determination results of the unconditional branch determination circuit 3 and the branch destination address determination circuit 4 ( S5). When it is determined that the instruction word 10 is an infinite self-loop circuit, the infinite self-loop determination circuit 5 notifies the microprocessor, the diagnosis unit, and the like (S6).

As described above, the instruction word 1 is stored in the instruction register 1.
When 0 is held, the instruction unconditionally branches according to each parameter (OP code 11, CF bit 12, and AS field 13) of the held instruction word 10, and branches to its own instruction word. It is determined whether or not the instruction is an infinite self-loop instruction.

When the infinite self-loop determining circuit 5 determines that the instruction word is an infinite self-loop instruction,
Using this result as a trigger, the diagnosis unit may be notified of the detection of a system abnormality, and the diagnosis unit may be moved to a failure processing process. Alternatively, a trigger for activating a system abnormality notification flow to the OS may be used as an interrupt signal to the microprogram. Similarly, it is also effective as a signal for inhibiting new writing to the tracer memory storing the processing history associated with the execution of each instruction.

It should be noted that the present invention is not limited to the above embodiments, and each embodiment can be appropriately modified within the scope of the technical idea of the present invention.

As described above, according to the embodiment of the present invention, as compared with the conventional intentional execution of an infinite self-loop and the detection of a system abnormality by the system monitoring means using a timer, a time-out does not occur. It is possible to detect a system abnormality at an early stage. This eliminates wasteful occupation of the processor due to the self-loop being performed for a certain period of time due to a system abnormality, thereby enabling efficient resource provision. Further, the trace information in the processor is not overwritten by the infinite self-loop, and the efficiency of debugging can be improved.

[0036]

As is apparent from the above description, according to the present invention, an infinite self-loop instruction which is an instruction which branches unconditionally in an infinite loop and whose own instruction word is a branch destination can be quickly executed. Upon detection, the system abnormality can be promptly notified to the software management program or the diagnosis unit.

As a result, resources can be efficiently used, and failure analysis data such as trace data existing inside the processor is not overwritten, so that efficient debugging can be performed.

As another effect, the system abnormality can be detected earlier than the conventional system abnormality detection by timer monitoring, so that the processor occupied by the infinite loop for a certain time can be released earlier. Can be provided efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a format of a command word.

FIG. 3 is a flowchart illustrating an operation of the exemplary embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 instruction register 2 address register 3 unconditional branch determination circuit 4 branch destination address determination circuit 5 infinite self-loop determination circuit 10 instruction word 11 OP code (operation code) 12 CF bit (branch determination reference bit) 13 AS field (address instruction word) )

Claims (9)

[Claims] 1. A monitoring apparatus for a system for sequentially processing instruction words, wherein an unconditional branch determination unit that determines whether an instruction word to be executed is an instruction to branch unconditionally, and the executed instruction Branch destination address determining means for determining whether or not the branch destination of the word is the instruction word itself to be executed; and performing the execution from the determination results of the unconditional branch instruction determining means and the branch destination address determining means. A system monitoring apparatus comprising: an infinite self-loop determining means for determining whether an instruction word is an infinite self-loop instruction. 2. The instruction word includes an operation code, a branch determination reference bit referred to in branch determination, and an address designator indicating an address of operand data or a branch destination address for a branch instruction. Determining means for inputting the operation code and the branch determination reference bit to determine whether the instruction word is an instruction for unconditionally branching; the branch destination address determining means includes: 2. The system monitoring apparatus according to claim 1, wherein an address of the executed instruction word on the storage device is input to determine whether the instruction word is a self-loop instruction that branches to its own instruction word. 3. The unconditional branch determination means detects that the operation code indicates a branch instruction and that all of the branch determination reference bits indicate a branch. 3. The system monitoring apparatus according to claim 2, wherein the instruction is determined to be an instruction that branches unconditionally. 4. The branch destination address judging means compares the address indicated by the address designator with the address of the instruction to be executed on a storage device. 3. The system monitoring device according to claim 2, wherein it is determined that the instruction is a self-loop instruction. 5. The system according to claim 3, wherein said self-loop determining means notifies a software management program when determining that the executed instruction word is an unconditional self-loop instruction. Monitoring device. 6. The self-loop determining means, when determining that the command to be executed is an unconditional self-loop command, notifies the diagnostic program to execute a fault handling process. 5. The system monitoring device according to 3 or 4. 7. A system monitoring method for a system for sequentially processing instruction words, comprising determining whether or not the instruction word is a branch instruction from an operation code of the instruction word, and referring to the branch determination of the instruction word. It is determined whether the instruction word indicates an unconditional branch from the determined branch determination reference bit, and the address word indicating the address of the operand data of the instruction word or the branch destination address for the branch instruction is the instruction word. It is determined whether or not an address on its own storage device is indicated, the instruction word is a branch instruction, a branch is unconditionally performed, and it is determined that the branch destination is the instruction word itself. In a case, a system monitoring method includes notifying a predetermined device. 8. The system monitoring method according to claim 7, wherein the notification to the predetermined device is a signal for prompting a diagnosis unit to start a failure processing process. 9. The system monitoring method according to claim 7, wherein the notification to the predetermined device is a signal for inhibiting new writing to a tracer memory storing a processing history of the instruction.