JP2000250439A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable interlaced scanning without causing deterioration in picture quality due to a flicker by making luminance modulating elements in adjacent rows illuminate at a specific multiple and obtaining light emission corresponding to the spread of a light emission spot of a CRT display device. SOLUTION: The light emission corresponding to the spread of the light emission spot of the CRT display is obtained by making the luminance modulating elements in adjacent rows illuminate at α times. Namely, when such an image that the luminance of luminance modulating elements in (n) rows and (m) columns is f (n, m), the luminance of dots (n+1, m) is set to α×f (n, m). Here, α is a constant less than 1. A finely hatched part represents luminance modulating elements 250 in a high-luminance state and a roughly hatched part shows luminance modulating elements 252 in a low-luminance state. By this α, dots between scanning lines in a field period illuminate with luminance which is a coefficient α less and a flicker increase can effectively be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for displaying an image by arranging light-emitting elements or light modulation elements in a matrix and controlling the light emission or light modulation characteristics of the elements, and more particularly to an image display by interlaced scanning. The present invention relates to an image display device suitable for displaying an image.

[0002]

2. Description of the Related Art In the following description, "brightness" indicates brightness in the case of a light emitting element, and indicates transmittance or reflectance in the case of a light modulation element such as a liquid crystal element. The term “luminance modulating element” refers to an element whose luminance changes depending on the amplitude or application time of a voltage or current applied to the element.

The intersection of the electrode groups orthogonal to each other is defined as a pixel,
A matrix type display device (matrix type display) that displays an image by adjusting the voltage applied to each pixel includes a liquid crystal display, a field emission display (hereinafter, referred to as “FED”), an electroluminescence display ( EL), light emitting diode display (LED), and the like. For example, F
As described in Japanese Patent Application Laid-Open No. 4-289644, the ED arranges a large number of fine electron emission electron sources in each pixel, accelerates the electrons emitted therefrom in a vacuum, and irradiates the phosphor with the phosphor. Illuminate the illuminated portion of the phosphor.

On the other hand, a cathode ray tube (hereinafter referred to as "CRT") widely used as a television display device displays an image by scanning a plurality of electron beams corresponding to colors on a screen. In this case, interlaced scanning is often used, especially when displaying an image having motion.

[0005] Interlaced scanning means that when displaying an image of N scanning lines, one screen, that is, one frame is composed of two fields. In the first field, only odd-numbered scanning lines are scanned and the second field is scanned. Scans only even-numbered scanning lines. This method is widely used in the transmission of television signals because it has the advantage that it is possible to achieve both responsiveness to image motion and image definition without increasing the signal bandwidth. In addition, interlaced scanning has another advantage that the cost and power consumption of the display device are reduced. For example, when interlaced scanning is adopted in a CRT display device, the deflection frequency of the electron beam is reduced by half as compared with the case where a method of scanning all the scanning lines in one frame (sequential scanning method) is used. This has the advantages described above.

[0006] Despite these advantages, interlaced scanning has been rarely used in matrix displays. As a reason for this,
When interlaced scanning is performed on a matrix type display, flicker increases at the edge of the screen, and the image quality is greatly deteriorated.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a matrix type image display device capable of performing interlaced scanning without deteriorating image quality due to flicker. It is in.

[0008] Recently, images to be displayed have been diversified remarkably. Therefore, if one device can perform not only interlaced scanning but also sequential scanning, it is possible to cope with various images and the practicality of the device is enhanced.

Another object of the present invention is to provide an image display device capable of switching between interlaced scanning and sequential scanning.

[0010]

According to the first object of the present invention, in the first field, the luminance modulation elements in the even-numbered rows adjacent to the odd-numbered rows are replaced with the luminance modulation elements in the odd-numbered rows. Light at α times the brightness (α <1), and in the second field, turn on the brightness modulation elements in the odd-numbered rows adjacent to the even-numbered rows at α times the brightness of the brightness modulation elements in the even-numbered rows. This can be solved effectively.

Such a means has been derived by considering a flicker generation mechanism when the interlaced scanning method is applied to a matrix type display.

FIG. 17 schematically shows a pixel configuration of a conventional matrix type display. The hatched part is the luminance modulation element 250 in the high luminance state, and the unhatched part is the luminance modulation element 251 in the zero luminance state. The row number is shown on the left side of the pixel configuration.

When interlaced scanning is performed, pixels in odd rows are turned on in the first field (FIG. 17A),
The pixels in the even rows in the field light up (FIG. 17b). Usually, in a matrix type display, since the boundary between adjacent pixels is clear, the lighting position of the first field and the lighting position of the second field do not overlap, which causes flicker to increase.

On the other hand, in a CRT display device, a light emitting point (hereinafter referred to as a "light emitting spot") of a phosphor is generated by an electron beam.
Is actually scanned, but the emission spot actually exhibits a Gaussian-like intensity distribution due to factors such as the spread of the electron beam. For this reason, as shown in FIG. 18, for example, when the third scanning line is scanned, the light emission spot spreads to the area corresponding to the adjacent scanning lines 2 and 4 above and below it. This reduces flicker.

The image display device of the present invention obtains light emission corresponding to the spread of the light emission spot of the CRT display device by turning on the luminance modulation elements in the adjacent rows at α times, and effectively suppresses flicker increase. can do.

FIG. 1 schematically shows a pixel configuration of the image display device of the present invention. FIG. 1a shows the display image in the first field,
FIG. 1B schematically shows a display image in the second field. The part with fine hatching is the luminance modulation element 250 in the high luminance state, and the part with coarse hatching is the luminance modulation element 252 in the low luminance state.

In order to display an image in which the luminance of a luminance modulation element of n rows and m columns (hereinafter referred to as a dot (n, m)) is f (n, m), the luminance of the dot (n + 1, m) is displayed. Brightness is α ×
f (n, m). Here, α is a constant less than 1. Due to such α, within the field period,
The dots between the scanning lines are also illuminated with a weak luminance by the coefficient α, and the display state is the same as that of the above-described CRT display device. That is, the flicker increase of the screen which has conventionally occurred in the interlaced scanning is suppressed.

If the value of α exceeds 60%, the image has a slightly blurred impression, and if it is smaller than 0.1%, the effect of suppressing flicker decreases. Therefore, 0.1% <α <6
0% is a particularly desirable range. The required image definition is
It depends on the field of application using the display device and the video source. Also, how to feel flicker is screen brightness, screen size,
It depends on various conditions such as ambient brightness. Therefore, an optimal value of α is set in consideration of these conditions.

A specific driving method for realizing the present invention is shown in FIG. 2 by taking as an example the case where the luminance of the dot (n + 1, m) of the scanning line is set to α times. In FIG. 2, only 4 rows × 4 columns of the matrix type display are extracted and described. Here, as the luminance modulation element 201 of each dot, for example, an element that emits light when a positive voltage is applied to the column electrode 203 while a negative voltage is applied to the row electrode 202 is used.

FIG. 2 also shows the voltage waveforms applied to the rows R1 to R4 of the row electrodes 202 and the columns C1 to C4 of the column electrodes 203 together. At time t0, a row selection pulse 210 of a negative voltage is applied to the row R1, and simultaneously, a positive voltage pulse is applied to the columns C1, C2, and C4. Therefore, the dots (R1, C1), (R1, C2), (R
1, C4) lights up. At this time, a row selection pulse 210 having a negative voltage whose pulse width is multiplied by α is applied to the adjacent row R2. Thereby, the dots (R2, C1), (R2, C2), (R
2, C4) is lit at a luminance α times the row R1.

Next, at time t1, a row selection pulse 210 of a negative voltage is applied to the row R3, and a positive voltage pulse is applied to the columns C1 and C3 to form dots (R3, C1), (R3, C3). Lights up. Also in this case, similarly to the above, a row selection pulse 210 having a negative voltage twice the pulse width α is applied to the adjacent row R4. As a result, the dots (R4, C1) and (R4, C3) become
Lights up at twice the brightness.

In this way, an image corresponding to FIG. 1a is obtained. In the next field, an image corresponding to FIG. 1b is obtained by pairing the rows R2 and R3 and applying a pulse having a pulse width α times to R3.

In the one-row simultaneous addressing method described above, that is, a method in which all dots on one row electrode are simultaneously addressed, a signal switching interval corresponding to image data applied to a column electrode (see FIG. In time 2, from time t0 to t1
Is the scanning cycle. The longer the switching cycle, that is, the lower the switching frequency, the lower the speed of signal processing and the response time constant of the circuit, so that the circuit can be simplified and the cost can be reduced. As can be seen from FIG. 2, the switching period of the column electrode application pulse is one row.
The switching frequency corresponds to the time of every other scan, that is, the time of the interlaced scanning, and the switching frequency is halved compared to the case of the sequential scanning. Therefore, according to the present invention, the above advantages of the interlaced scanning obtained in the CRT display device can be obtained also in the matrix type display.

In this example, the pulse width applied to the row electrode 202 is changed to increase the luminance ratio between the n-th row and the (n + 1) -th row by α. That is, pulse width modulation is used. On the other hand, when the luminance B of the element has an exponential characteristic with respect to the voltage V applied to the element, that is, when there is a relationship of B = C exp (V), amplitude modulation can be used.
In this case, when −V0 is applied to the nth row Rn of the row electrode 202, − (V0−ΔV0) is applied to the (n + 1) th row Rn + 1. Assuming that the positive voltage applied to the m-th column Cm of the column electrode 203 and corresponding to the image data is Vp, the dot (Rn,
Cm) and (Rn + 1, Cm) are respectively Therefore, ΔV0 may be set so that α = exp (−ΔV0).

Here, the luminance B-voltage V characteristic of the element does not need to exactly match the exponential function characteristic. If the characteristic deviates from the exponential function characteristic, the α value fluctuates depending on the voltage (V0 + Vp). However, since the human visual characteristics are not so strict, a change in the α value that does not seem unnatural to the eye is allowed. .

In the above examples, only the lower row of the (n + 1) th row is turned on when scanning the nth row. However, only the (n-1) th row of the upper row may be turned on. n + 1
The top and bottom of the row and the (n-1) th row may be turned on at the same time. In this case, the luminance of the (n + 1) th row and the (n−1) th row is set to α /
Make it double.

FIG. 3 shows a driving method when the upper and lower rows are turned on at the same time. In FIG. 3, contrary to the driving method of FIG. 2, when a positive pulse is applied to the row electrode 202 and no pulse is applied to the column electrode 203, the intersection is lit. On the other hand, when a positive pulse is applied to the column electrode 203, the intersection does not light (luminance is zero). During the period from time t1 to t2, when a long pulse is applied to the row R3 serving as a main display dot and a short pulse is applied to the rows R2 and R4, the row R3 is turned on with high brightness, and the row R2 is turned on. , R
The dot 4 is lit at α / 2 times the luminance. This allows
Light emission can be obtained which is closer to the CRT light emission spot where light emission spreads on both sides of the main display dot.

In the above description, a light-emitting display is taken as an example. However, the present invention can be similarly applied to a non-light-emitting display such as a liquid crystal display, and a similar effect can be obtained. Not even.

As described above, according to the present invention, in displaying an image on a matrix type display, it is possible to perform interlaced scanning without increasing flicker.

The second object of the present invention can be effectively solved by adopting a circuit configuration in which an operation state changes by a change in a pulse arrangement of a clock signal in a drive circuit for driving a row electrode. it can. As will be described in detail later, two separate shift registers are used for driving a row that emits light at high luminance and for driving a row that emits light at α times, and the pulse arrangement is interlaced scanning and sequential scanning. In the case of interlaced scanning, both shift registers are operated, and in the case of sequential scanning, only the high-luminance shift register is operated at twice the speed. This makes it possible to switch between interlaced scanning and sequential scanning.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image display device according to the present invention will be described in more detail with reference to embodiments of the present invention according to some embodiments shown in the drawings. Note that the same symbols in FIGS. 1 to 17 indicate the same or similar objects.

[0032]

<Example 1> A display panel in which a brightness modulation element for each dot is formed by a combination of a thin-film type electron source, which is an electron emission electron source, and a phosphor is used and driven by row electrodes and column electrodes of the panel. An embodiment in which circuits are connected will be described with reference to FIGS.

FIG. 4 is a plan view of the display panel viewed from the face plate side, and FIG. 5 is a plan view of the display panel substrate viewed from the face plate side. 6A is a cross-sectional view taken along line AB in FIGS. 4 and 5, and FIG. 6B is a left half view of a cross-section taken along line CD.

4 and 5, 13 is a lower electrode serving as a row electrode, 11 is an upper electrode serving as a column electrode formed on the lower electrode 13, and 32 is a drive electrode for driving the upper electrode 11. The upper electrode bus line, 114A is a phosphor emitting red (R), 114B is a phosphor emitting green (G), 114C is a phosphor emitting blue (B), 60 is a spacer surrounding the phosphor 114, 120 is This is a black matrix formed between the phosphors 114.

Next, in FIG. 6A and FIG.
Is a substrate for forming each electrode, and 12 is an upper electrode 1
An insulating layer provided between the first electrode and the lower electrode 13, a protection layer 15 for insulating the upper electrode bus line 32 from the lower electrode 13, a face plate 110 coated with a phosphor 114, and a phosphor layer 122. The accelerating electrode 10 formed on the 114 is a vacuum space formed between the substrate 14 and the face plate 110 via the spacer 60. The acceleration electrode 122 also functions as a metal back.

In such a structure, a thin-film electron source is formed at the intersection of the upper electrode 11 and the lower electrode 13,
The phosphor 114 is excited by electrons from the thin film electron source,
Emits light.

Such a thin film electron source was manufactured according to the procedure shown in FIG. In FIG. 7, the right column shows a plan view, and the left column shows a cross-sectional view taken along line AB of the plan view. FIG.
Although only one electron source is illustrated in FIG. 5, the electron sources are actually arranged in a matrix as shown in FIGS.

On a glass substrate 14, as a thin film for the lower electrode 13, Al was deposited to a thickness of 300 n by a sputtering method.
m. The material of the substrate 14 may be any material having an insulating property other than glass, and the Al film may be formed by a resistance heating evaporation method or the like in addition to the above method.

Next, the Al film was processed into a stripe by resist formation by photolithography and subsequent etching to form a lower electrode 13. The resist used here may be a resist suitable for etching, and the etching can be any of wet etching and dry etching.

The surface of the lower electrode 13 was anodized under a formation voltage of 4 V to form an insulating layer 12 having a thickness of 5.5 nm (see FIG. 7A). The thickness of the insulating layer is 5 to 10
It may be in the range of nm.

Next, a quinonediazide-based positive resist was applied and exposed to ultraviolet rays to perform patterning, thereby forming a resist pattern 501 shown in FIG. 7B.
Subsequently, with the resist pattern 501 attached, anodic oxidation was performed again to form the protective layer 15. In the second anodization, the formation voltage was set to 50 V, and the thickness of the protective layer 15 was set to 70 nm (see FIG. 7C).

After the resist pattern 501 was peeled off with an organic solvent such as acetone, a resist pattern 502 shown in FIG. 7D was formed in the same manner as described above. Thereafter, a metal film to be the upper electrode bus line 32 was formed on the entire surface of the substrate 14. The metal film was a laminated film composed of a lower layer of Mo and an upper layer of Au, which was formed by a sputtering method. The film thickness was 30 nm for the Mo film and 100 nm for the Au film. In addition, other metals such as Cr, Ta, W, and Nb having good adhesion to the insulating substrate 14 can be used for the lower layer. In the upper layer, in addition to Au, Pt, Ir, R
It is possible to use a metal which is rich in electric conductivity and hardly oxidized, such as h and Ru. By using these metals, electrical contact with the upper electrode 11 formed later can be ensured.

For the formation of the metal film, a vapor deposition method or the like other than the above-described sputtering method can be adopted, and it is preferable to form a laminated film by continuous film formation in any method. The thickness of the metal film is appropriately selected according to the required specification of the wiring resistance.

Subsequently, the resist pattern 502 was lifted off with acetone as an organic solvent to obtain a shape shown in FIG. 7E.

Thereafter, a resist pattern 503 shown on the right side of FIG. 7F was formed. In this state, anodization was performed by immersion in a chemical conversion solution. The formation voltage was the same voltage of 4 V as when the insulating layer 12 was formed. The insulating layer 12 has been slightly damaged by a chemical such as a developer in the resist patterning process performed several times. Therefore, before the upper electrode 11 is formed, the damage is repaired by anodizing the insulating layer 12 again.

Subsequently, the film thickness of 1 was formed by sputtering.
A 0 nm ITO (Indium Tin Oxide) film was formed to form an upper electrode 11 of a transparent electrode.

Then, by lifting off with an organic solvent such as acetone, an electron source having a structure shown in FIG. 7G was obtained. Through the above process, a thin-film electron source is completed on the substrate 14. In this thin-film electron source, electrons are emitted from a region defined by the resist pattern 501. Since the protective layer 15, which is a thick insulating film, is formed around the electron emitting portion, the electric field applied between the upper electrode 11 and the lower electrode 13
The inconvenience of concentrating on the side or the corner of is avoided. Thus, the thin-film electron source of this embodiment can obtain stable electron emission characteristics for a long time.

Next, a face plate 110 provided with a phosphor 114 was manufactured by the following procedure. Glass was used for the face plate 110. The face plate 110 may be a light-transmitting material other than glass. First, a black matrix 120 was formed on the face plate 110 in order to increase the contrast of the display device (FIG. 6B).
reference). The black matrix 120 is arranged between the phosphors 114 in FIG. 4, but is not shown in FIG. 4 in order to avoid display complexity.

Next, a red phosphor 114A, a green phosphor 114B,
A blue phosphor 114C was formed. The patterning of these phosphors was performed using photolithography in the same manner as used for producing a phosphor screen of an ordinary cathode ray tube. As the phosphor, red _{Y 2 O 2 S: Eu (} P22-R), green Zn ₂ Si
O ₄ : Mn (P1-G1) and ZnS: Ag (P22-B) for blue.

Subsequently, after covering the entire face plate 110 with a thin film of nitrocellulose, the entire face plate 110 is similarly coated with Al to a thickness of 50 nm.
An acceleration electrode (metal back) 122 was formed by vapor deposition in a range of about 300 nm. Thereafter, the face plate 110 was heated to about 400 ° C. to thermally decompose the thin film and organic substances such as PVA (polyvinyl alcohol) used during the above steps. Thus, the face plate 110 was completed.

The face plate 110 and the substrate 1 thus manufactured
4 was sealed using frit glass (low-melting glass) with a frame glass (not shown) around the panel and a spacer 60 interposed therebetween. The positional relationship between the face plate 110 and the substrate 14 is as shown in FIG. FIG. 5 shows a pattern of the thin-film electron source formed on the substrate 14 corresponding to FIG. However, illustration of the protective layer 15 and the upper electrode surface layer film is omitted.

The distance between the face plate 110 and the substrate 14 is 1 to
The range was 3 mm. The spacer 60 is inserted in order to prevent the panel from being damaged by an external force due to the atmospheric pressure when the inside of the panel is evacuated.
Therefore, when a display device having a display area of about 4 cm in width and about 9 cm in length is manufactured by using glass of 3 mm in thickness for the substrate 14 and the face plate 110, the atmospheric pressure is determined by the mechanical strength of the face plate 110 and the substrate 14 itself. Therefore, it is only necessary to insert the frame glass around the panel, and there is no need to insert the spacer 60.

In FIG. 4, R (red), G (green), B (blue)
Although the columns of the spacer 60 are provided for each dot that emits light, that is, for each of the three rows of the upper electrode 11, the number (density) of columns can be reduced as long as the mechanical strength can withstand. The spacer 60 is manufactured by forming a hole having a desired shape in an insulating plate such as glass or ceramic having a thickness of about 1 to 3 mm by, for example, a sandblast method.

Finally, the sealed panel was removed to about 1 × 10 ⁻⁷ Torr.
Was evacuated and sealed. Thus, a display panel using the thin-film electron source was completed.

In this embodiment, since the distance between the face plate 110 and the substrate 14 is as long as 1 to 3 mm, the acceleration voltage applied to the metal back 122 can be as high as 3 to 6 KV. Therefore, it becomes possible to use a phosphor for a cathode ray tube (CRT) that emits light at a high acceleration voltage exceeding 3 KV.

FIG. 8 shows the relationship between the applied voltage and the electron emission current of the thin-film electron source of this embodiment, which is a luminance modulation element in combination with a phosphor. The vertical axis is logarithmic. As can be seen from this figure, the current-voltage characteristics are almost exponential. Since the light emission intensity of the phosphor is proportional to the current, the luminance B-voltage V characteristic also becomes an almost exponential function.

In this embodiment, the upper electrode bus line 3
By changing the signal applied to 2, a desired image or information can be displayed. That is, the upper electrode bus line 3
By appropriately changing the magnitude of the applied voltage V2 to 2 in accordance with the image signal, an image with gradation can be displayed. Since the luminance B and the applied voltage V are close to an exponential relationship B = C exp (V), the applied voltage V2 to the upper electrode bus line 32 is
Irrespective of the size of, the luminance difference between adjacent rows is about exp (-ΔV), which is almost constant (α times). Therefore, in this embodiment, amplitude modulation is adopted to increase the luminance ratio by α times.

FIG. 9 shows the structure of an image display device in which a drive circuit is connected to the manufactured display panel. In the same figure, 41 is a lower electrode drive circuit connected to each row R1 to R3 of the lower electrode 13, 42 is an upper electrode drive circuit connected to each column C1 to C3 of the upper electrode bus line 32, and 43 is an acceleration electrode This is an acceleration electrode drive circuit connected to 122. As described above, the dot at the intersection of the n-th row Rn of the lower electrode 13 and the m-th column Cm of the upper electrode bus line 32 is defined as (Rn, Cn
m).

FIG. 10 shows the waveform of the voltage generated by each drive circuit and the light emitting state of the display panel. Each waveform is set based on the amplitude modulation. Further, a voltage in the range of 3 to 6 KV is constantly applied to the acceleration electrode 112 from the acceleration electrode drive circuit 43. In FIG. 10, the lower electrode 13 is a row electrode 202.
(Rows R1, R2, R3, R4), and the upper electrode bus lines 32 become column electrodes 203 (columns C1, C2, C3, C4).

At time t0, no voltage is applied to any of the electrodes, so that no electrons are emitted, and thus the phosphor 114 does not emit light.

From time t0 to time t1, the row selection pulse 210 of the voltage -V1 is applied to the row R1 of the lower electrode 13, and the row selection pulse 2 of the voltage -V3 =-(V1-ΔV) is applied to the adjacent row R2.
Apply 10. At the same time, the column C of the upper electrode bus line 32
A pulse of + V2 is applied to 1, C2 and C4. In each dot serving as the luminance modulation element 201, the dot (R1,
Since a voltage of (V1 + V2) is applied between the lower electrode 13 and the upper electrode 11 of (C1), (R1, C2) and (R1, C4), electrons are emitted from the thin-film electron source of these three dots. Vacuum 1
Released during 0. The emitted electrons are accelerated by the high voltage applied to the acceleration electrode 122 and collide with the phosphor 114 to cause the phosphor 114 to emit light. Thereby, the dot (R
(1, C1), (R1, C2) and (R1, C4) are lit with high luminance. Also, dots (R2, C1), (R2, C2), (R2, C
In (4), since a voltage of (V1 + V2−ΔV) is applied, electrons are emitted similarly to cause the phosphor 114 to emit light. However, when the applied voltage is equal to the dots (R1, C1), (R1, C2), (R1,
Since each is lower than C4) by exp (-. DELTA.V), the emission current amount is .alpha. Times and the luminance is .alpha. Times. Where α is
It is an almost constant value in the range of 0.1% to 60%.

Next, from time t1 to time t2,-
A row selection pulse 210 having a voltage of V1 is applied, and an adjacent row R
4 is a row selection pulse 2 having a voltage of -V3 =-(V1-ΔV).
Apply 10. When a pulse of the voltage V2 is applied to the columns C1 and C3, the dots (R3, C1) and (R3, C3) light up with high brightness, and the adjacent dots (R4, C1) and (R4, C3) have their α. Lights up at twice the brightness. By applying such a voltage,
The finely hatched dots in FIG.
1) is lit at a relative luminance of 1, and the coarsely hatched dots are lit at a relative luminance α.

As described above, an image corresponding to the odd field in FIG. 1A can be displayed. In the subsequent even field, a voltage of -V1 is applied to the row R2 of the lower electrode 13 from time t0 to t1, and -V3 =-
A voltage waveform of (V1-.DELTA.V) is applied, and the voltage waveform is shifted by two rows. In this case, FIG.
An image corresponding to the even field of b is displayed. By alternately repeating the two, an image by interlaced scanning can be displayed.

FIG. 11 shows details of the lower electrode driving circuit 41 for performing such driving. Shift register for odd rows
The output signals of the shift register 401 and the even-numbered row shift register 402 are supplied to the signal switch 403. The signal switch 403 has an input terminal A1 and an output terminal A according to a signal from the field switch 405.
2 and input terminal B1 and output terminal B2, or connect terminal A1
And terminal B2 and between terminal B1 and terminal A2.

The output driver circuit 404 receives the signals of the output terminals A2 and B2 of the signal switch 403 at the input terminals M and S, and outputs a signal for driving the row electrode 202 to the output terminal out. The output driver circuit 404 is provided for each row of the row electrode 202, and an output terminal outi (i = 1, 2, 3, 4) is connected to the row Ri. The output driver circuit 404 outputs a main pulse when a signal is input to the input terminal Mi, and outputs a sub-pulse when a signal is input to the input terminal Si. Here, the main pulse is applied to the row electrode 20 corresponding to the main display dot of high luminance.
The sub-pulse is a pulse applied to the adjacent row electrode 202 such that the luminance becomes α times the luminance.

In order to realize the waveform shown in FIG.
From t1 to t1, the output of the odd-row shift register 401 is input to the signal switch 403 corresponding to the first row, and the output of the even-row shift register 402 is input to the signal switch 403 corresponding to the second row.
To enter. Then, a main pulse is output from the output terminal out1, and a sub-pulse is output from the output terminal out2.

At time t1, shift registers 401, 40
When both 2 are shifted up, the output terminal out
The main pulse is output from 3 and the sub-pulse is output from the output terminal out4. In this manner, the waveform shown in FIG. 10 can be realized. <Embodiment 2> The electron source of the display panel in which the thin-film electron source in Embodiment 1 is changed to a field emission electron source which is another electron emission electron source. The part is shown in FIG. The method of producing the field emission type electron source is described in, for example, Japanese Patent Application Laid-Open No. 4-289644, and the description of the production procedure is omitted. Hereinafter, the structure of the manufactured electron source will be described.

There is a lower electrode 301 on a glass substrate 300,
On top of this is a resistance layer 302 made of amorphous Si.
Other insulating materials can be used for the substrate 300, and other conductive materials can be used for the resistance layer 302.

An insulating film 305 having a thickness of about 1 μm is formed on the resistance layer 302.
And a gate electrode 304 is provided thereon. Gate electrode 304
The insulating film 305 has a hole having a diameter of about 1 μm, in which a chip 303 made of Mo is provided. Chip 30
3 can be made of a conductive material such as Si in addition to Mo.

When an appropriate voltage is applied between the gate electrode 304 and the lower electrode 301 so that the gate electrode 304 becomes positive, electrons are emitted from the tip of the chip 303 by field emission. By patterning the gate electrode 304 and the lower electrode 301 so as to be orthogonal to each other, an intersection of the two electrodes becomes an electron source to be a brightness modulation element (dot). Usually 1
About 1000 to 10000 chips 303 are formed in each dot to reduce variations in the field emission current. In addition,
The resistance layer 301 functions as a stabilizing resistor for stabilizing the emission current.

The substrate 300 on which the field emission type electron source is formed
Is combined with a face plate coated with a phosphor in the same manner as in Example 1, and the same face plate is sealed to a substrate 300 to form a panel.
The inside was evacuated to vacuum and sealed. By applying a voltage to the accelerating electrode on the face plate, electrons emitted from the field emission type electron source are accelerated, and the electrons excite the phosphor to emit light. Thus, the intersection of the gate electrode 304 and the lower electrode 301 becomes a luminance modulation element.

FIG. 13 shows a waveform of a voltage applied to each electrode of the field emission type electron source. The gate electrode 304 becomes the row electrode 202 (row R1, R2, R3, R4) and the lower electrode 301
Become the column electrodes 203 (columns C1, C2, C3, C4).

At time t0, a row selection pulse 210 having a voltage V11 is applied to the row R1, and a row selection pulse 210 having a short pulse width and the voltage V11 is applied to the row R2. Columns C1, C2, C4 are 0
With the voltage kept at V, a pulse of the voltage V12 is applied to the column C3.
Then, in each dot of the luminance modulation element 201, a dot
The gate electrode 304 of (R1, C1), (R1, C2), (R1, C4)
The applied voltage between and the lower electrode 301 is V11,
The applied voltage between the gate electrode 304 and the lower electrode 301 of (R1, C3) is V11-V12. Gate electrode 304 and lower electrode 3
When the applied voltage during 01 becomes V11, electrons are sufficiently emitted, and when V11-V12, electrons are not emitted. Therefore, as shown in FIG. 13, dots (R1, C1), (R
(1, C2) and (R1, C4) indicate that the phosphor emits light with high luminance corresponding to the applied voltage V11, and the dots (R2, C1), (R2, C2),
(R2, C4) emits light at low luminance corresponding to the short pulse width applied to the row electrode, and further emits dots (R1, C3), (R2, C4).
3) does not emit light because the applied voltage is V11-V12.

As described above, an image corresponding to the odd field in FIG. 1A can be displayed. In the subsequent even-numbered field, the voltage V11 is applied to the row R2 of the gate electrode 304 from time t0 to t1, and the voltage V11 is applied with a short pulse width to the adjacent row R3 to form a voltage waveform shifted by two rows.
In this way, an image corresponding to the even field in FIG. 1B can be displayed. By alternately repeating the two, an image by interlaced scanning can be displayed.

In FIG. 13, the brightness of the dots on the adjacent row is adjusted by shortening the pulse width applied to the row R2. Instead, the amplitude of the pulse applied to the row R2 is reduced. To adjust the brightness.

In the first and second embodiments, a thin film type electron source and a field emission type electron source have been described as examples of the brightness modulation element using a combination of an electron source and a phosphor. It is needless to say that the present invention is not limited to the source, and it is needless to say that another electron emission electron source such as a surface conduction electron source can be used, and the same effect can be obtained. For example, a method for producing a surface conduction electron source is described in, for example, Journal of the Society for Information Display.
mation Display) Volume 5 Issue 4 (issued in 1997) Issue 3
Pp. 45-348.

<Embodiment 3> As a third embodiment of the present invention, a display device using an organic electroluminescent element as a luminance modulation element will be described. The brightness modulation element 201 in FIG. 2 is an organic electroluminescent element. The anode of the organic electroluminescent device is connected to the column electrode 203, and the cathode is connected to the row electrode 202. In addition, about the structure and the manufacturing method of an organic electroluminescent element, for example, SID97 Digest magazine (SID97 Digest) pages 1073-10
Page 76 (issued in May 1997).

With the above connection, only the organic electroluminescent element 201 to which the row selection pulse 210 is applied to the row electrode 202 and the positive pulse is applied to the column electrode 203 at the same time emits light. Row electrode 202
The organic electroluminescent element 201 on the row R2 of FIG.
Since the pulse width is shorter, light is emitted with lower luminance, so that the state of FIG. 1A can be realized, and an interlaced display without flicker can be realized. In this embodiment, when the row selection pulse 210 applied to the row electrode 202 is set to a positive voltage and the pulse applied to the column electrode 203 is set to a negative voltage, the cathode is set to the column electrode 203 and the anode is set to the row electrode 202. And the same interlaced display can be realized.

As the luminance modulating element 201, an inorganic electroluminescent element or a light emitting diode can be used in addition to the above-described organic electroluminescent element, and it goes without saying that the same effect can be obtained.

Here, in the description of the first to third embodiments with reference to FIGS. 2, 3 and 10, the pulse application to the electrodes has been described as “voltage pulse”. In the case of driving, a “current pulse” may be used, and it goes without saying that the same effect can be obtained in that case.

<Embodiment 4> An embodiment in which the drive circuit in Embodiment 1 is changed to a drive circuit capable of switching between interlace scanning and sequential scanning will be described. FIG. 14 shows a drive circuit of this embodiment. The output signals of the shift register for main pulse 411 and the shift register for sub-pulse 412 are supplied to the output driver circuit 404. The output driver circuit 404 is substantially the same as that used in the first embodiment, but is configured to operate only when an enable signal (Enable in the figure) is input. Output terminals out1 to o of each output driver circuit 404
ut4 is connected to the rows R1 to R4 of the row electrodes, respectively. The signal CLK1 is input as a shift-up clock signal of the main pulse shift register 411, and the signal C1 is input as a shift-up clock signal of the sub-pulse shift register 412.
LK2 is input.

FIG. 15 shows an outline of the operation of the present driving circuit.
In the figure, M1 to M4 and S1 to S4 are input terminals M1 to M4 and S1 to S4 of the output driver circuit 404 of each row, respectively.
4 shows the input signal. The first feature of this circuit system is that the pulse width of input signals to the input terminals M1 to M4 is reduced every other row by shifting up the shift registers 411 and 412 by two clocks. In combination with the enable signal, the output driver circuit 404 is prevented from operating for a signal having a short pulse width, and interlaced scanning is realized.

The second feature is that, at the beginning of a field, an adjustment pulse 501 for each field is input to the clock signals CLK1 and CLK2, and the number of the pulses is changed by one between the clock signals CLK1 and CLK2. is there. As a result, at time t1, the input terminals M1,
Since a signal is input to S1, a main pulse is output from the output terminal out1, and a sub-pulse is output from the output terminal out2. In this way, the waveform shown in FIG. 10 can be realized.

In the next field, the number of adjustment clock pulses 501 for each field is set to two for the clock signal CLK1 and three for the clock signal CLK2. As a result, since the whole is shifted by one row, the main pulse is output from the output terminals out2 and out4, and the sub-pulse is output from the output terminal out3. Therefore,
The display shown in FIG. 1 can be realized. When realizing the waveforms as shown in FIGS. 2, 3, and 13, the circuit configuration of the output driver circuit 404 is changed so that a width-modulated pulse is obtained.

FIG. 16 shows signal waveforms when sequential scanning (non-interlaced scanning) is performed with the same drive circuit configuration.
Shown in By making the clock signal CLK1 an equally spaced clock, main pulses are output from the output terminals out1, out2, out3, and out4 line by line in the order of M1, M2, M3, and M4, as shown in FIG. . That is, sequential scanning is performed. In this case, the clock signal CLK2 stops, and the input terminal S
No signal is input to 1, S2, S3 and S4.

As described above, the present driving circuit has a feature that interlaced scanning and sequential scanning can be realized only by changing the clock signals CLK1 and CLK2 with the same circuit configuration. As described above, an image display device capable of switching between interlaced scanning and sequential scanning can be easily and inexpensively realized.

[0087]

According to the present invention, an adjacent row is lit at α times the luminance, so that an image can be displayed on a matrix type display by an interlaced scanning method without deteriorating the image quality due to an increase in flicker. become. Further, by employing a drive circuit capable of changing the scanning method only by changing the clock signal, it is possible to easily and inexpensively realize an image display device capable of switching between interlaced scanning and sequential scanning.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a pixel configuration of an image display device according to the present invention.

FIG. 2 is a diagram illustrating an example of a driving method of the image display device according to the present invention.

FIG. 3 is a diagram for explaining another example of the driving method of the image display device of the present invention.

FIG. 4 is a plan view illustrating a display panel of the first embodiment of the image display device according to the present invention.

FIG. 5 is a plan view for explaining a substrate of the display panel of the first embodiment.

FIG. 6 is a cross-sectional view for explaining the display panel of the first embodiment.

FIG. 7 is a process chart for explaining the procedure for manufacturing the display panel of the first embodiment.

FIG. 8 is a curve diagram for explaining a relationship between an applied voltage and an electron emission current.

FIG. 9 is a diagram illustrating a device configuration including a drive circuit according to the first embodiment.

FIG. 10 is a diagram for explaining a driving method according to the first embodiment.

FIG. 11 is a circuit diagram illustrating a circuit for driving a row electrode according to the first embodiment;

FIG. 12 is a cross-sectional view illustrating a display panel according to a second embodiment.

FIG. 13 is a diagram illustrating a driving method according to a second embodiment.

FIG. 14 is a circuit diagram illustrating a circuit for driving a row electrode according to a fourth embodiment.

FIG. 15 is a waveform chart for explaining the operation of the circuit shown in FIG. 14;

16 is another waveform chart for explaining the operation of the circuit shown in FIG.

FIG. 17 is a diagram illustrating a pixel configuration of a conventional image display device.

FIG. 18 is a view for explaining a conventional CRT display device.

[Explanation of symbols]

10 space part, 11 upper electrode, 12 insulating layer, 13 ...
Lower electrode, 14: substrate, 15: protective layer, 32: upper electrode bus line, 41: lower electrode drive circuit, 42: upper electrode drive circuit, 43: acceleration electrode drive circuit, 110: face plate, 114 ...
Phosphor, 120: black matrix, 122: accelerating electrode (metal back), 201: luminance modulation element, 202: row electrode, 203
... column electrode, 210 ... row selection pulse, 250 ... luminance modulation element in a high luminance state, 251 ... luminance modulation element in a luminance zero state, 252 ... luminance modulation element in a low luminance state.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Makoto Okai 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. F-term in the Central Research Laboratory (Reference) 2H093 NA06 NA45 NA56 ND10 ND20 NH18 5C080 AA06 AA18 DD06 EE29 FF12 GG08 GG09 GG12 JJ02 JJ04 JJ05 JJ06 5C094 AA02 AA51 AA56 BA21 BA24 BA27 BA43 CA19 GA10 JA01

Claims (8)

[Claims] 1. An image display apparatus comprising: a display panel in which luminance modulation elements are arranged in a matrix; and a drive circuit for driving the display panel, wherein the drive circuit is arranged in an odd-numbered row in a first field. The luminance modulation elements on the adjacent even-numbered rows are lit at α times the luminance of the luminance modulation elements on the odd-numbered rows (α <1). In the second field, the luminance modulation elements on the odd-numbered rows adjacent to the even-numbered rows are turned on. An image display device wherein the display panel is driven by interlaced scanning so that the luminance modulation elements are turned on at α times the luminance of the luminance modulation elements in the even-numbered rows. 2. The brightness ratio α ranges from 0.001 to 0.5.
The image display device according to claim 1, wherein 3. In the first field, the even-numbered row adjacent to the odd-numbered row is a row below the odd-numbered row, and the odd-numbered row adjacent to the even-numbered row in the second field. The image display device according to claim 1 or 2, wherein is a line below the even-numbered line. 4. In the first field, even-numbered rows adjacent to odd-numbered rows are rows above and below the odd-numbered rows, and odd-numbered rows adjacent to even-numbered rows in the second field. 3. The image display device according to claim 1, wherein the first row is a row above and below the even-numbered row. 5. The driving circuit according to claim 1, wherein the driving circuit drives the display panel by using a pulse. In the first field, an α-times width of a pulse applied to a luminance modulation element in an odd-numbered row is an even-numbered row. In the second field, α times the width of the pulse applied to the even-numbered row of brightness modulation elements is the width of the pulse applied to the odd-numbered row of brightness modulation elements in the second field. The image display device according to claim 1, wherein: 6. The driving circuit drives a display panel by using a pulse. In a first field, the luminance modulation elements in the even-numbered rows are α times the luminance of the luminance modulation elements in the odd-numbered rows. The amplitude of the pulse applied to the luminance modulation elements in the even-numbered rows is set to be lower than the amplitude of the pulses applied to the luminance modulation elements in the odd-numbered rows so that the luminance of the odd-numbered rows in the second field is turned on. The amplitude of the pulse applied to the odd-numbered row luminance modulation elements is such that the amplitude of the pulse applied to the odd-numbered row luminance modulation elements is such that the modulation elements are lit at α times the luminance of the even-numbered row luminance modulation elements. 2. The method according to claim 1, wherein the value is set lower.
The image display device according to claim 4. 7. The thin-film type electron source comprising two kinds of electrodes and an insulating layer sandwiched between the two kinds of electrodes,
7. A display element selected from the group consisting of a field emission electron source, an organic electroluminescence element, an inorganic electroluminescence element, a light emitting diode element and a surface conduction electron source. 13. The image display device according to claim 1. 8. An image display device comprising: a display panel on which luminance modulation elements are arranged in a matrix; and a drive circuit for driving the display panel, wherein the drive circuit comprises: an odd-numbered row in a first field; Are turned on at α times (α <1) the luminance of the odd-numbered row luminance modulation elements, and the odd-numbered rows adjacent to the even-numbered rows in the second field. The operation of driving the display panel by interlaced scanning so that the luminance modulation elements of the even numbered rows are illuminated at α times the luminance of the luminance modulation elements of the even-numbered rows; and An image display device, wherein an operation of sequentially driving a display panel is switched in accordance with an arrangement of clock pulses.