JP2000243930A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fill the inside of a trench of high aspect ratio with a silicon film without introducing voids or seams. SOLUTION: An oxide film 14 of not forming Si nucleus is formed on the side wall of a trench 7. Subsequently, a part from the bottom to the middle of the trench 7 is filled with an As-doped polysilicon film 13 that forms Si nuclei. The inside of the trench 7 is further filled with an As-doped polysilicon film 15 by means of selective CVD of Si. The unfilled part of the trench 7 is filled with an As-doped polysilicon film 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device characterized by a method for embedding a groove.

[0002]

2. Description of the Related Art As semiconductor integrated circuits typified by DRAMs become highly integrated and miniaturized, the element area is reduced with each generation. In a DRAM in which a memory cell is composed of one transistor and one capacitor, reduction in element area leads to reduction in the area of a capacitor for storing information.
This impairs the information storage function.

[0003] In order to prevent the information storage function from being impaired by the high integration and miniaturization of the DRAM, various contrivances have been made to ensure a sufficient capacitance of the capacitor. One of them is to make a capacitor into a three-dimensional structure, that is, to employ a trench capacitor or a stacked capacitor.

When a trench capacitor is used,
It is necessary to fill the inside of the trench having a high aspect ratio of 20 or more with a polysilicon film. An LPCVD method, which is a film forming method having good step coverage, is conventionally used for filling the holes.

However, even if the LPCVD method is used, it is difficult to bury the inside of the trench having a high aspect ratio with a polysilicon film with good coverage, as shown in FIG. Or seams (seams).

[0006] Voids and seams are caused by the formation of growth nuclei in the LPCVD process starting from the side walls of the trench. In this case, if there is a place where nucleus growth from the side wall is fast, the hole is closed at that place and a void is generated below. Even when no voids are formed, a seam occurs when the film grown from the side wall is joined at the center of the trench.

The presence of voids and seams increases the resistance, and in addition, oxidizes the exposed portions of the voids and seams in the oxidation step, stresses the periphery of the trench due to volume expansion, and reduces the charge retention time due to crystal defects. And other problems.

[0008] In order to solve such a problem, there has been proposed a method in which the upper portion of the trench is tapered to improve the embedding property. However, in this case, since the diameter at the trench opening surface is larger than the diameter inside the trench, improvement in the degree of integration is hindered.

[0009]

As described above, the hole is buried by the LPCVD method which has a good step coverage than the conventional method. Is difficult to embed with a polysilicon film with good coverage, and there is a problem that voids and seams occur.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device in which a groove having a high aspect ratio can be buried without causing voids or seams. It is in.

[0011]

Means for Solving the Problems To achieve the above object, a method for manufacturing a semiconductor device according to the present invention is directed to a method for manufacturing a semiconductor device having a step of filling the inside of a groove with a film. As a groove, a side wall is made of a material in which the material of the film does not form nuclei by CVD, and a bottom surface is formed by a CVD method. It is characterized by being formed by.

In the present invention, the term “not nucleated” means not to form nuclei at all, and also to a small nucleation such that voids or seams are not substantially formed by nucleation from the side walls even if nuclei are formed. Includes as meaning.

According to the present invention, the film can be preferentially grown from the bottom of the groove, so that the inside of the groove having a high aspect ratio can be filled without causing voids or seams. Become.

[0014]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 to 3 are process sectional views showing a method for manufacturing a trench capacitor according to a first embodiment of the present invention. This trench capacitor is D
It is used for a memory cell of a RAM.

[0016] First, as shown in FIG. 1 (a), injecting the As (arsenic) ions on the surface of the silicon substrate 1, a depth of about 3μm by performing thermal diffusion continues n ^- -type diffusion layer 2 I do.

Next, as shown in FIG. 1B, after an oxide film 3 having a thickness of about 10 nm is formed on the n ⁻
A silicon nitride film 4 having a thickness of about 300 nm and a BSG film 5 having a thickness of about 700 nm are formed by the PCVD method.

Next, as shown in FIG. 1C, using the photoresist pattern 6 as a mask, the silicon nitride films 4, B
The SG film 5 is etched by RIE.

Next, as shown in FIG. 1D, the photoresist pattern 6, the silicon nitride film 4, and the BSG Membrane 5
Is used as a mask, the silicon substrate 1 is etched by RIE to form a trench 7. The aspect ratio of this trench is 20 or more.

Next, as shown in FIG.
50 nm thick AsSG (As doped Silicate)
After forming a (glass) film 8 and filling a part of the trench 7 with a resist, the exposed AsSG film 8 is removed by etching using a wet process such as HF. Thereafter, the resist 9 is stripped.

Next, as shown in FIG. 2 (f), a 3 nm thick SiO ₂ film 10 for preventing As diffusion is formed by a CVD method using TEOS, and then heat-treated at 1050 ° C. for about 30 minutes. Then, an n ⁺ -type impurity diffusion layer 11 as a buried plate electrode is formed.

Next, as shown in FIG. 2 (g), the AsSG film 8 and the SiO ₂ film 10 are etched and removed by a wet process such as HF to have a thickness of 8 n as a capacitor insulating film.
An m-th silicon nitride film 12 is formed.

Next, as shown in FIG.
After a polysilicon film containing As (As-doped polysilicon film) 13 as a storage node electrode is formed in the trench 7 by a method, the As-doped polysilicon film 13 is polished by CMP to planarize the surface. SiO
₂ After removing the films 5 and 10 by wet etching,
The As-doped polysilicon film 13 is polished again by CMP to flatten the surface.

Next, as shown in FIG. 3 (h), the As-doped polysilicon film 13 is recessed by RIE to the depth of the n ⁺ -type impurity diffusion layer 11, and the exposed silicon nitride film 12 is made of phosphoric acid or the like. After removal by wet etching, re-oxidation is performed, and then LPC using TEOS
An oxide film (color oxide film) 14 having a thickness of about 70 nm is formed by the VD method.

Next, as shown in FIG.
Is removed by RIE. At this time,
The oxide film 14 on the inner wall of the trench 7 is also etched to some extent, and the thickness of the oxide film 14 is reduced.

[0026] Then, as shown in FIG. (I), a natural oxide film on the surface of the As-doped polysilicon film 13 (not shown) is removed by HF, followed by 900 ° C., for about 3 minutes H ₂
After annealing, 900 ° C, 10T without releasing to the atmosphere
DCS (SiH ₂ C) in a reduced pressure atmosphere of about
l ₂ ), S using a gas system containing HCl and AsH ₃
As-doped polysilicon film 15 as a storage node electrode is formed inside trench 7 by i-selective CVD.
To form The removal of the natural oxide film can be performed simultaneously with the removal of the oxide film 14 outside the trench 7.

Here, since the selective CVD method is used,
Since the nucleation of Si on various insulating films is suppressed and selective growth occurs toward the substrate surface with the surface of the As-doped polysilicon film 13 as a nucleus, voids and the like are contained in the As-doped polysilicon film 15. No seams occur. Therefore,
No problems such as a rise in resistance due to voids or seams and a decrease in charge retention time occur.

The As-doped polysilicon film 15 is formed in the trench 7 without causing voids or seams.
Can be formed, so that it is not necessary to taper the upper part of the trench 7 for improving the burying property, and the problem that the improvement of the integration degree is hindered does not occur.

An H ₂ anneal performed prior to the formation of the As-doped polysilicon film 15 causes a SiO ₂ film (color oxide film) 14 formed using TEOS as a raw material.
And the formation of an oxide film on the As-doped polysilicon film 15 due to degassing from the SiO ₂ film 10 is suppressed.

Finally, as shown in FIG. 3J, the exposed oxide film 14 is removed by wet etching such as HF.
Subsequently, an As-doped polysilicon film 16 is deposited by LPCVD, and the surface thereof is planarized by CMP to complete a trench capacitor.

(Second Embodiment) FIGS. 4 and 5 are process sectional views showing a method for manufacturing a trench capacitor according to a second embodiment of the present invention. 1 to 3 are denoted by the same reference numerals as those in FIGS. 1 to 3, and detailed description will be omitted. In the present embodiment, a method will be described in which a trench capacitor can be formed in a smaller number of steps than in the first embodiment.

First, FIG. 1A to FIG. 1 of the first embodiment
Steps up to (d) are performed. Thereafter, HF processing is performed.

Next, as shown in FIG.
As is diffused into the side wall of the trench 7 by vapor phase diffusion by high temperature annealing in an H ₃ atmosphere to form an n ⁺ -type impurity diffusion layer 11 as a buried plate electrode.
An 8 nm-thick silicon nitride film 12 is deposited on the entire surface.

Next, a resist is applied to the entire surface so as to fill the inside of the trench 7, and is developed by irradiating i-line of a mercury lamp having a wavelength of 365 nm. The i-line reaches only halfway through the trench 7. As a result, as shown in FIG. 4B, a resist 9 filling from the bottom of the trench 7 to a depth in the middle thereof is formed.

Next, as shown in FIG. 4C, after removing the silicon nitride film 12 at locations not covered with the resist 9 by wet treatment with phosphoric acid or the like, the silicon nitride film 1 is removed.
2 is removed and a portion of the SiO ₂ film 17 having a thickness of 5 nm
Is formed by thermal oxidation. This thermal oxidation has the effect of removing damage in Si on the side wall of the trench 7 and improving the breakdown voltage by rounding the corner of the upper side wall of the wrench 7. Thereafter, the resist 9 is peeled off as shown in FIG.

Next, as shown in FIG.
A polycrystalline or amorphous silicon film (As-doped silicon film) containing As as a storage node electrode is formed so as to cover the side wall of the trench 7 and not completely fill the inside of the trench 7 by using the method. Is formed on the entire surface. Next, as shown in FIG. 4D, a resist 19 is applied to the entire surface so as to fill the inside of the trench 7.

Next, as shown in FIG.
9 and the As-doped silicon film 18 are receded by etching, and the resist 19 and the As-doped silicon film 18 outside the trench 7 and inside the trench 7 are formed.
Is removed. Thereafter, the resist 19 is removed.

Next, as shown in FIG. 5F, the As-doped silicon film 1 is formed by a wet process such as a dilution HF process.
The native oxide film (not shown) on the surface of No. 8 is removed.
After performing H ₂ annealing at 0 ° C. for about 3 minutes, without releasing to the atmosphere, at 900 ° C. in a reduced pressure atmosphere of about 10 Torr,
The trench 7 is formed by a selective CVD method of Si using a gas system containing CS (SiH ₂ Cl ₂ ), HCl and AsH _3.
The inside is buried with an As-doped polysilicon film 20.

Here, since the Si selective CVD method is used, nucleation of Si on various insulating films is suppressed, and As
Since selective growth occurs in the direction of the substrate surface with the surface of the doped silicon film 19 as a nucleus, no void or seam occurs in the upper region in the trench 7.

Here, as shown in FIG. 2F, a seam 21 is formed under the above-mentioned region due to the selective growth in the lateral direction with respect to the substrate surface, but this seam 21 is not exposed. Therefore, there is no problem because the exposed portion is not oxidized in the oxidation step and is formed in a lower region that is not exposed in the recess step.

Finally, the surface is flattened by CMP to complete the trench capacitor.

The present invention is not limited to the above embodiment.

For example, in the above embodiment, the selection C of Si
Although one As-doped polycrystalline silicon film is formed in the trench before performing the VD method, two or more As-doped polycrystalline silicon films may be formed in the trench. Conversely, the Si selective CVD method may be performed from the beginning without forming the As-doped polycrystalline silicon film in the trench in advance.

In the above embodiment, the As-doped polysilicon film is used as the storage node electrode, but a polysilicon film containing other impurities may be used.

In the above embodiment, the case of a trench capacitor used in a DRAM memory cell has been described. However, the present invention can be applied to a trench capacitor used in another semiconductor device.

The present invention can be applied to other than the trench of the trench capacitor. That is, the present invention is effective for the whole method of manufacturing a semiconductor device including the step of filling the inside of the groove with a film.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0048]

As described above, according to the present invention, the film can be preferentially grown from the bottom of the groove.
A method of manufacturing a semiconductor device in which a groove having a high aspect ratio can be buried without causing voids or seams can be realized.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing the first half of a method for manufacturing a trench capacitor according to a first embodiment of the present invention.

FIG. 2 is a process cross-sectional view illustrating a middle part of the method of manufacturing the trench capacitor according to the first embodiment of the present invention.

FIG. 3 is a process sectional view showing the latter half of the method for manufacturing the trench capacitor according to the first embodiment of the present invention.

FIG. 4 is a process sectional view showing the first half of a method for manufacturing a trench capacitor according to a second embodiment of the present invention;

FIG. 5 is a process sectional view showing the latter half of the method for manufacturing the trench capacitor according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view for explaining a conventional problem.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 n ^- type diffusion layer 3 oxide film 4 silicon nitride film 5 BSG film 6 photoresist pattern 7 trench 8 AsSG (As doped Silicate Glass) film 9 resist 10 SiO ₂ film 11 n ⁺ type impurity diffusion layer (buried plate electrode) 12 silicon nitride film (capacitor insulating film) 13 As doped polysilicon film (storage node electrode) 14 oxide film (color oxide film) 15 As doped polysilicon film (storage node electrode) 16 ... As doped polysilicon film 17 ... SiO ₂ film 18 ... As doped polysilicon film (storage node electrode) 19 ... resist 20 ... As doped polysilicon film 21 ... seam

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/822 (72) Inventor Ichiro Mizushima 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Pref. Toshiba Yokohama office (72 ) Inventor Shigeki Sugimoto 8 Shingsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Toshiba Yokohama office (reference) 5F038 AC05 AC10 DF05 EZ11 5F045 AA06 AB02 AB03 AB04 AB31 AB32 AB33 AB34 AB36 AC05 AC07 AC13 AD13 AE23 DB05 DC51 GH10 HA05 HA13 HA14 HA16 5F083 AD17 GA30 JA04 JA05 JA33 JA47 PR05 PR21 PR33 PR40

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device having a step of filling the inside of a groove with a film, wherein the groove has a side wall made of a material that does not form nuclei of the film by CVD, and a bottom surface formed by CVD. A method of manufacturing a semiconductor device, comprising: forming a groove made of a material for forming a nucleus of the film, and then forming the film by a selective CVD method. 2. The groove is formed in a silicon substrate, and the side wall of the groove is formed of a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or at least two of them.
A bottom surface of the groove is made of silicon, the film is a silicon film, and this silicon film is formed by a selective CVD method using a gas containing SiH ₂ Cl ₂ and HCl. Claim 1 characterized by the following:
13. The method for manufacturing a semiconductor device according to item 5. 3. The trench is a trench of a trench capacitor, and before the inside of the trench is filled with the silicon film, another portion of a polycrystalline or amorphous portion is formed from a bottom surface of the trench to a halfway depth thereof. 3. The method according to claim 2, wherein the semiconductor device is embedded with a silicon film.