JP2000243924A - Ferroelectric element - Google Patents

Ferroelectric element

Info

Publication number
JP2000243924A
JP2000243924A JP11045759A JP4575999A JP2000243924A JP 2000243924 A JP2000243924 A JP 2000243924A JP 11045759 A JP11045759 A JP 11045759A JP 4575999 A JP4575999 A JP 4575999A JP 2000243924 A JP2000243924 A JP 2000243924A
Authority
JP
Japan
Prior art keywords
ferroelectric
upper electrode
nitride
ferroelectric element
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP11045759A
Other languages
Japanese (ja)
Inventor
Masahiko Hirai
匡彦 平井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd filed Critical Asahi Chemical Industry Co Ltd
Priority to JP11045759A priority Critical patent/JP2000243924A/en
Publication of JP2000243924A publication Critical patent/JP2000243924A/en
Withdrawn legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To reduce the influence of an active hydrogen to a ferroelectric and to obtain a ferroelectric element with less machining damage by setting an upper electrode formed on the ferroelectric layer of the ferroelectric element to a conductive nitride. SOLUTION: A field oxide film 2 is formed on the surface of a substrate 1, and a lower electrode 4 is formed on it. Further, a ferroelectric film 5 is formed on the lower electrode 4. Further, a gallium nitride thin film that is a conductive nitride is formed as an upper electrode 7 by the DC sputtering method. Also, in a conductive nitride thin film used for the upper electrode 7, a conductive nitride thin film such as gallium nitride and aluminum nitride or their mixed crystals or impurities are mixed, thus extremely reducing the active characteristic function of hydrogen, thus obtaining a reliable ferroelectric element without any damage due to an active hydrogen and with a high yield.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、強誘電体素子に関
し、特に、信頼性の高い上部電極を有する強誘電体素子
の構造に係るものである。
The present invention relates to a ferroelectric device, and more particularly, to a structure of a ferroelectric device having a highly reliable upper electrode.

【0002】[0002]

【従来の技術】不揮発性メモリの一種として、最近、動
作速度が速く、書き換え回数を大きく取れる強誘電体メ
モリが登場した。これは、DRAMのキャパシタを強誘
電体キャパシタに置き換えた構造をしたもので、FRA
M(Ferroelectric Random Access Memory)として特開平
2ー113496号公報(ラムトロン・コーポレーショ
ン)等に見られる。この前記素子は、電源を遮断しても
情報が失われない不揮発性メモリであり、かつ動作がD
RAM並に高速であるため注目されている。
2. Description of the Related Art Recently, as one type of nonvolatile memory, a ferroelectric memory which has a high operation speed and can take a large number of rewrites has appeared. This is a structure in which a DRAM capacitor is replaced with a ferroelectric capacitor.
It can be found as M (Ferroelectric Random Access Memory) in JP-A-2-113496 (Ramtron Corporation) and the like. This element is a non-volatile memory in which information is not lost even when power is cut off, and operates in a D
Attention has been paid to the high speed of a RAM.

【0003】また、前記素子は、強誘電体層上の上部電
極として一般にPt(白金)電極が使われ、このPt電
極は製造プロセス過程や外部で発生する水素によって活
性化される。その結果、Pt電極が水素活性触媒として
働き、複合酸化物である強誘電体層にダメージを与える
問題が発生している。
[0003] In the device, a Pt (platinum) electrode is generally used as an upper electrode on a ferroelectric layer, and the Pt electrode is activated by hydrogen generated in the manufacturing process or outside. As a result, there is a problem that the Pt electrode functions as a hydrogen activation catalyst and damages the ferroelectric layer which is a composite oxide.

【0004】[0004]

【発明が解決しようとする課題】上記の強誘電体層が受
けるダメージとは、Pt上部電極が水素を活性化させ、
これが強誘電体を還元し、主に弱い金属−酸素結合を切
る作用が深刻であると言われている。従って、上部電極
として酸素活性のない材料を使用することにより、この
ような強誘電体が受けるダメージを劇的に減らすことが
出来ると考えられる。しかしながら、水素活性機能が無
く、酸化雰囲気アニールに耐え、ドライエッチングしや
すい電極材料を選択することは難しい。本発明は、この
ような従来の技術が有する未解決の課題を解決するべく
行われたものであり、強誘電体が受ける活性水素による
劣化問題を解決することを目的としている。
The damage to the ferroelectric layer is that the Pt upper electrode activates hydrogen,
It is said that this has a serious effect of reducing ferroelectrics and mainly breaking weak metal-oxygen bonds. Therefore, it is considered that the use of a material having no oxygen activity as the upper electrode can dramatically reduce the damage to such a ferroelectric. However, it is difficult to select an electrode material that does not have a hydrogen activation function, resists annealing in an oxidizing atmosphere, and is easily dry-etched. The present invention has been made to solve such an unsolved problem of the conventional technology, and has as its object to solve the problem of deterioration of a ferroelectric caused by active hydrogen.

【0005】[0005]

【課題を解決するための手段】本発明者は、前記課題を
解決するために上部電極として導電性窒化物が有効であ
ることを見いだし、本発明に至った。つまり、請求項1
に記載の強誘電体素子は、強誘電体層上に上部電極を有
する強誘電体素子において、前記上部電極が導電性窒化
物であることを特徴とする。また、請求項2記載の強誘
電体素子は、請求項1記載の強誘電体素子において、前
記導電性窒化物が3族金属と窒素からなる化合物、また
は該化合物に不純物を混入したものであることを特徴と
する。
Means for Solving the Problems The present inventor has found that a conductive nitride is effective as an upper electrode for solving the above-mentioned problems, and has reached the present invention. That is, claim 1
The ferroelectric element described in (1) is a ferroelectric element having an upper electrode on a ferroelectric layer, wherein the upper electrode is a conductive nitride. The ferroelectric element according to a second aspect is the ferroelectric element according to the first aspect, wherein the conductive nitride is a compound comprising a Group 3 metal and nitrogen, or an impurity mixed into the compound. It is characterized by the following.

【0006】また、請求項3記載の強誘電体素子は、請
求項1記載の強誘電素子において、前記導電性窒化物が
窒化ガリウム、または窒化アルミニウム、または窒化ガ
リウムと窒化アルミニウムの混晶、またはこれらに不純
物を混入したものであることを特徴とする。また、請求
項4記載の強誘電体素子は、請求項1記載の強誘電体素
子において、前記強誘電体層が少なくともPbTi
3、PZT(PbZrTiO 3)、PLZT(Pb
1-xLa xZr 1-yTi y 3)、Bi 2SrTa 2
9、Bi 2 -XNb XSrTa 2 9、Bi 2VO 5 ~ 6
薄膜のいずれかであることを特徴とする。
According to a third aspect of the present invention, in the ferroelectric element according to the first aspect, the conductive nitride is gallium nitride or aluminum nitride, or a mixed crystal of gallium nitride and aluminum nitride, or They are characterized by being mixed with impurities. According to a fourth aspect of the present invention, there is provided the ferroelectric element according to the first aspect, wherein the ferroelectric layer includes at least PbTi.
O 3 , PZT (PbZrTiO 3 ), PLZT (Pb
1-x La x Zr 1-y Ti y O 3 ), Bi 2 SrTa 2 O
9 , Bi 2 -X Nb X SrTa 2 O 9 , Bi 2 VO 5-6
It is a thin film.

【0007】また、請求項5記載の強誘電体素子は、請
求項1乃至請求項4のいずれかの強誘電体素子におい
て、前記強誘電体層が電界効果型トランジスタのゲート
絶縁膜として機能するか、またはゲート絶縁膜上に設け
られることを特徴とする。
According to a fifth aspect of the present invention, in the ferroelectric element according to any one of the first to fourth aspects, the ferroelectric layer functions as a gate insulating film of a field effect transistor. Or provided on a gate insulating film.

【0008】[0008]

【発明の実施の形態】強誘電体素子とは、強誘電体キャ
パシタや強誘電体キャパシタと電界効果型トランジスタ
との組み合わせ、強誘電体を電界効果型トランジスタの
ゲート絶縁層に利用したデバイス等をいう。電界効果型
トランジスタとは、半導体と絶縁体を接合した構造を持
つゲートの両側にソース、ドレインと称する導電体電極
を有するトランジスタのことで、例えば、MOS(Meta
l/Oxide/Semiconductor)−FET(Field Effect Tran
sistor)、TFT(Thin Film Transistor)などがこれ
にあたる。強誘電体とは、印加電圧を取り除いても、内
部分極が残る(残留分極)誘電体(絶縁体)のことで、
例えば、PbTiO 3、PZT(PbZrTiO 3)、
PLZT(Pb 1-xLa xZr 1-yTi y 3)、Bi
2SrTa 2 9、Bi 2-XNb XSrTa 2 9、B
2VO 5 ~ 6薄膜等を用いる。強誘電体キャパシタと
は、上記強誘電体からなる薄膜を、下部電極として例え
ば白金、イリジウム、酸化イリジウム、上部電極として
窒化ガリウム、窒化アルミニウムなどの導電性の薄膜電
極で挟み、容量(キャパシタ)としたものである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A ferroelectric element is a ferroelectric capacitor.
Pasters and ferroelectric capacitors and field-effect transistors
Combination of ferroelectrics with field-effect transistors
Refers to devices used for the gate insulating layer. Field effect type
A transistor has a structure in which a semiconductor and an insulator are joined.
Conductor electrodes called source and drain on both sides of the gate
Transistor, for example, MOS (Meta
l / Oxide / Semiconductor)-FET (Field Effect Tran)
sistor), TFT (Thin Film Transistor), etc.
Hit. A ferroelectric substance means that even if the applied voltage is removed,
Dielectric (insulator) with partial poles remaining (remanent polarization)
For example, PbTiOThree, PZT (PbZrTiOThree),
PLZT (Pb1-xLaxZr1-yTiyOThree), Bi
TwoSrTaTwoO 9, Bi2-XNbXSrTaTwoO9, B
iTwoVO5-6Use a thin film or the like. With ferroelectric capacitors
Is a thin film composed of the above ferroelectrics as a lower electrode.
Platinum, iridium, iridium oxide, upper electrode
Conductive thin film electrodes such as gallium nitride and aluminum nitride
It is sandwiched between poles to form a capacitance (capacitor).

【0009】上部電極に用いる導電性窒化物薄膜とは、
例えば窒化ガリウム、窒化アルミニウム等の導電性窒化
物薄膜または、これらの混晶、またはこれらに不純物を
混入したもので、水素の活性特性機能については、持っ
ていないか、あるいは極めて小さいものである。これら
の特徴により、活性水素によるダメージのない、信頼性
の高い強誘電体素子を得ることができる。
The conductive nitride thin film used for the upper electrode is
For example, a conductive nitride thin film such as gallium nitride or aluminum nitride, or a mixed crystal of these, or a mixture of these with impurities, has no or very small hydrogen active characteristic function. With these features, a highly reliable ferroelectric element free from damage by active hydrogen can be obtained.

【0010】[0010]

【実施例1】以下、本発明の実施例を図面に基づいて説
明する。図1に示すような強誘電体素子を作製した。基
板1には、抵抗率2Ωcmのp型Si(100)単結晶基
板を用い、表面に熱酸化法によってフィールド酸化膜2
を400nm形成させたものを用いた。この上に下部電極4
として、チタン20nm、Pt150nmをDCスパッタ法で形
成した。Ptを形成する際の基板温度は300℃とした。
さらに、この下部電極の上に強誘電体薄膜5としてPL
ZTをゾルゲル法で作製した。強誘電体の組成は、Pb
1.15、La0.03、Zr0.30、Ti0.70のものを使用し
た。5回塗布し、250nmの膜厚を得た。1回塗布毎にRT
A(急速加熱法)による600℃のアニールを30秒行い、5
回塗布後に20分の酸素中アニールを行った。さらに上部
電極7として、GaN(窒化ガリウム)薄膜をDCスパ
ッタリング法を用いて膜厚150nmを得た。このとき、タ
ーゲットには導電性の焼結GaNを用い、基板温度を30
0℃とした。これを順次ドライエッチングして、強誘電
体キャパシタを形成した後、層間絶縁膜3としてオゾン
TEOS膜を400nm形成し、コンタクトホールをあけた後、
回復アニールを酸素雰囲気中、650℃20分行った。
Embodiment 1 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. A ferroelectric device as shown in FIG. 1 was manufactured. As the substrate 1, a p-type Si (100) single crystal substrate having a resistivity of 2 Ωcm is used, and a field oxide film 2 is formed on the surface by a thermal oxidation method.
Having a thickness of 400 nm was used. On this, the lower electrode 4
As a result, titanium 20 nm and Pt 150 nm were formed by DC sputtering. The substrate temperature when forming Pt was 300 ° C.
Further, as a ferroelectric thin film 5 on the lower electrode, PL
ZT was produced by a sol-gel method. The composition of the ferroelectric is Pb
1.15, La0.03, Zr0.30, Ti0.70 were used. The coating was performed five times to obtain a film thickness of 250 nm. RT for each application
A (rapid heating method) annealing at 600 ° C for 30 seconds, 5
After the first coating, annealing was performed in oxygen for 20 minutes. Further, as the upper electrode 7, a GaN (gallium nitride) thin film having a thickness of 150 nm was obtained by using a DC sputtering method. At this time, conductive sintered GaN was used as the target, and the substrate temperature was set at 30 ° C.
The temperature was set to 0 ° C. This is sequentially dry-etched to form a ferroelectric capacitor.
After forming a TEOS film of 400nm and opening a contact hole,
Recovery annealing was performed in an oxygen atmosphere at 650 ° C. for 20 minutes.

【0011】さらに、Al配線6を形成し、これをドラ
イエッチングして加工した。Al配線は、触針により電
気特性評価できるよう、0.1mm角のパッド状になるよう
にした。最後に、窒素雰囲気中で、400℃20分のアニー
ルを行った。また、電気特性を評価するために、裏面に
基板コンタクト用金属層9を形成した。裏面を希フッ酸
処理した後、アルミニウムを真空蒸着して形成した。
Further, an Al wiring 6 was formed and processed by dry etching. The Al wiring was formed into a 0.1 mm square pad so that electrical characteristics could be evaluated with a stylus. Finally, annealing was performed at 400 ° C. for 20 minutes in a nitrogen atmosphere. Further, in order to evaluate the electric characteristics, a metal layer 9 for substrate contact was formed on the back surface. After the back surface was treated with diluted hydrofluoric acid, aluminum was formed by vacuum evaporation.

【0012】比較例として、上部電極7をPtとした以
外は実施例1と同様な比較素子も作製した。比較素子と
実施例1素子のサンプルを1%水素中(窒素にて希釈)
150℃20分アニールし、劣化の有無を印加電圧、分極強
度の関係で観察した。印加電圧、分極強度の関係の測定
を図2の模式図に示すような回路を用いて測定したとこ
ろ、図3のような結果を得た。上部電極をPtとしたも
のは、分極強度が激しく劣化しているのに対し、GaN
としたものはほとんど劣化していないことが判る。ま
た、上部電極としてGa0.9Al0.1N1を用いた場合も
同様の優位性を得た。
As a comparative example, a comparative element similar to that of Example 1 was also prepared except that the upper electrode 7 was Pt. Samples of the comparative device and the device of Example 1 were diluted in 1% hydrogen (diluted with nitrogen).
Annealing was performed at 150 ° C. for 20 minutes, and the presence or absence of deterioration was observed in relation to applied voltage and polarization intensity. When the relationship between the applied voltage and the polarization intensity was measured using a circuit as shown in the schematic diagram of FIG. 2, a result as shown in FIG. 3 was obtained. In the case where the upper electrode was made of Pt, the polarization intensity was severely deteriorated, whereas GaN was
It can be seen that the sample that had been hardly deteriorated. Similar superiority was obtained when Ga0.9Al0.1N1 was used as the upper electrode.

【0013】[0013]

【実施例2】他の実施例を以下に示す。図4に示すよう
なMFIS(Metal-Ferroelectrics-Insulator-Semicon
ductor)型素子を作製した(ただし、この場合Metal層
にあたるのは導電性窒化物層である)。基板1には、抵
抗率2Ωcmのp型Si(100)単結晶基板を用い、表
面にゲート絶縁膜8SiON絶縁膜を膜厚4nm形成し
た。このSiON膜は、窒素をイオン注入した上、酸素
雰囲気中で800℃15分アニールすることで形成する。さ
らに、この上に強誘電体薄膜5としてSBT(SrBi
2Ta 2 9)を塗布法で作製した。塗布薬液の組成
は、Sr0.80、Bi2.20、Ta2.0、のものを使用し
た。5回塗布し、400nmの膜厚を得た。1回塗布毎に酸素
中雰囲気で700℃のアニールを20行い、5回塗布後に30分
の700℃酸素中アニールを行った。
Embodiment 2 Another embodiment will be described below. MFIS (Metal-Ferroelectrics-Insulator-Semicon) as shown in FIG.
A ductor type device was produced (however, in this case, the conductive nitride layer corresponds to the Metal layer). As the substrate 1, a p-type Si (100) single crystal substrate having a resistivity of 2 Ωcm was used, and a gate insulating film 8 SiON insulating film having a thickness of 4 nm was formed on the surface. This SiON film is formed by ion implantation of nitrogen and annealing at 800 ° C. for 15 minutes in an oxygen atmosphere. Further, an SBT (SrBi) is formed thereon as a ferroelectric thin film 5.
2 Ta 2 O 9 ) was prepared by a coating method. The composition of the coating solution used was Sr0.80, Bi2.20, Ta2.0. The coating was performed five times to obtain a film thickness of 400 nm. Annealing was performed 20 times at 700 ° C. in an atmosphere of oxygen after each application, and annealing was performed in oxygen at 700 ° C. for 30 minutes after applying 5 times.

【0014】さらに上部電極7として、実施例1と同様
にGaN薄膜をDCスパッタリング法を用いて膜厚150n
mを得た。上部電極をドライエッチングして、MFIS
構造を形成した。さらに層間絶縁膜3としてオゾンTEOS
膜を400nm形成し、コンタクトホールをあけた後、回復
アニールを酸素雰囲気中、700℃20分行った。さらに、
Al配線6を形成し、これをドライエッチングして加工
した。Al配線は、触針により電気特性評価できるよ
う、0.1mm角のパッド状になるようにした。最後に、窒
素雰囲気中で、400℃20分のアニールを行った。
Further, as the upper electrode 7, a GaN thin film was formed by DC sputtering to a thickness of 150
got m. Dry etching of the upper electrode, MFIS
Structure formed. Further, as the interlayer insulating film 3, ozone TEOS
After forming a film of 400 nm and opening a contact hole, recovery annealing was performed in an oxygen atmosphere at 700 ° C. for 20 minutes. further,
An Al wiring 6 was formed and processed by dry etching. The Al wiring was formed into a 0.1 mm square pad so that electrical characteristics could be evaluated with a stylus. Finally, annealing was performed at 400 ° C. for 20 minutes in a nitrogen atmosphere.

【0015】比較例として、上部電極7をPtとした以
外は実施例2と同様な比較素子も作製した。比較素子と
実施例2素子のサンプルを1%水素中(窒素にて希釈)
150℃20分アニールし、劣化の有無を印加電圧、分極強
度の関係で観察した。印加電圧、キャパシタンスの関係
を図5の模式図に示すような回路を用いて測定したとこ
ろ、図6のような結果を得た。上部電極をPtとしたも
のは、分極強度が激しく劣化しているのに対し、GaN
としたものはほとんど劣化していないことが判る。ま
た、上部電極としてGa0.9Al0.1N1を用いた場合も
同様の優位性を得た。
As a comparative example, a comparative device similar to that of Example 2 except that the upper electrode 7 was made of Pt was also manufactured. A sample of the comparative device and the device of Example 2 were diluted with 1% hydrogen (diluted with nitrogen).
Annealing was performed at 150 ° C. for 20 minutes, and the presence or absence of deterioration was observed in relation to applied voltage and polarization intensity. When the relationship between the applied voltage and the capacitance was measured using a circuit as shown in the schematic diagram of FIG. 5, the result as shown in FIG. 6 was obtained. In the case where the upper electrode was made of Pt, the polarization intensity was severely deteriorated, whereas GaN was
It can be seen that the sample that had been hardly deteriorated. Similar superiority was obtained when Ga0.9Al0.1N1 was used as the upper electrode.

【0016】[0016]

【発明の効果】以上の説明のように、本発明によれば、
活性水素による強誘電体への影響を著しく低減すること
が出来、加工ダメージの少ない強誘電体素子を提供する
ことが出来る。また、導電性窒化物薄膜はスパッタ法な
どで容易に形成させることができる上、ドライエッチ可
能で白金やイリジウムに比較して加工が容易である。こ
のため、歩留まりが高く、信頼性の高い強誘電体素子を
実現できるなどの効果がある。
As described above, according to the present invention,
The influence of active hydrogen on the ferroelectric can be significantly reduced, and a ferroelectric element with less processing damage can be provided. In addition, the conductive nitride thin film can be easily formed by a sputtering method or the like, can be dry-etched, and is easier to process than platinum or iridium. For this reason, there are effects that a high yield and a highly reliable ferroelectric element can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】実施例1で作製した本発明の強誘電体素子の断
面を示す図である。
FIG. 1 is a diagram showing a cross section of a ferroelectric element of the present invention manufactured in Example 1.

【図2】実施例1で作製した強誘電体素子の電気特性の
測定回路を示す図である。
FIG. 2 is a diagram showing a circuit for measuring electric characteristics of the ferroelectric element manufactured in Example 1.

【図3】実施例1で作製した強誘電体素子の電気特性評
価結果を示す図である。
FIG. 3 is a view showing the results of evaluating the electric characteristics of the ferroelectric element manufactured in Example 1.

【図4】実施例2で作製した本発明の強誘電体素子の断
面を示す図である。
FIG. 4 is a diagram showing a cross section of the ferroelectric element of the present invention manufactured in Example 2.

【図5】実施例2で作製した強誘電体素子の電気特性の
測定回路を示す図である。
FIG. 5 is a diagram showing a circuit for measuring electric characteristics of the ferroelectric element manufactured in Example 2.

【図6】実施例2で作製した強誘電体素子の電気特性評
価結果を示す図である。
FIG. 6 is a diagram showing the results of evaluating the electrical characteristics of the ferroelectric element manufactured in Example 2.

【符号の説明】[Explanation of symbols]

1・・・・基板 2・・・・フィールド酸化膜 3・・・・層間絶縁膜(オゾンTEOSシリコン酸化膜) 4・・・・下部電極(Pt/Ti薄膜) 5・・・・強誘電体薄膜(PLZT) 6・・・・金属配線層(アルミニウム) 7・・・・上部電極 8・・・・ゲート絶縁膜 9・・・・基板コンタクト用金属層 10・・・金属ステージ 1 ... Substrate 2 ... Field oxide film 3 ... Interlayer insulating film (ozone TEOS silicon oxide film) 4 ... Lower electrode (Pt / Ti thin film) 5 ... Ferroelectric Thin film (PLZT) 6 Metal wiring layer (aluminum) 7 Upper electrode 8 Gate insulating film 9 Metal layer for substrate contact 10 Metal stage

フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 21/8247 29/788 29/792 Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat II (Reference) H01L 21/8247 29/788 29/792

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 強誘電体層上に上部電極を有する強誘電
体素子において、前記上部電極が導電性窒化物であるこ
とを特徴とする強誘電体素子。
1. A ferroelectric device having an upper electrode on a ferroelectric layer, wherein the upper electrode is a conductive nitride.
【請求項2】 請求項1記載の強誘電体素子において、
前記導電性窒化物が3族金属と窒素からなる化合物、ま
たは該化合物に不純物を混入したものであることを特徴
とする強誘電体素子。
2. The ferroelectric device according to claim 1, wherein
A ferroelectric element, wherein the conductive nitride is a compound comprising a Group 3 metal and nitrogen, or an impurity mixed with the compound.
【請求項3】 請求項1記載の強誘電素子において、前
記導電性窒化物が窒化ガリウム、または窒化アルミニウ
ム、または窒化ガリウムと窒化アルミニウムの混晶、ま
たはこれらに不純物を混入したものであることを特徴と
する強誘電体素子。
3. The ferroelectric element according to claim 1, wherein said conductive nitride is gallium nitride, aluminum nitride, a mixed crystal of gallium nitride and aluminum nitride, or an impurity mixed therein. Characteristic ferroelectric element.
【請求項4】 請求項1記載の強誘電体素子において、
前記強誘電体層が少なくともPbTiO 3、PZT(P
bZrTiO 3)、PLZT(Pb 1-xLa xZr 1-y
Ti y 3)、Bi 2SrTa 2 9、Bi 2-XNb X
SrTa 2 9、Bi 2VO 5 ~ 6薄膜のいずれかであ
ることを特徴とする強誘電体素子。
4. The ferroelectric device according to claim 1, wherein
The ferroelectric layer is at least PbTiOThree, PZT (P
bZrTiOThree), PLZT (Pb1-xLaxZr1-y
TiyOThree), BiTwoSrTaTwoO9, Bi2-XNbX
SrTa TwoO9, BiTwoVO5-6One of the thin films
A ferroelectric element characterized in that:
【請求項5】 請求項1乃至請求項4のいずれかの強誘
電体素子において、前記強誘電体層が電界効果型トラン
ジスタのゲート絶縁膜として機能するか、またはゲート
絶縁膜上に設けられることを特徴とする強誘電体素子。
5. The ferroelectric element according to claim 1, wherein the ferroelectric layer functions as a gate insulating film of a field effect transistor or is provided on the gate insulating film. A ferroelectric element characterized by the above-mentioned.
JP11045759A 1999-02-24 1999-02-24 Ferroelectric element Withdrawn JP2000243924A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11045759A JP2000243924A (en) 1999-02-24 1999-02-24 Ferroelectric element

Publications (1)

Publication Number Publication Date
JP2000243924A true JP2000243924A (en) 2000-09-08

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090108294A1 (en) * 2007-10-30 2009-04-30 International Business Machines Corporation Scalable high-k dielectric gate stack

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090108294A1 (en) * 2007-10-30 2009-04-30 International Business Machines Corporation Scalable high-k dielectric gate stack

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