JP2000242570A - Serial data controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability between a microcomputer and a device by detecting whether or not serial data transferred from a CPU has an error and transmitting only error-free data to the device. SOLUTION: An error detecting circuit 10 detects whether or not the serial data transferred from the CPU has an error and transmits only error-free data to the device. A command analysis block 11 of the error detecting circuit 10 decides whether serial data sent out of the microcomputer 20 is normal data or a data clear command. A comparator 13 compares data in fetch buffers 11a to 11c and a resending request block 14 sends a request to resend serial data to the microcomputer 20 when the compared data are discrepant. An STB decision block 12 decides which device the serial data are communicated to. A clock generating circuit 15 generates a clock needed for serial communication to be set to a device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to error detection of three-wire serial communication between a CPU and a device, and more particularly, to a CPU.
The present invention relates to a serial data control device that prevents transmission of erroneous serial data by incorporating an error detection circuit between the serial data control device and a device.

[0002]

2. Description of the Related Art As shown in FIG. 5, a conventional general circuit configuration in the same hardware employs a form in which serial data is set by using a 3-wire serial communication directly from a microcomputer. However, in this setting method, even if the serial data differs from the serial data sent by the microcomputer due to noise (high voltage), temperature change, etc. on the connection set from the microcomputer to the device, There was a problem that was set.

There is also a problem that the register itself set in the device is destroyed by a special environment (high voltage, temperature change). If something goes wrong, it can even be fatal, and some mistakes are unacceptable. For precision equipment used in such an environment, improvement of reliability is indispensable. There is also a method of performing error discrimination by adding a parity bit.However, since this method is the processing of data itself, even if it happens to be incorrect data depending on the environment in which precision equipment is handled, it is possible to obtain normal data. It is conceivable that this may also occur when treated as

Therefore, as a method for avoiding the case where the serial data is set by mistake or the register of the device itself has been changed, there is a method of transmitting the serial data from the microcomputer to each device at regular intervals.

[0005]

In the above-described conventional error detection circuit, since the circuit is assembled in the same hardware as the device, there is a risk that the register will be destroyed. There is also a method of transmitting serial data to each device at regular intervals, but there is a possibility that incorrect serial data may be set, so that there is a problem that reliability is lacking.
Furthermore, since it is necessary to perform serial communication with all devices, there is a problem that the microcomputer is occupied by the serial communication processing. SUMMARY OF THE INVENTION An object of the present invention is to provide a serial data controller for solving the above-mentioned conventional disadvantages and improving reliability between a microcomputer and a device.

[0006]

In order to solve the above-mentioned problems, a serial data control device according to the first invention of the present application comprises:
A serial data control device for three-wire serial communication between a CPU and a device includes an error detection circuit that detects presence or absence of an error in serial data transferred from the CPU and transmits only error-free data to the device. The serial data control device according to the first aspect of the present invention having the above-described configuration has an error detection circuit incorporated between the CPU and the device, so that the data transferred from the CPU may be garbled due to noise or the like, or a temperature change may occur. Can detect register data corruption by
Can improve the reliability of serial data transmitted to each device.

Further, in the serial data control device according to the second invention of the present application, the error detection circuit may include a command analysis block for identifying what kind of command the transferred serial data is. A STB discriminator that stores the serial data matched by the comparator and transfers it to a designated device, and retransmits the mismatched serial data verified by the comparator. It is characterized by comprising a retransmission request block for performing an instruction. According to the second invention of the present application having the above configuration, the command analysis block discriminates the instruction content from the CPU, and the comparator eliminates erroneous data due to transmission from the CPU.
The reliability of the serial data can be improved by transmitting the data to each device by the determination block and by having the CPU transfer the correct data for the erroneous data again by the retransmission request block. Further, output of erroneous data that is garbled due to a change in device voltage or a change in temperature can be avoided. Further, the transmission of serial data for managing each device performed by the CPU can be performed by the error detection circuit, so that the load on the CPU can be reduced.

Further, in the serial data control device according to the third invention of the present application, the command analysis block may determine whether the transferred serial data is a command for setting a device, a command for clearing a capture buffer, or a command for all devices. It is characterized in that it is a reset command. According to the third invention of the present application having the above-described configuration, the serial data transmitted from the CPU is transmitted to each device by determining the type of the instruction transferred from the CPU by the command analysis block. Since the analysis can be performed, erroneous serial data is not transmitted.

In the serial data control device according to a fourth aspect of the present invention, the comparator captures the serial data transferred from the CPU into a plurality of buffers, compares the captured serial data with each other, and determines whether the serial data is Only when they match, the data is stored in the storage buffer. According to the fourth invention of the present application having the above-described configuration, by comparing transferred serial data with each other, erroneous serial data can be eliminated and only correct serial data can be transmitted, so that reliable serial data can be transmitted. Can be sent.

The serial data control device according to a fifth aspect of the present invention is characterized in that the STB determination block determines a device to which serial data is transferred. The STB determination block of the fifth invention of the present application having the above configuration can transmit serial data without occupying the CPU by transmitting the serial data transferred from the CPU to each designated device. Can be reduced.

In a sixth aspect of the invention, the serial data control device is characterized in that the retransmission request block requests the CPU again for serial data that does not match by the comparator. The retransmission request block according to the sixth aspect of the present invention having the above configuration can transmit erroneous serial data as normal serial data by transferring again only the serial data not matched by the comparator from the CPU. Can be improved in reliability.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. As shown in FIG. 1, a serial data control device according to the present invention detects an error in serial data transferred from a CPU (not shown) and detects an error in the serial data. The error detection circuit 10 includes a command analysis block 11 for determining whether the serial data transmitted from the microcomputer 20 is a normal data or a data clear command, and a command analysis block 11 for capturing and storing the normal data from the microcomputer 20. A retransmission request for sending a serial data retransmission request to the microcomputer 20 when the data compared by the comparators 13 for comparing the data in the capture buffers 11a to 11c and the data in the capture buffer is not the same. Block 14 and the serial data to which device STB determination block 12 for determining communication, storage buffers 12a to 12d for holding data of each device when data compared by the comparator is the same, and one data from a plurality of storage buffers. And a clock generating circuit 15 for generating a clock necessary for serial communication for setting the device.

FIG. 2 is a block diagram for performing three-wire serial transfer in which the error detection circuit 10 of the present invention is inserted between the microcomputer 20 and each of the devices 70 to 90. The microcomputer 20 and the error detection circuit 10 include a serial clock line 30, a serial data line 40, and a strobe line 50 to each of the devices 70 to 90.
The serial clock line 30, the serial data line 40, and the strobe line 50 are used to transfer data from the microcomputer 20 to the error detection circuit 10, and the retransmission request line 60
0 indicates that the error detection circuit 10
0 to notify a retransmission request. The connection between the error detection circuit 10 and each of the devices 70 to 90 uses a serial clock line 30, a serial data line 40, and a strobe line 50. This is for each device 70-90
When viewed from the side, the configuration is the same as that controlled directly by the microcomputer 20, and conventional devices 70 to 90 can be used.

Next, the operation of this embodiment will be described in detail with reference to FIG. 1, FIG. 2 and FIG. FIG. 2 and FIG.
FIG. 3 is a block diagram of a three-wire serial transfer including an error detection circuit 10, in which the way of writing the block diagram is changed. CLO output from microcomputer 20
CK30, DATA40, and STB50 are input to the error detection circuit 10, and the error detection circuit 10 notifies the microcomputer 20 of a retransmission request via the retransmission request line 60. In addition, the notification to each of the devices 70 to 90 is performed by the CLOCK 30 and DA output from the error detection circuit 10.
This is performed by TA40 and STB50. As a result, the input to each of the devices 70 to 90 can be controlled in the same manner as in the state where the input is directly connected to the microcomputer 20.

Next, the internal operation of the error detection circuit 10 will be described in detail with reference to FIG. FIG. 1 shows a configuration of the error detection circuit 10. The command analysis block 11 determines which of the three types of serial data output from the microcomputer 20 is the setting data for the device, the clearing of the capture buffer, and the resetting of all devices. (All settings are set to devices except for clearing the capture buffer and resetting all devices.) When the command analysis block 11 determines that the device is set, the first serial data from the microcomputer 20 is: Capture buffer 11
a, and the second serial data is stored in the capture buffer 11b. The comparator 13 compares the capture buffer 11a with the capture buffer 11b, and stores the serial data of the device determined by the STB determination block 12 from the storage buffer 12a to the storage buffer 12d only when they are the same. The serial data is stored in any of.

Thereafter, serial transfer is performed to each of the devices 70 to 90 using the serial data stored in the storage buffer. When the comparator 13 determines that the serial data in the buffer for capture is different, it notifies the retransmission request block 14 and requests the microcomputer 20 to retransmit the serial data. When retransmission is requested and the third serial data is transferred to the command analysis block 11, the capture buffer 1
1c. The comparator 13 compares the capture buffer 11c and the capture buffer 11a, or the capture buffer 11c and the capture buffer 11b, adopts the same serial data, and stores the serial data in the storage buffer. Then, serial transfer is performed for each device.

If it is determined in the command analysis block 11 that all devices are to be reset, serial communication is performed to all devices using the serial data stored in the storage buffer. At this time, serial communication from the microcomputer 20 to the error detection circuit 10 is performed only once, and the serial communication is performed once.
Since all devices can be set, the burden of serial transfer processing occupying the microcomputer is reduced.

Next, a second embodiment will be described.
FIG. 4 is a block diagram of a three-wire serial transfer in which the error detection circuit 10 is incorporated for each device. This is used when there is a transfer of serial data including address designation in the same strobe, and the error detection circuit 10 shown in FIG.
When the command is analyzed by the command analysis block 11, the address and the data are distinguished and compared for each address, and the serial data is stored in the storage buffer. As a result, even if the strobe is the same, the serial data is stored for each address. Therefore, when the device is reset, the serial data stored in the storage buffer is sequentially transmitted to the device, so that the microcomputer 20 Then, serial transfer to all addresses of the device can be performed by one serial transfer to the error detection circuit 10. It should be noted that the present invention is not limited to the above-described embodiment, and can be implemented with various modifications within the scope of the technical idea.

[0019]

As described above, according to the serial data control device of the present invention, when the serial data from the microcomputer is garbled due to noise or the like, the garbled data is prevented from being set in the device. can do. The reason is that by inserting the error detection circuit of the present invention between the microcomputer and the device, the correctness of the serial data transmitted from the CPU is determined, and the device is not set unless it is determined that there is no error. Because it is. If the serial data is determined to be incorrect, the error detection circuit notifies the microcomputer of a retransmission request, compares the serial data with new serial data, and does not set the device unless it is determined that there is no error. It is. The second effect is that, when resetting all devices from the microcomputer, the microcomputer sends a reset command from the CPU to the error detection circuit instead of sending out all data. The setting of all devices is executed by the error detection circuit. The reason is that since the serial data of each device is stored in the storage buffer in the error detection circuit, the serial data of the storage buffer can be transmitted from the error detection circuit in order of each device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an error detection circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 3 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 4 is a block diagram showing an entire configuration of a second embodiment of the present invention.

FIG. 5 is a diagram showing the overall configuration of a conventional device.

[Explanation of symbols]

 Reference Signs List 10 Error detection circuit 11 Command analysis block 11a Capture buffer 11b Capture buffer 11c Capture buffer 12 STB determination block 12a Storage buffer 12b Storage buffer 12c Storage buffer 12d Storage buffer 13 Comparator 15 Clock generation circuit 16 Transmission Buffer 20 CPU 30 CLOCK 40 DATA 50 STB 60 device 70 device 80 device 90 device

Claims (6)

[Claims] 1. A serial data control device for performing three-wire serial data communication between a CPU and a device, wherein the serial data transferred from the CPU detects the presence or absence of an error and transmits only data without an error to the device. A serial data control device comprising an error detection circuit. 2. An error detection circuit comprising: a command analysis block for identifying what kind of instruction the transferred serial data is; and a comparator which receives the transferred serial data into a plurality of buffers and compares matching conditions. And an STB discriminating block for storing the serial data matched by the comparator and transferring the serial data to a designated device, and a retransmission request block for issuing a retransmission command for the non-matching serial data verified by the comparator. The serial data control device according to claim 1. 3. The command analysis block according to claim 1, wherein the transferred serial data is a command for setting a device, a command for clearing a buffer for capturing, or a command for resetting all devices. 1 or Claim 2
2. The serial data control device according to item 1. 4. The comparator captures serial data transferred from a CPU into a plurality of buffers, compares the captured serial data with each other, and stores the serial data in a storage buffer only when the serial data matches. The serial data control device according to claim 1 or 2, wherein: 5. The serial data control device according to claim 1, wherein the STB determination block determines a device to which serial data is transferred. 6. The serial data control device according to claim 1, wherein the retransmission request block requests the CPU again for serial data that does not match by the comparator.