JP2000236361A - Radio equipment and signal degradation compensating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a configuration capable of suppressing the factor of signal degradation such as inter-symbol interference caused by the frequency characteristics of a transmitter and the others. SOLUTION: A base band data signal is mapped by an I and Q signal generating circuit 101 and inputted to a band limit filter 102. On the other hand, a signal resulting from branching the transmission output of the transmitter or a signal received from the side of reception is demodulated by a demodulating circuit 105 and inter-symbol interference quantity is measured or information included in the received signal is acquired by an inter-symbol interface quantity detecting circuit 106. On the basis of the inter-symbol interference quantity, the tap coefficient of the band limit filter 102 is corrected and the band limit filter 102 is driven. Thus, a signal outputted from the band limit filter 102 is formed so as to compensate the inter-symbol interference. This formed signal is processed by a modulating circuit 103 and a high frequency processing circuit 104 and sent out as transmission signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio apparatus and a signal deterioration compensation method in radio communication.

[0002]

2. Description of the Related Art In digital communication, a radio apparatus with higher transmission speed, lower power, longer communication distance, and less signal deterioration is required. There is a demand for a highly accurate circuit configuration. In particular, when wireless communication with a wide band is performed, it is desired to reduce intersymbol interference since deterioration greatly affects due to in-band deviation. In addition, when miniaturization, low power consumption, and light weight of the receiver are required for mobile communication,
Since the functions on the receiving side are reduced, an equalizing function cannot be provided. Therefore, the transmission side is required to have particularly high modulation accuracy, and it is effective to provide a configuration for correcting a modulation error. The method of providing a configuration for correcting the modulation error is also effective when performing fixed multiplex communication as broadband communication.

FIG. 19 is a block diagram showing a configuration example of a conventional digital radio transmission apparatus. Baseband data generated by a transmission data signal generation circuit (not shown) is input to an I and Q signal generation circuit 1301.
The I and Q signal generation circuit 1301 separates, for example, the odd-numbered symbols and the even-numbered symbols of the baseband data and sends them as I and Q signals (performs mapping). . The I and Q signals sent from the I and Q signal generation circuit 1301 are input to a band limiting filter (roll-off filter) 1302, and after a signal band is limited, a modulation circuit (such as a mixer)
1303. The signal modulated by the modulation circuit 1303 is supplied to a signal synthesis circuit (hybrid circuit) 13.
04 and superimposed on the local carrier. At this time, the phases of the carrier on which the I signal is superimposed and the carrier on which the Q signal is superimposed are shifted by 90 °, and the signals in the phase-shifted state are multiplexed with each other. The multiplexed signal has been converted from a baseband band to an RF band, and then processed in a high frequency processing circuit (such as an amplifier) 1305. In the high frequency processing circuit 1305, the high frequency component of the carrier of the input signal is removed or the AGC (Automatic
Gain control) is performed, and the processed signal is output as a transmission signal. A baseband clock synchronized with the baseband data signal is input to the transmission data synchronization clock 1306, and the I and Q signal generation circuits 1301
A clock signal synchronized with transmission data for performing processing for extracting an I signal and a Q signal from a baseband signal is input. Local signal generation circuit 1307
Generates a carrier for wirelessly transmitting an I signal and a Q signal. The orthogonal signal generation circuit 1308 outputs the carrier wave input from the local signal generation circuit 1307 as it is, and uses the carrier wave for the I signal. Further, the quadrature signal generation circuit 1308 rotates the phase of the carrier input from the local signal generation circuit 1307 by 90 ° and inputs the carrier to the modulation circuit 1303 as a Q signal carrier.

[0004] In the above-mentioned conventional digital transmitter, only the band-limiting filter 1302 has a band-limiting function (also used for a digital type and an LSI type), and a modulation circuit 1303 and a hybrid circuit 1304 are used. With respect to the frequency characteristics (gain, loss) of the local signal and the frequency amplitude deviation of the local signal of the local signal generation circuit 1307 and the orthogonal signal generation circuit 1308, there is no correction circuit.
The frequency characteristics are designed to be as flat as possible. However, actually, since the frequency characteristics are not flat, waveform deterioration or the like always occurs.

FIG. 20 is a diagram schematically showing what band characteristics the signal is processed in the circuit of FIG. First, a baseband signal is processed into an I signal and a Q signal by an I and Q signal generation circuit. The frequency vs. gain relationship diagram shown in FIG. 3 shows the frequency characteristics of the constituent circuits shown above the graph. The signal band is within the range surrounded by the dotted line in the graph, and it is shown that the frequency characteristics of the I and Q signal generation circuits are not completely flat in the signal band.

[0006] The I and Q signals generated by the I and Q signal generation circuits are frequency-limited by band-limiting filters. As shown below, the frequency characteristic of the band-limiting filter is a low-frequency limiting filter having a roll-off characteristic, and the frequency characteristic of the signal band is almost flat, but is still slightly distorted. In. Further, the signal output from the band limiting filter is input to a modulation circuit and a hybrid circuit. Here, the baseband signal is converted from the baseband band to the RF band. However, since the frequency characteristics of the modulation circuit and the hybrid circuit are also not completely flat in the signal band, the signal is distorted. Further, the signals output from the modulation circuit and the hybrid circuit are processed in the high-frequency processing circuit, and the frequency characteristics of the high-frequency processing circuit are not flat in the signal band as shown below.

As described above, a signal deteriorates by passing through a circuit having a non-flat frequency characteristic. After transmission, the signal deteriorates not only in the antenna but also in the transmitter. turn into. Such signal degradation causes intersymbol interference,
This causes deterioration of reception characteristics.

FIG. 21 is a diagram for explaining the deviation of the orthogonality. FIG. 7A shows a case where there is no deviation in orthogonality. That is, when an I signal and a Q signal are put on a carrier wave,
This is a case where the phases of the I-phase and Q-phase carrier waves generated on the transmission side have a correct 90 ° difference. When an I signal and a Q signal are placed on such a carrier and transmitted, the receiving side reproduces the I phase and the Q phase carriers and returns the I signal and the Q signal to the baseband signal. Since it is at an ideal position on the -Q plane, there is no occurrence of phase shift or deterioration of the amplitude of the signal point.

On the other hand, FIG. 1B shows a case where orthogonal displacement occurs. For example, if the phase difference between the I-phase and Q-phase carrier waves generated on the transmitting side is 90
If it is not °, considering the case where the I signal and the Q signal are returned to the baseband signal with the carrier having the phase difference of 90 ° correctly on the receiving side, the transmitting side carrier seen from the receiving side is the same. It looks as shown on the I axis and Q ′ axis in FIG. Since the signal is thus arranged in a coordinate system that is distorted when viewed from the receiving side, if the receiving side correctly extracts the signal using a carrier having a phase difference of 90 °, the carrier on the receiving side will be: As shown on the I axis and the Q axis, the position of the signal point is deformed into a rhombus or a parallelogram. Therefore, when a signal is reproduced based on the I-axis and the Q-axis, a phase shift and a deterioration in amplitude occur.

[0010]

As described above,
Conventionally, the frequency characteristics of the components of the transmitter are based on the assumption that they have an ideal flat curve, the coefficients of the filter are determined, so if any of the frequency characteristics of the components is not flat, Intersymbol interference will occur. In addition, there is an error in the filter itself,
It is a deterioration factor by itself. The higher the transmission speed, the more noticeable the deterioration, and the greater the effect on the communication system.

As described with reference to FIG. 20, the frequency characteristic of each main signal system is shown in FIG. There are I, Q signal generation circuits, modulation circuits,
Both high-frequency processing circuits are not flat. Further, since the band limiting filter does not have the ideal characteristic, the amplitude is distorted as the total characteristic.

Further, since a carrier is separately generated on the transmitting side and the receiving side and conversion between the baseband signal and the RF signal is performed, if the orthogonality of the carrier is shifted on the transmitting side, the receiving side receives the signal. The resulting signal will have amplitude degradation and phase shift.

It is an object of the present invention to provide a configuration for suppressing a cause of signal deterioration such as intersymbol interference caused by frequency characteristics of a transmitter and the like.

[0014]

According to the present invention, there is provided a radio apparatus for filtering a variable baseband signal for limiting the band of a mapped baseband signal, and a transmitting section for modulating and transmitting a signal transmitted through the filter section. And compensating for the deterioration of the signal transmitted from the transmitting means by specifying the amount of deterioration of the signal transmitted from the transmitting means and changing the filter characteristic of the filter means based on the specified amount of deterioration. And compensating means.

According to the signal deterioration compensating method of the present invention, (a) providing a filter having a variable filter characteristic; and (b)
(C) modulating and transmitting the signal transmitted through the filter; and (d) deteriorating the signal transmitted from the step (b). And compensating for the deterioration of the signal transmitted from the transmitting means by changing the filter characteristic of the filter based on the specified deterioration amount.

According to the present invention, a signal to be transmitted is branched before being actually transmitted, demodulated in the apparatus, and deterioration due to intersymbol interference is measured. Then, the characteristic of a filter provided in the transmitter is changed according to the measurement result of the intersymbol interference, and the passed signal is shaped so as to compensate for signal deterioration. Thereby, the degradation of the signal to be transmitted is compensated by passing through the filter. That is, it is possible to compensate for a phenomenon that the signal deteriorates as the signal passes through a device in the transmitter, and transmit an optimal signal.

Also, if information (such as the amount of intersymbol interference) relating to the deterioration of the signal transmitted by itself is received as a signal from the receiving side, the characteristics of the filter are varied based on this information, and the signal to be transmitted is shaped. In wireless communication, it is also possible to compensate for the deterioration of a signal in the antenna.

In this way, when the signal to be transmitted is received on the receiving side, the degradation is compensated, and the quality of communication can be improved.

[0019]

DETAILED DESCRIPTION OF THE INVENTION In a digital communication system,
Intersymbol interference directly leads to deterioration of line quality, and it is necessary to minimize the deterioration. In the case of a communication system with a wide band, correction may be performed by an equalizer or the like in the receiver. I was holding it down.

In the embodiment of the present invention, regarding deterioration at the time of transmission, at the time of start-up of a transmitting device, an inter-symbol interference amount of a transmission signal output by the transmitting device is extracted by an external reference measuring instrument, and the bandwidth is determined based on the result. Feedback is provided as a correction value to the limiting filter to offset the deterioration factor of the transmission system. Digital FI as a band limiting filter in equipment
An R filter (Finite Impulse Response filter) is adopted, a filter coefficient holding unit having a constant value for the coefficient, a correction value holding unit that can be arbitrarily changed externally, and an addition mechanism for combining the correction value with the filter coefficient. Have. Alternatively, a filter coefficient can be determined only by an arbitrary coefficient set value holding mechanism, and a characteristic of a filter capable of removing interference can be easily obtained. Further, the distortion on the phase plane of the transmission signal is obtained and the value is fed back to correct the orthogonality of the local signal at the time of generating I and Q.

Further, in order to obtain initial values, a reference clock used for generating transmitter I and Q signals and a local signal for modulation are externally output through a phase adjustment mechanism, and are externally hard-wired to an external reference measuring instrument. , And the data reproduction is performed, thereby enabling the extraction of the interference amount excluding the error of the receiving system. When calculating the correction coefficient based on the interference amount extraction result,
After integrating the interference amount of each signal, correcting the I and Q detection phases and correcting the opening point of the eye pattern with the reference measuring device on the receiving side, averaging is performed to further absorb the phase error of the transmitting carrier. Then, a mechanism for passing data to the transmitter is provided so as to cancel the remaining error, and the correction value of the filter is used, so that the amplitude error can be accurately corrected.

FIGS. 1 to 5 are principle diagrams of a low intersymbol interference radio apparatus according to the present invention. FIG. 1 is a diagram showing the principle configuration of the interference reduction device of the present invention. As shown in FIG. 1, the baseband data signal is input to an I / Q signal generation circuit 101, where the baseband data signal is subjected to I / Q signal generation processing.
2 limits the band to a frequency band suitable for transmission. This signal is up-converted by the modulation circuit 103, and is subjected to necessary gain, out-of-band limitation, and power control by the high-frequency processing circuit 104, and then transmitted. Demodulation circuit 10
At 5, after receiving the transmission signal of this device, the clock, L
An O signal (a local signal: a periodic wave oscillated by a local oscillator) is generated or received by hard wiring to generate an eye pattern. This signal is used to calculate a symbol point error by an intersymbol interference amount detection circuit 106, and based on the calculation result, performs feedback to the band limiting filter 102 for correction. The band limiting filter 102 is, for example, a digital FIR filter, and suppresses intersymbol interference by setting the maximum value portion of the next symbol waveform to a portion where the waveform of the symbol of an adjacent signal becomes zero. This is performed by appropriately adjusting the tap coefficients of the digital FIR filter, changing the frequency characteristics, and controlling the signal waveform output from the filter.

The low intersymbol interference radio transmitting apparatus of the present invention is shown in FIG.
As shown in (1), after demodulating the transmission signal by the demodulation circuit, the inter-symbol interference is detected, and the band-limiting filter is controlled so as to cancel the value. Is operated so as to cancel the intersymbol interference by changing the filter characteristics so as to correct.

FIG. 2 is a diagram showing the principle configuration of the orthogonality correction device of the present invention. As shown in FIG. 2, the baseband data signal is input to the I and Q signal generation circuit 101,
After the signal and the Q signal are generated, the band limiting filter 102
Is limited. Then, the band-limited signal is input to the modulation circuit 103 and modulated to a high frequency. The local signal for the modulation circuit 103 is provided by a local signal generation circuit 202. The local signal can have an arbitrary frequency by the local signal generation circuit 202. The LO signal (local signal) is converted by the orthogonal signal generation / correction circuit 201 into two signals having a 90 ° phase difference. At this time, based on the eye pattern obtained from the demodulation circuit 105 as a correction signal, the phase quadrature correction value generation circuit 203 generates a quadrature error signal for correcting the deviation of the quadrature as described in FIG. I do. Further, the phase correction value processing circuit 204 generates data for canceling the rotation error direction,
Send to.

As shown in FIG. 2, the orthogonality correcting apparatus of the present invention is provided with a circuit for detecting and judging an eye pattern in order to detect the phase orthogonality in the demodulation circuit. The rotation direction is calculated, a correction value for canceling the value is generated, and the correction value is given to a phase correction circuit on the transmission side to rotate the phase of the orthogonal I or Q local signal to improve the orthogonality. Do.

FIG. 3 is a block diagram showing the principle of the band limiting correction mechanism according to the present invention. As shown in FIG. 3, in order to determine the filter characteristics of the FIR digital filter 301, a coefficient is given to each tap of the FIR digital filter 301. This coefficient is a value obtained by theory, and is held in the filter tap coefficient holding circuit 303. Further, a value for correcting the coefficient is held in the filter tap coefficient correction value holding circuit 304, and the filter tap coefficient calculation circuit 302
In, an operation for correcting the theoretical value is performed. The value to which the correction value has been given to the theoretical value is given as a coefficient of each tap of the FIR digital filter 301 to perform band limitation. The correction value of the tap coefficient is calculated by a calculation circuit (not shown).

The band limiting correction mechanism of the present invention, as shown in FIG. 3, comprises a band limiting filter composed of an FIR type digital filter, so that the filter coefficient can be set arbitrarily and the value obtained by theoretically determining the value Then, by calculating a correction value, a desired filter characteristic is provided, the value is retained, and the filter is used as a filter for canceling the analog error of the main signal system on the transmission side.

FIG. 4 is a block diagram showing the principle of the automatic phase adjustment mechanism of the present invention for the I and Q balance tables. As shown in FIG. 4, the automatic phase adjustment circuit rotates the phase of the baseband clock (hard-wired or reproduced clock) by the clock phase adjustment mechanism 404, and shifts the I and Q axis projection phases in each rotation phase to the I and Q axis projection amplitudes. Determined by the detection balance determination circuit 406, the adjustment count value (phase rotation value)
-Store the phase of the baseband clock and the opening degree of the eye pattern of the detected signal in the I / Q balance value tabulating circuit 402. The best value for adjustment is calculated based on the stored value, and the holding circuit 403 compares the values in the table (comparison of the opening degree of the eye pattern obtained with respect to the phase of the different baseband clock) to open the eye pattern. The baseband phase having a large degree is selectively held. The baseband clock phase is forcibly rotated by the phase rotation value setting circuit 401. The data from the I and Q axis projection amplitude detection and balance determination circuits 406 are generated by the orthogonality detection correction value generation circuit 405 to indicate the magnitude of the orthogonality shift, and based on this data, the phase of the baseband clock is inverted. A rotation correction value is generated, and a LO part of a transmission system (not shown)
Is fed back to. This value is sent to the convergence determination / phase rotation amount instruction circuit 407. In the convergence determination, a phase rotation command is output to the LO phase adjustment circuit 408 so that the aperture of the eye pattern is maximized based on the data of the I / Q axis projection amplitude detection / balance determination circuit 406 and the orthogonality data. When the value is saturated (at the time when the value falls within the set range), it is determined that the value has converged, and a storage instruction is issued to the adjustment count value (phase rotation value) -I, Q balance value tabulating circuit 402, Further, it transmits the phase convergence information to the transmitting side.

FIG. 4 shows the automatic phase adjusting mechanism of the present invention.
As shown in, of the input baseband clock and local signal, the baseband clock is forcibly rotated in phase and over 360 degrees, a good point of the I and Q signals is detected in each phase, The baseband clock phase at this time should be detected and held. The stored data is tabulated so that the optimum phase can be extracted. At the time of adjustment, the local side forms a loop, performs feedback so as to obtain an optimum value, and performs phase rotation by a phase adjustment circuit so that the opening point of the eye pattern is maximized. When the phase reaches the optimum value, a command is sent to the intersymbol interference control circuit to start calculation of the amount of interference, assuming that the phase has converged.

FIG. 5 is a diagram showing the principle of the amplitude-based interference detecting mechanism according to the present invention. As shown in FIG. 5, the intersymbol interference amount detection mechanism delays the signal amplitude value, which is the detection result of the I and Q axis projection amplitude detection circuits 501, by the intersymbol interference amount detection circuit 504, obtains a correlation, and inter-symbols at each delay. Detect interference. The value obtained by integrating the intersymbol interference amount for each tap by the tap integration circuit 505 and averaging the value is converted by the convergence determination correction value conversion circuit 506 into a correction that cancels the interference amount. The transform coefficients are arbitrarily determined by the system, or a loop is formed, and training is performed until convergence. The inter-symbol interference amount detection circuit 504 has a baseband clock having an appropriate phase from the clock timing adjustment circuit 502 and a baseband clock adjustment convergence from the inter-symbol interference amount acquisition timing generation circuit 503.
The LO phase convergence result is input, and the acquisition timing is given.

In the intersymbol interference detection mechanism of the present invention, as shown in FIG. 5, the amount of interference is calculated by using a delay unit and a correlator to calculate the difference between the signal before and after a certain symbol and optimizing the average of the difference. A result obtained by calculating an error from the value is used as a correction value from which an error caused by an unexpected factor has been removed. In the determination of the initial value of the intersymbol interference amount, it is determined as the interference value when the variation of the average result becomes equal to or less than the set value. This interference value is converted so as to have a fixed ratio to a value obtained by normalizing the coefficient used in the filter on the transmission side, and is output after the correction direction is changed to a positive direction.

FIG. 6 and FIG. 7 are block diagrams showing the configuration of the low intersymbol interference radio apparatus according to the embodiment of the present invention. FIG.
As shown in (1), the baseband data signal is input to the I and Q signal generation circuit 601 and subjected to processing such as mapping (the processing for generating the I signal and Q signal described above) and then output. The I and Q signals are applied to the FIR digital filter 602,
603 band limitation. Although the filter characteristics vary depending on the system, cosine roll-off characteristics are often used. The filter characteristics are such that ideal filter characteristics can be obtained as basic characteristics. For this reason, tap coefficients for realizing ideal filter characteristics are held in the filter coefficient holding circuit 611. I and Q output from FIR digital filters 602 and 603
The signal is input to modulation circuits 604 and 605. In the modulation circuits 604 and 605, the local periodic wave generated in the local signal generation circuit 613 is transformed into the orthogonal signal generation circuit 61.
4 and two phase waves converted into signals having a phase difference of 90 ° by the phase rotation circuit 616, respectively.
Side and Q side modulation signals are obtained. Phase rotation circuit 61
In step 6, the phase is rotated according to the value of the phase correction value calculation circuit 615 to correct the phase shift. These I and Q signals are combined by the hybrid circuit 606 and sent as a modulated wave having phase and amplitude information (or frequency information) to the high-frequency processing circuit 607 and converted into an output that can be transmitted by the antenna. . By the way, the analog-to-digital conversion is to be performed at any position that is optimal in terms of the system configuration.

As a correction circuit for suppressing the intersymbol interference, there are provided a phase rotation correction circuit and a filter coefficient correction circuit. The phase correction value calculation circuit 615 inputs the correction signal as a phase correction value. The rotation error information from the ideal symbol point is accumulated and a function as a loop filter is provided, and the phase difference of 90 degrees between the I-phase carrier and the Q-phase carrier is maintained at an appropriate value. The filter coefficient receives a coefficient correction value for each tap in the filter tap coefficient correction value holding circuit 612, and calculates a filter tap coefficient (filter tap coefficient stored in the filter tap coefficient holding circuit 610) obtained as a theoretical value. Is performed in the filter tap coefficient correction calculation circuits 609 and 610.
Since each correction coefficient converges with each other, a holding instruction is generated by the correction value holding timing generation circuit 617 using the intersymbol interference convergence result and the phase determination convergence result, and each correction value is held / fixed. Alternatively, it is updated periodically. This switching is performed by the system setting, and differs depending on the configuration that requires real-time properties and the case where the setting of the correction value is held as the initial value.

In the low intersymbol interference radio transmission apparatus of the present embodiment, a correction value is calculated for a value for which a filter coefficient has been theoretically obtained by configuring a band limiting filter using an FIR digital filter. Set by
The filter characteristic is changed so as to correct the amplitude deviation of the modulation circuit and the high-frequency processing circuit, and the value is held to be used as a filter for canceling the analog error of the main signal system on the transmission side. Further, with respect to the orthogonality of the local signal at the time of performing the modulation, a phase rotation circuit is provided on one side, and a fine phase rotation is caused by this circuit, thereby improving the orthogonality on the I side and the Q side. These correction values can be switched in real time as well as holding the values by system settings.
In this case, a correction value is generated using error data from the receiving system, and the correction is constantly performed while updating this value. The received data is extracted from the opposing receiver or acquired by providing a correction receiver in the own station.

In this embodiment, in a radio device, deterioration due to intersymbol interference due to transmission-side band limitation is compensated for by changing the characteristics of the filter, and the phase plane of the transmission signal is compensated for by orthogonality compensation of the local signal. The symbol point at is closer to the ideal point. This also improves the modulation accuracy.

This is particularly effective when a flat frequency characteristic cannot be obtained in a system having a wide band.
Further, by using the FIR digital filter, the configuration becomes stable and easy to control, and the calculation of the correction amount based on the value obtained by theory becomes easy. When a correction value is provided as an initial value in a system, the receiving function can be eliminated in the device, and the cost and size can be reduced. By performing averaging when detecting intersymbol interference, measurement errors due to local signal fluctuations and noise can be removed, and a stable value can be obtained.

Further, a baseband clock and a local phase required for measurement can be automatically set, so that the initial value can be obtained at high speed and without adjustment, and an active correction operation can be performed by having a receiver. Further, by providing the opposite receiver with the same function, it is possible to compensate for the permanent deterioration in the antenna on the transmission side.

FIG. 7 is a block diagram showing details of the interference amount measuring circuit. The interference amount measurement circuit shown in FIG. 11 provides the low inter-symbol interference radio apparatus of FIG. 6 with a phase orthogonality correction value, a phase convergence determination result, a filter tap correction coefficient, and an inter-symbol interference convergence determination result.

Depending on the system configuration, the configuration shown in the figure is either provided inside the wireless device to perform real-time correction, or used as an initial value training test device (fixed correction value) when connected externally to the wireless device. Used for In order to input a transmission signal and obtain phase information and amplitude information, a baseband clock and a local signal used for transmission are input by hard wiring, and detection and demodulation are performed.
In order to automatically adjust the baseband clock and the local signal, first, the baseband clock is phased into a phase shifter 701.
, And mechanically rotates the phase using the value set by the phase rotation value setting circuit 704. The phase rotation value is generated by a coarse adjustment counter A702 and a fine adjustment counter B7.
03. First, the phase rotation of the baseband clock is roughly adjusted to 3 using the counter value from the counter A.
Perform 60 degrees. At each set angle of the phase of the baseband clock, the phase of the local signal is performed by the phase shifter 709, and the I and Q balance values for each phase (each adjustment step) of the phase shifter 709 are obtained by the I and Q amplitude balance determination circuit 710. Then, a comparison table is created by the rough adjustment count value-I, Q balance value table conversion unit 706, and the best point is obtained by the coarse adjustment best value calculation circuit 708.

The I-axis projection amplitude detection circuit 712 and the Q-axis projection amplitude detection circuit 713 determine whether the received transmission signal, the signal obtained by shifting the phase of the local signal as the reproduction carrier, and the signal obtained by shifting the phase of the baseband clock are output. , And multiply the received transmission signal by the I-phase and Q-phase local signals, respectively, perform baseband signal extraction processing using a baseband clock, and obtain the I signal and the Q signal by the processing, respectively. This is a circuit that outputs a signal value. The I and Q amplitude balance determination circuit 710 converts the signal values of the I and Q signals obtained by the I-axis projection amplitude detection circuit 712 and the Q-axis projection amplitude detection circuit 713 into a plurality of symbols for one baseband clock phase. Minute output.

The coarse adjustment count value-I, Q balance value tabulation unit 706 calculates the count value of the counter A indicating the phase shift amount of each of the baseband clocks shifted by the phase shifter 701 and the baseband clock. The signal values of the I signal and the Q signal in the case of the phase corresponding to the count value are stored in association with each other.

Then, the rough adjustment best value calculation and holding circuit 7
08 is a readout of the signal values of the I signal and the Q signal from the table stored in the coarse adjustment count value-I and Q balance value table generation unit 706, and the I signal when the baseband clock is at a certain phase. And the value of the Q signal are collected, and when the signal value is around the ideal signal value, a large weight is added. The signal value is added. It is obtained and held as the coarse adjustment count value at the best time.
Since the phase shifter 701 changes the phase of the baseband clock based on the count value from the counter A,
By knowing the count value, the optimum phase of the baseband clock can be known.

The optimum baseband clock phase obtained in this manner is stored in the counter A best value holding /
It is held in the count control circuit 715. In the counter B, the middle point is provided by the counter B middle point holding / count control circuit 714 until the coarse adjustment is completed.
Using the counter B 703, the same processing as in the case of the coarse adjustment is performed, and the count value for fine adjustment -I, Q balance value tabulation 705, the best value calculation circuit for fine adjustment 707, the midpoint holding / count control for the counter B are performed. Circuit 714 is used to select the best point of the baseband clock phase. The baseband clock has a structure in which no feedback is applied. However, the local signal is subjected to convergence determination through the I and Q amplitude balance determination circuits 710 based on information extracted by the I-axis projection amplitude detection 712 and the Q-axis projection amplitude detection 713. The / phase rotation amount instructing section 711 acquires the signal values of the I signal and the Q signal for each phase of the local signal. Then, as performed by the rough adjustment best value calculation and holding circuit 708, the signal values for a plurality of symbols in each phase are added with weights that maximize the area around the ideal point, and the largest conversion result is obtained. In addition to holding the phase value, the phase shifter 709 is instructed so that the phase of the local signal becomes the phase. During the phase adjustment of the local signal, there is no phase change of the baseband clock. As described above, from the amplitude distributions of the I signal and the Q signal, the convergence determination / phase rotation amount instructing section 711 determines the I signal and the Q signal.
Feedback is applied to the phase shifter 709 so as to minimize the difference in signal amplitude balance. Note that the local signal phase difference (I, Q orthogonality) accuracy at the output of the phase shifter 709 is sufficiently higher than the orthogonal signal generation circuit for transmission.

The I / Q amplitude balance determination circuit 710
The signal value from the axis projection amplitude detection circuit 712 and the signal value from the Q axis projection amplitude detection circuit 713 are input to the representation-specific data division unit 720 as they are. Representation-specific data division unit 720
Calculates a signal point from the signal value of the I signal and the signal value of the Q signal.
-Classify each quadrant in the Q plane. Then, the signal values of the first and third quadrants and the signal values of the second and fourth quadrants are input to the I and Q absolute value calculation circuits 721 and 722, respectively. The absolute values of these signal values are calculated by I and Q absolute value calculating circuits 721, 7
22. This is because, as can be understood from FIG. 21, when the phase difference of the carrier is shifted from 90 °, the signal point of the first quadrant, the signal point of the third quadrant, and the signal point of the second quadrant Since the signal point and the signal point of the fourth quadrant have the same behavior, the processing is performed collectively as described above.
At this point, the amplitude information is processed with the required resolution. I and Q absolute value calculation circuit 721,
The output of 722 is compared in magnitude by an amplitude comparison circuit 723 and input to a quadrature correction value generation circuit 724. The orthogonal correction value generation circuit 724 outputs rotation direction data of the orthogonal correction value according to the comparison result of the amplitude comparison circuit 723. This is because if the phase difference between the I-phase and Q-phase carrier waves is shifted by more than 90 °, the inclination of the I-axis and the Q-axis on the transmitting side will not be a right angle, and a corresponding shift in the signal point will occur. By examining the deviation of the signal points, it is possible to calculate the gradient between the I axis and the Q axis, that is, the phase difference between the I-phase and Q-phase carrier waves. Based on this calculation result, a correction value of the phase difference between the I phase and the Q phase is output. It should be noted that the I and Q balance values and the orthogonal correction value are equal to or less than a certain value (or changes in the rotation direction within a certain period are equal).
When, the convergence determination / phase rotation amount instruction circuit 711 considers that the determination for correction has converged, and outputs convergence information. After convergence is established on both the local side and the baseband side, the measurement of intersymbol interference is performed.

The amplitude information from the I-axis projection amplitude detection circuit 712 and the Q-axis projection amplitude detection circuit 713 is used by an intersymbol interference detection circuit 716 to calculate the amount of interference in each code using a one-symbol delay unit and a correlator, respectively. I do. This result is temporally integrated (averaged) for each tap in the tap-by-tap integration circuit 717, and the result is sent to the convergence determination circuit 718 after removing errors due to other factors. In the convergence determination, when the amount of variation becomes equal to or less than the set amount of variation, it is considered that the integration has converged, and convergence information is output. Further, the interference amount data of each tap at that time is sent to the correction value conversion circuit 719, where it is converted into a correction value of each tap coefficient that cancels this interference, and is sent out as a filter tap correction coefficient.
The generation of the correction value is determined based on items required for the system, such as the size, direction, and degree of correction of the filter tap coefficient.

The circuit shown in the figure receives a baseband clock and a local signal via hard wired in order to detect a transmission signal when detecting intersymbol interference. Of these two signals, the baseband clock is forcibly rotated in phase and over 360 degrees, good points of the I and Q signals are detected in each phase, and the baseband clock phase at this time is detected. Make sure you can keep it. The stored data is tabulated so that the optimum phase can be extracted. Further, in order to increase the extraction speed, the number of angle divisions is made to converge stepwise using a rough circuit and a minute circuit. At the time of adjustment, the local side forms a loop and performs feedback so that the phase of the local signal becomes the optimum value while performing the detection processing of the optimum phase of the baseband clock. Rotation by the phase shifter. The calculation of the amount of interference is started when the signal drawn in using the hard wired becomes the optimum value. The amount of interference is determined by using a signal before and after a certain symbol by a delay unit and a correlator.
The error between each symbol is calculated and obtained. The number of times of performing the averaging process is set according to the system according to the system (when the process is performed in real time or when the initial value is obtained). In addition, in the initial value acquisition, when the variation of the average result becomes equal to or less than the set value, it is determined as the interference value. This value is converted so as to have a fixed ratio to a value obtained by normalizing the tap coefficient used in the filter on the transmission side, and is output after the correction direction is changed to a positive direction. In the case of interference information from the opposing receiver, the baseband clock and the local signal are reproduced from the received wave, but the automation of the phase optimization of the baseband clock is realized by the configuration used in the present embodiment.

In this way, when detecting interference,
By performing averaging, measurement errors due to fluctuations and noise of local signals can be removed, and a stable value can be obtained. Furthermore, the baseband clock and the local phase required for the measurement can be automatically set, the speed at the time of obtaining the initial value can be increased, and no adjustment can be performed, and the active correction operation by having the receiver can be performed. Further, by providing the opposite receiver with the same function, it is possible to compensate for the permanent deterioration in the antenna on the transmission side.

FIG. 8 is a block diagram showing a detailed configuration of the intersymbol interference detection circuit and each tap integration circuit of FIG. The received data of the I signal and the Q signal from the I-axis projection amplitude detection circuit 712 and the Q-axis projection amplitude detection circuit 713 in FIG.
It is input to a delay unit 730 that delays by the sampling clock. The delay unit 730 delays the received signal by one symbol and inputs the delayed signal to the correlator 734. Correlator 734
Then, at a certain sampling point of a signal delayed by one symbol, the signal is correlated with signals before and after a specific signal, and is output for each delay amount. The timing at which the delay unit 730 delays the signal and the timing at which the correlator 734 calculates the correlation are performed based on a clock signal given from the sampling clock 701. Correlator 734 is
The correlation value obtained for each delay amount is output as a correction amount for each tap. FIG. 2 shows a correction coefficient calculation block configuration for one of the taps. Since the configuration for other taps is the same, illustration and description are omitted.

The correction data is held by the holding circuit 735. This is to hold the previous calculated value of the correction value for one tap, compare it with the calculated correction value for the next tap, and determine whether the correction of the tap coefficient has converged. belongs to. The correction value of the tap coefficient calculated this time is input to the comparison circuit 736, and is compared with the previous correction value stored in the holding circuit 735 and the comparison circuit 7.
Compared at 36. The comparison result is input to the forward protection circuit 737. The forward protection circuit 737 obtains the comparison result several times, and outputs the comparison result when the same result is obtained a plurality of times, assuming that the result is surely obtained.

From the front protection circuit 737, the integration circuit 73
8, an integration start signal is input. Upon receiving the integration start signal, the integration circuit 738 integrates the input correlation value (interference value) with respect to the tap for a relatively long time, and divides the integrated value by the integrated time to obtain an average. The output indicates the amount of interference that has been averaged over a relatively long period of time. At the same time, the correlation value is also input to the moving average circuit 739. The moving average circuit 739 is an integration circuit having a small time constant, and performs integration and averaging of a plurality of interference amount signals in a shorter time than the integration circuit 738. The integration / average result from the moving average circuit 739 and the integration / average result from the integration circuit 738 are input to the determination circuit 740. The determination circuit 740 compares the two, and if they match, it means that the fluctuation of the correlation value obtained by the moving average circuit 739 has converged to the output value of the integration circuit 738, and the interference amount having high reliability is determined. Assuming that it has been obtained, the control section 737 commands the forward protection circuit 737 to stop (reset) the output of the integration start signal, and inputs an integration stop signal to the integration circuit 738. The output value from the integration circuit 738 is also input to the switching unit 741. The output value of the determination circuit 740 is input to the switching unit 741 and also to the AND circuit 744. The output from the determination circuit 740 is 1
This indicates that the interference amount is determined (converged) for one tap, and by taking the AND with the intersymbol interference convergence signal from the other taps, the measurement of the interference amount is performed for all taps. A signal indicating whether or not the convergence has occurred is output from the AND circuit.

The switching section 741 initially outputs the correlation value (correction data) input from the correlator 734,
The moving average circuit 742 performs integration and averaging, inputs the result to the coefficient conversion circuit 743, and outputs the result as a filter tap correction coefficient. However, although this is integrated and averaged, but before the inter-symbol interference convergence determination, the correction coefficient includes an influence such as noise and is not a definitive correction coefficient. When the intersymbol interference convergence signal is input from the determination circuit 740,
The switching unit 741 inputs the signal from the integration circuit 738 to the moving average circuit 742. The moving average circuit 742 receives the correction data after the convergence of the intersymbol interference from the correction data that has been input in the form of a pulse. The moving average circuit 742 averages and outputs the correction data, and removes fluctuations and the like due to an unexpected cause.
And outputs the same value as the correction data input from, and is converted into a filter tap correction coefficient in a coefficient conversion circuit 743. This correction coefficient is output as a final filter tap correction coefficient since the measurement of the intersymbol interference amount has converged.

FIG. 9 is a block diagram showing another detailed configuration of the intersymbol interference detection circuit and each tap integration circuit of FIG. In the figure, the configuration after the correlator 734 is shown. The same components as those in FIG. 8 are denoted by the same reference numerals.

In the figure, the output from the correlator 734 is
The correlation value for each tap is obtained by directly calculating the filter tap correction coefficient in the circuit 7-A, excluding the center tap, and performing intersymbol interference convergence determination only for the center tap. At other than the center tap, the correlation value output from the correlator 734 is input to the integration circuit 738 and also to the switching unit 741. The integration start and integration end signals are input to the integration circuit 738 based on the interference convergence determination result provided for the center tap processing, and the integration and averaging processing is started and ended based on the signals. Integration circuit 7
While the integration and averaging process is performed by the 38, the correlator 734
Are input to the moving average circuit 742 via the switching unit 741. In the moving average circuit 742,
The average of the correlation values sequentially input is taken, and the coefficient conversion circuit 7
Input to 43. The coefficient conversion circuit 743 converts the input correlation value into a filter tap correction coefficient and outputs the result. Since this correction coefficient is before the convergence of the interference, it is not the final filter tap correction coefficient. When the integration stop signal is input to the integration circuit 738, the final correlation value stored in the integration circuit 738 is input to the moving average circuit 742 via the switching unit 741. The moving average circuit 742 inputs the correlation value from the integration circuit 738 to the coefficient conversion circuit 743. And
The coefficient conversion circuit 743 outputs a filter tap correction coefficient based on the correlation value from the integration circuit 738. Since this correction coefficient has been subjected to interference convergence determination, it is output as a final filter tap correction coefficient.

The processing of the correlation value for the center tap is as follows:
Since the processing is performed by the same configuration as the configuration shown in FIG. 8,
Description is omitted. Since the intersymbol interference convergence signal is determined using only the convergence of the correlation value of the center tap, A
No ND circuit is provided, and only the convergence of the inter-symbol interference measurement of the center tap is taken as the convergence of all the filter tap correction coefficients.

FIG. 10 is a diagram showing a schematic configuration of a system for correcting waveform deterioration in an antenna in addition to waveform deterioration due to a cause in a transmitter. For example, FIG. 2 shows a case where the terminal 8 is a small terminal such as a mobile phone and communicates with the base station 9. The transmitter 13 of the terminal 8 generates transmission data in the transmission data generation unit 25, multiplexes the transmission data by the transmission data multiplexer 24, maps the signal to, for example, an I signal and a Q signal 23, and modulates the data by the modulator 22. To the base station 9. At this time, the transmission signal includes data relating to the intersymbol interference of the signal received from the base station 9. A transmission signal from terminal 8 is received by base station 9. In the base station 9, the receiver 1
The first demodulator 17 demodulates the transmitted signal, and the data extraction mechanism 16 extracts data relating to intersymbol interference and the like. The data extraction mechanism 16 obtains the data deterioration status and the like, inputs this information to the data holder 15 of the transmitter 10, and, based on the deterioration information, via the waveform deterioration correction circuit 14,
The signal is corrected and transmitted to the terminal 8. In the terminal 8, the signal from the base station 9 is received by the receiver 12. In the receiver 12, the signal is demodulated by the demodulator 19. Demodulator 19
Demodulates a received signal based on signals from the carrier recovery unit 20 and the clock recovery unit 21. The error data extracting unit 18 obtains signal deterioration information from the demodulated data signal, sends the deterioration information to the transmitter 13, and transmits the signal deterioration information to the base station 9. In this way, the terminal 8 detects the deterioration of the signal from the base station 9 and sends the deterioration information to the base station 9. The base station 9 combines the transmitted degradation information with the degradation information generated within itself,
The correction circuit 14 corrects the filter tap coefficient and corrects the waveform deterioration, thereby forming a large feedback path including the base station 9 and the terminal 8 and reducing the signal deterioration of the signal transmitted from the base station 9 in the antenna. Can be corrected in consideration of

FIG. 11 is a diagram showing another embodiment of the configuration corresponding to FIG. 7, which is used for the correction circuit in the configuration of FIG. The same components as those in FIG. 7 are denoted by the same reference numerals.

The configuration shown in the figure is a circuit configuration provided on the transmitter side. Therefore, since the phase shifter 701 that adjusts the phase of the baseband clock uses the clock used for transmission itself, the phase adjuster 701 skips the step of coarse adjustment and finely adjusts the phase of the baseband clock from the beginning. . The counter B 703 is a clock for fine adjustment of the phase,
The clock output from the counter B 703 is used when the phase rotation value is determined by the phase rotation value setting circuit 704. The determined phase rotation value is input to the phase shifter 701 and used to rotate the phase of the baseband clock. The phase-rotated baseband clock is I
It is input to the axis projection amplitude detection circuit 712 and the Q axis projection amplitude detection circuit 713. A local signal is also input, and the local signal is input to the phase shifter 709, the I / Q amplitude balance determination circuit 710,
The phase of the local signal is adjusted to an optimum value by the feedback control configured by the convergence determination / phase rotation amount instruction unit 711. I-axis projection amplitude detection circuit 712 and Q
The signal values obtained by the axis projection amplitude detection circuit 713 are I, Q
After being input to the representation-specific data division unit 720 via the amplitude balance determination circuit 710 and performing the processing described with reference to FIG. 7, the I and Q absolute value calculation circuits 721 and 722 perform I-Q
The absolute value of the signal point on the Q plane is determined, and the amplitude comparison circuit 723 calculates the amplitude of the signal point in the first and third quadrants,
A comparison is made with the amplitude of the signal point in the second and fourth quadrants. This result is input to the holding unit 1203. Also, the holding unit 1203 includes the representation rotation timing generation unit 1
The representation rotation timing signal from 201 is input. The holding unit 1203 rotates the quadrature (rotates the I-axis and the Q-axis as a whole) according to the held amplitude comparison result according to the quadrant rotation timing signal to generate respective I signal components and Q signal components. It is input to the amplitude comparison circuit 1204. This is because when a signal from the transmitting side is received, the carrier is reproduced. However, it is not possible to determine whether the reproduced carrier has been used as the I-phase or the Q-phase on the transmitting side. Rotating the present, swapping the settings of the recovered carrier between the I and Q phases,
This is to determine what happens to the amplitudes of the I signal and the Q signal. The result of comparing the I signal and the Q signal obtained by the symbol rotation with the amplitude comparison circuit 1204 is as follows.
At 24, it is used to generate an orthogonal correction value. The quadrature correction value is output as a phase quadrature correction value. The orthogonal correction value is input to the convergence determination / phase rotation amount instruction unit 711. The convergence determination / phase rotation amount instructing section 711 has a 90-degree rotation instructing section 1 based on the symbolic rotation timing signal generated by the symbolic rotation timing generating section 1201.
A quadrature rotation instruction signal generated by the quadrature 202 is input, and the I signal and the Q signal are most optimal when the quadrant is at any angle.
Whether the amplitude of the signal is reproduced (whether the orthogonality correction value is reduced) is acquired, and the optimal phase of the local signal is determined. If it is determined that the phase adjustment has converged, a phase convergence determination signal is output. The output of the convergence determination / phase rotation amount instruction unit 711 is also input to the counter B. The counter B outputs a signal for shifting the phase of the next baseband clock when the phase adjustment of the local signal converges and the intersymbol interference is detected.

Fine adjustment count value -I, Q balance value tabulation section 705, fine adjustment best value calculation and holding circuit 70
7 and counter B middle point holding / count control circuit 714
About the coarse adjustment mechanism shown in FIG.
16, integration circuit 717 for each tap, convergence determination circuit 71
8 and the correction value conversion circuit 19 perform the same operation as the corresponding configuration in FIG.

FIG. 12 is a block diagram of an embodiment in which the interference measuring circuit is provided in the transmitting section. In addition,
6, the same components as those in FIGS. 6 and 7 are denoted by the same reference numerals.

The transmission signal is branched by a coupler 801 and passed to detection / I and Q amplitude detection circuits 712 and 713. The baseband clock and the local signal are supplied to the phase rotation mechanism 8.
02, the phase is sent to the local signal phase adjustment unit 804 to adjust the phase. The phase rotation mechanism 802 shows a circuit equivalent to the counter A 702, the counter B 703, the phase shifter 701, and the phase rotation value setting circuit 704 of FIG. 7 as one block. These controls are performed by the adjustment best value calculation and holding / phase adjustment control circuit 805.
Details of the adjustment best value calculation and holding / phase adjustment control circuit 805 will be described later. As for the orthogonality of the local signal, a correction value is generated in the orthogonal correction value generation unit 803, and the phase rotation mechanism (the phase correction value processing circuit 61) of the transmission unit is used.
5. An optimum phase is obtained by the phase rotation circuit 616).
The orthogonal correction value generation unit 803 is a circuit equivalent to the configuration including the amplitude comparison unit 723 and the orthogonal correction value generation circuit 724 in FIG. The local signal phase adjuster 804 includes the phase shifter 712 and the I / Q amplitude balance determination circuit 7 shown in FIG.
This is a circuit equivalent to the circuit consisting of ten. The phase determination completion information is determined by the phase determination convergence completion instructing unit 806. The phase determination convergence completion instructing unit 806 will be described later. The intersymbol interference convergence signal and the filter tap correction coefficient are created and transmitted by the intersymbol interference detection and correction value generation unit 807. The intersymbol interference detection and correction value generation unit 807 is a circuit equivalent to a circuit including the intersymbol interference detection circuit 716, the tap-by-tap integration circuit 717, the convergence determination circuit 718, and the correction value conversion circuit 719 in FIG.

The other components having the same reference numerals as those in FIG. 6 perform the same operations as those in FIG.
Description is omitted. According to the present embodiment, the interference amount measurement circuit can be attached only during training for determining the correction value of the tap coefficient, so that the device can be downsized.
The weight can be reduced. Alternatively, dynamic correction can be performed by always providing, and deterioration due to environmental factors and aging can be compensated.

FIG. 13 is a block diagram showing a first configuration example of the adjustment best value calculation, holding, and phase adjustment control circuit in the embodiment of FIG. The I and Q signals input from the I and Q amplitude balance determination circuit 710 have their noise components averaged by an averaging circuit 1310, and
01, and are held until the next I and Q signals are input, and are also input directly to the magnitude comparison circuit 1302. The magnitude comparison circuit 1302 stores I,
The amplitude of the Q signal is compared with the amplitudes of the currently input I and Q signals. If the amplitudes of the currently input I and Q signals are larger, a phase rotation instruction signal of the local signal is output. On the other hand, the magnitude comparison circuit 1302 compares the amplitudes of the two types of input I and Q signals over a plurality of sampling values, and the amplitude becomes a constant value near the maximum value, or the variation in the signal value decreases. Table memory 1
An update signal for writing data to 308 is output.

The output from the holding section 1301 and the direct output from the averaging circuit 1310 are compared with the difference detection circuit 1304.
To calculate the degree of change in the signal value. This calculated value is input to the comparison circuit 1306.
The protection range setting value from the protection range setting circuit 1307 is input to the comparison circuit 1306. When the input calculation value is smaller than the protection range setting value, the comparison circuit 1306
The mask signal is output to the mask unit 1305 assuming that the fluctuation of the signal value is stable and reliable data is obtained. When the masking unit 1305 has received the hold signal output when the comparison circuit 1306 has the calculated difference value larger than the protection range set value, the mask unit 1305 has obtained some signal corresponding to the update signal from the size comparison circuit 1302. However, masking is performed so that a data write enable signal to the table memory 1308 is not output. Comparison circuit 1306
When the mask signal is input to the mask unit 1305, the mask unit 1305 is in a state capable of outputting the enable signal. When an update signal is input from the magnitude comparison circuit 1302 while the mask signal is being input to the mask unit 1305, a write enable signal for writing data to the table memory is output from the mask unit 1305. Mask section 130
The enable signal from No. 5 is extended by the select control unit 1322 to the table memory 1308 until data writing is completed in order to enable writing of data for generating a table as described later. Is output. Further, the selector control unit 1322 divides the absolute value of the signal point indicated by the I signal and the Q signal into an absolute value range with the precision of the number of quantization bits, and determines how many pieces of data are included in each range. In order to generate a table for registering an address, an address indicating an absolute value range is generated and input to the selector 1321 and the selector 1313.

The I-axis projection amplitude detection circuit 712 and Q in FIG.
The I and Q amplitude data input from the axis projection amplitude detection circuit 713 are input to the range identification circuit 1320. The range identification circuit 1320 determines whether the data value of the input I and Q amplitude data is within the range of the quantized data value, and sends out the data of the range including the I and Q amplitude data. (There are as many as the number of quantized data value ranges). These data are stored in a counter 1311
The number of data included in each range is counted with respect to the data input during a predetermined time. Each count value is input to the selector 1321. The selector 1321 receives the address indicating the range of the data value from the select control unit 1322, and stores the data regarding the number of data included in the corresponding range in the table memory 130.
8 is output. Accordingly, an enable signal is output from the mask unit 1305, and the enable signal extended by the select control unit 1322 is stored in the table memory 1308.
Is input to the table memory 1305.
Is written to. The enable signal from the mask unit 1305 is input to the holding unit 1301 and resets the holding unit 1301 to start the next data writing process.
The address at which data is written to the table memory 1308 is determined by the count value input to the selector 1313 from the baseband clock phase rotation counter 703 and the address value input from the select control unit 1322 indicating the range of the data value. You. For example, selector 1
Reference numeral 313 denotes a count value from the counter 703 as upper bits of an address value to be given to the table memory 1308,
The address value input from the select control unit 1322 is set as the lower bits, and an address obtained by combining these is generated and given to the table memory 1308. Also, a counter 703
Is input to the baseband clock phase 2π rotation completion determining circuit 1312. The circuit 1312 is
Based on the count value from the counter 703, it is determined whether or not the phase of the baseband clock has been rotated by 2π,
If it is determined that the rotation has been completed by 2π, the selector 13
13 is input with a switching signal. The selector 1313 is
When the switching signal is received, the output of the count value from the counter 703 is stopped, and the count value from the best clock phase calculation counter 1314 is output. That is, while the selector 1313 is outputting an address (or count value) based on the count value and the address value from the counter 703 and the select control unit 1322, data is being written to the table memory 1308,
When the phase rotation of the baseband clock reaches 2π, the data writing is stopped, and then the table memory 13 is used to detect the best baseband clock phase.
The operation for reading data from 08 starts.

The circuit 1314 includes a table memory 1308
Are sequentially output from the beginning. Further, the maximum value calculation circuit 1317 detects the output of the count value from the selector 1313 and stores the count value in the mask unit 1305 in the table memory 1.
A read enable signal 308 is output. The table memory 1308 outputs the number of data included in a certain data value range at a certain address, that is, at a certain baseband clock phase. The number of data output from the table memory 1308 is
5 is input. The multiplication circuit 1325 includes a selector 131
3, the address currently being read is received, and, for example, from the lower bit of this address, the table memory 130
The number of data input from 8 knows the value of the data value, and outputs a value obtained by multiplying the data value by the number of data. The result of the multiplication is input to the holding circuit 1315 and the comparing circuit 1316, respectively. The maximum value calculation circuit 1317 includes the holding circuit 1
The comparison result between the immediately preceding data stored in 315 and the currently read data, and the compared data value are input. The maximum value calculation circuit 1317 detects the largest of the multiplication values of the data value and the number of data from these inputs, outputs a clock best phase calculation completion signal, and outputs the maximum multiplication value from the selector 1313. The address value corresponding to the clock phase output unit 1326
Is input to The clock phase output unit 1326 extracts the higher-order bits from the address output from the selector 1313 and outputs it as a clock phase rotation instruction signal. When the calculation of the maximum value is completed, the maximum value calculation circuit 1317 outputs a hold signal to the mask unit 1305 to stop reading data from the table memory 1308.

The holding unit 1301 and the table memory 1
A clock signal of the clock 1309 is input to the counter 308, the best clock phase calculation counter 1314, and the holding circuit 1315, and each operation is performed in synchronization with the clock signal.

FIG. 14 is a block diagram showing a second configuration example of the adjustment best value calculation, holding, and phase adjustment control circuit in the embodiment of FIG. In FIG. 1, FIG.
The same components as those in 3 are denoted by the same reference numerals.

The I and Q signals input from the I and Q amplitude balance determination circuit 710 are averaged by the averaging circuit 1310 and input to the holding unit 1301, and the next I, Q
The signal is held until the Q signal is input, and is directly input to the magnitude comparison circuit 1302. Size comparison circuit 1302
Compares the amplitudes of the I and Q signals at the previous sampling point stored in the holding unit 1301 with the amplitudes of the currently input I and Q signals, and compares the amplitudes of the currently input I and Q signals. If the amplitude is larger, a local signal phase rotation instruction signal is output. On the other hand, the size comparison circuit 1
Reference numeral 302 denotes a table for comparing the amplitudes of the two types of input I and Q signals over a plurality of sampling values, and when the amplitude becomes a constant value near the maximum value or when the variation of the signal value becomes small. An update signal for writing data to the memory 1308 is output.

The output from the holding unit 1301 and the direct output from the averaging circuit 1310 are compared with the difference detection circuit 1304.
To calculate the degree of change in the signal value. This calculated value is input to the comparison circuit 1306.
The protection range setting value from the protection range setting circuit 1307 is input to the comparison circuit 1306. When the input calculation value is smaller than the protection range setting value, the comparison circuit 1306
A mask signal is output to the mask unit 1305. Mask part 1
If the comparison circuit 1306 receives the hold signal output when the calculated difference value is larger than the protection range setting value, the signal 305 is output from the magnitude comparison circuit 1302 even if any signal corresponding to the update signal is obtained. Masking is performed so that a data write enable signal to the table memory 1308 is not output. When the comparison circuit 1306 inputs the mask signal to the mask unit 1305, the mask unit 13
05 is a state in which the enable signal can be output. When an update signal is input from the magnitude comparison circuit 1302 while the mask signal is being input to the mask unit 1305, a write enable signal for writing data to the table memory is output from the mask unit 1305, and the data is output to the table memory 1308. Written.

The addition circuit 1303 includes an I-axis projection amplitude detection circuit 712 and a Q-axis projection amplitude detection circuit 713.
Weighted and added to the amplitude data of the I signal and the Q signal. Weight reference table memory 1318
Obtains the amplitude data of the I signal and the Q signal, obtains the weight coefficient corresponding to the amplitude data from the table, and outputs the weight coefficient to the multiplier 1319. The amplitude data of the I signal and the Q signal are multiplied by a weight coefficient in a multiplier 1319 and added in an addition circuit 1303. By weighting the values of the amplitude data of the I signal and the Q signal, the result of the addition in the adding circuit 1303 more clearly indicates the best baseband clock phase, and the phase adjustment of the baseband clock can be performed more accurately. Can do well. The weighting method and its concept will be described later. The holding unit 1311 applies the held data to a data input terminal of the table memory 1308. Therefore, when an enable signal is input from the mask unit 1305 to the table memory 1308, this data is written to the table memory 1305. The enable signal from the mask unit 1305 is input to the holding unit 1301 and resets the holding unit 1301 to start the next data writing process. The address at which data is written to the table memory 1308 is determined by the count value input from the baseband clock phase rotation counter 703 via the selector 1313. The count value of the counter 703 is input to the baseband clock phase 2π rotation completion determination circuit 1312. The circuit 1312 determines whether or not the phase of the baseband clock has been rotated by 2π based on the count value from the counter 703, and
When it is determined that the rotation has been completed by π, the selector 131
The switching signal is input to 3. Upon receiving the switching signal, the selector 1313 stops outputting the count value from the counter 703, and outputs the count value from the best clock phase calculation counter 1314. That is, while the count value from the counter 703 is being output from the selector 1313, data is being written to the table memory 1308, and when the phase rotation of the baseband clock becomes 2π, the data writing is stopped. Stop and then start reading data from table memory 1308 to find the best baseband clock phase.

The circuit 1314 includes a table memory 1308
Are sequentially output from the beginning. Further, the maximum value calculation circuit 1317 detects the output of the count value from the selector 1313 and stores the count value in the mask unit 1305 in the table memory 1.
A read enable signal 308 is output. As a result, the stored data is read from the table memory 1308, and the holding circuit 1315 and the comparison circuit 131
6 is input. The maximum value calculation circuit 1317 stores, in the comparison circuit 1316, the comparison result between the immediately preceding data stored in the holding circuit 1315 and the currently read data, and the compared data value. Is entered. The maximum value calculation circuit 1317 detects the largest data value among these inputs, outputs a clock best phase calculation completion signal, and outputs a clock best phase calculation completion signal from the selector 1313.
A count value corresponding to the maximum data value is output as a clock phase rotation instruction signal. When the calculation of the maximum value ends, the maximum value calculation circuit 1317
05 and outputs a hold signal to the table memory 1308
Stop reading data from.

The holding unit 1301 and the table memory 1
A clock signal of the clock 1309 is input to the counter 308, the best clock phase calculation counter 1314, and the holding circuit 1315, and each operation is performed in synchronization with the clock signal.

FIG. 15 is a diagram showing a configuration example of the phase determination convergence completion instructing unit of FIG. First, for the convergence of the phase control of the baseband clock, it is determined that the phase control of the baseband clock has converged upon receiving the clock best phase calculation completion signal output from the circuit of FIG. 13 or FIG.

The convergence judgment of the control of the phase of the local signal is as follows.
The local phase adjustment signal input to the phase shifter 709 is input to the magnitude comparison circuit 1409, and the range setting circuit 1
This is performed by comparing with a range setting value input from 408. That is, the phase adjustment of the local signal is performed as shown in FIG.
As shown in FIG. 1, control is automatically performed by a feedback system so as to always be optimal. However, the phase of the local signal is not always kept optimal, and the amount of phase adjustment changes greatly at the beginning of the control. Therefore, when the variation of the control value of the phase of the local signal falls within a predetermined range, it is determined that the phase adjustment of the local signal has converged. That is,
The magnitude comparison circuit 1409 calculates the difference between the phase adjustment value of the currently input local signal and the phase adjustment value of the immediately preceding local signal, and calculates the difference as the range setting circuit 14.
It is determined whether it is within the setting range input from step 08. If it is determined that the local signal phase adjustment value falls within the set range, it is determined that the local signal phase adjustment has converged, and the magnitude comparison circuit 1409 outputs a local convergence signal.

Although only the phase shifter 709 is shown in the figure in the figure, a feedback circuit or the like for causing the phase shifter 709 to adjust the phase of the local signal is actually connected.

The convergence of the orthogonality of the I-phase and Q-phase carrier waves is determined by acquiring a correction value from the orthogonal correction value generation circuit 724. The shift register 1405 stores the correction values sequentially input from the orthogonal correction value generation circuit 724, and stores a predetermined number of correction values.
Input to the difference circuit 1406. Average and difference circuit 1406
Then, a plurality of correction values input in parallel over a predetermined time are averaged and held. Next, shift register 1
A plurality of correction values input from 405 are further averaged, a difference from the previously held average value is calculated, and input to the range comparison circuit 1407. The range comparison circuit 1407 determines whether or not the input difference value is within a certain range. If it is determined that the difference value is within a certain range, it can be determined that the orthogonality correction value is determined to be a certain value. .

Finally, AND of the clock best phase calculation completion signal, the orthogonality correction convergence signal, and the local convergence signal
And outputs it as a convergence determination signal for all controls.
In this manner, when all of the control of the phase of the baseband clock, the control of the orthogonality of the I-phase and Q-phase carrier waves, and the control of the phase of the local signal converge, the convergence determination signal is output. I have.

FIGS. 16 and 17 are diagrams showing examples of tables used for baseband clock phase optimization. FIG. 16 shows the table memory 130 in the configuration example of FIG.
8 shows an example of a table stored in FIG. In the table of FIG. 16, for the baseband clock phase,
Probability information in each of the absolute amplitude ranges is input.
In this case, the number of data falls within the range within a certain set number of times. FIG. 18 shows the ideal amplitude as A.
21 (a) and the ideal signal point of FIG. 21 (a) projected onto each axis. This amplitude range is obtained over the quantization range of each phase and used for calculation. In other words, the number of data belonging to the absolute value range included in a certain baseband clock phase is represented by the representative value of the absolute value range (in this case, the absolute value range is the minimum range obtained by quantization. It is sufficient to set the upper limit as a representative value. However, since the maximum value range of the absolute range has no upper limit, the lower limit value of the absolute value range is used as a representative value), and this is multiplied by each baseband clock. The optimum value of the baseband clock phase can be known by obtaining the phase value for each phase value and determining which baseband clock phase value indicates the largest value.

FIG. 17 shows an example of a table stored in the table memory 1308 in the configuration example of FIG. The table of FIG. 7 is a table in which weights are applied to the amplitude range, and the calculation result is recorded as phase data of each baseband clock. As for the weighting calculation, the calculation weight of FIG. 18 is calculated for the number of data in each amplitude, and the result is fully added. As a result, the value increases as the number of points closer to the ideal point increases, and the best point of the baseband phase can be easily obtained.

When the table shown in FIG. 16 is used, since the data is processed into a table without processing, high-speed processing is possible and the configuration is simplified. On the other hand, FIG.
In the case of using the table, since the table is formed after multiplication of the weighting coefficient and the data value and addition processing over a plurality of data, the storage element can be reduced in size and the optimum value for searching for the optimum value of the baseband clock phase can be obtained. It is possible to increase the resolution. Further, post-processing is facilitated. These configurations can be combined according to the arithmetic processing.

FIG. 18 is a view for explaining the calculation method used when creating the table of FIG. The sampling point of the eye pattern is obtained by rotating the phase of the baseband clock, and its moving range corresponds to the resolution. Data is obtained at an arbitrary number of times at each sampling point, the portion corresponding to the data in the amplitude range is calculated, and the number of times of the data is counted and stored. Further, a value obtained by multiplying the number by a weighting coefficient and adding the result is stored. As shown in the right side of the figure, a large weighting coefficient is applied to the signal value near the ideal point of the eye opening. In this way, when the eye pattern of the obtained signal deviates from the ideal point, the result of multiplying the data value by the weighting factor and performing the total addition becomes small, and the phase of the baseband clock is not appropriate. You can judge that. Further, in this case, the closer the point is to the opening point of the eye pattern, the larger the value becomes, and the good point of the baseband clock phase can be easily calculated.

The present embodiment is particularly effective when a flat frequency characteristic cannot be obtained in a wide band system. In addition, the use of the FIR digital filter stabilizes the configuration and facilitates the control, and facilitates the calculation of the correction amount based on the theoretically obtained value. If the system has a correction value as an initial value, the receiving function can be deleted in the device,
Inexpensive and downsizing can be achieved. By performing averaging when detecting intersymbol interference, measurement errors due to fluctuations and noise of local signals can be removed, and a stable value can be obtained. Furthermore, the baseband clock and the local phase required for the measurement can be automatically set, the speed at the time of obtaining the initial value can be increased, and the adjustment can be performed without any adjustment. Furthermore, by having the same function in the opposing receiver, it is possible to compensate for the permanent deterioration in the antenna on the transmitting side.

In order to minimize the reception function, even in mobile communication in which an equalizer cannot be mounted, the reception sensitivity can be improved by improving the modulation accuracy on the transmission side.

[0084]

According to the present invention, in a radio apparatus, characteristics caused by inter-symbol interference due to band limitation on the transmission side can be compensated for by changing the characteristics of the filter.
Further, according to another aspect of the present invention, the symbol point on the phase plane of the transmission signal can be made closer to the ideal point by orthogonality compensation of the local signal, and the modulation accuracy can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a principle configuration of an interference reduction device of the present invention.

FIG. 2 is a diagram showing a principle configuration of the orthogonality correction device of the present invention.

FIG. 3 is a principle configuration diagram of a band limitation correction mechanism of the present invention.

FIG. 4 is a principle configuration diagram of an I / Q balance table-based automatic phase adjustment mechanism of the present invention.

FIG. 5 is a principle configuration diagram of an amplitude-based interference detection mechanism of the present invention.

FIG. 6 is a block diagram (part 1) illustrating a configuration of a low intersymbol interference radio apparatus according to an embodiment of the present invention.

FIG. 7 is a block diagram (part 2) illustrating a configuration of a low intersymbol interference radio apparatus according to an embodiment of the present invention.

8 is a block diagram illustrating a detailed configuration of an intersymbol interference detection circuit and an integration circuit for each tap in FIG. 7;

9 is a block diagram showing another detailed configuration of the intersymbol interference detection circuit and the tap-by-tap integration circuit of FIG. 7;

FIG. 10 is a diagram illustrating a schematic configuration of a system for correcting waveform deterioration in an antenna in addition to waveform deterioration due to a cause in a transmitter.

11 is a diagram showing another embodiment of the configuration corresponding to FIG. 7, which is used for the correction circuit in the configuration of FIG. 10;

FIG. 12 is a block diagram of an embodiment in which an interference amount measurement circuit is provided in a transmission unit.

13 is a block diagram showing a first configuration example of an adjustment best value calculation, holding, and phase adjustment control circuit in the embodiment of FIG. 12;

14 is a block diagram showing a second configuration example of the adjustment best value calculation, holding, and phase adjustment control circuit in the embodiment of FIG. 12;

15 is a diagram illustrating a configuration example of a phase determination convergence completion instructing unit in FIG. 12;

FIG. 16 is a diagram (part 1) illustrating an example of a table used for baseband clock phase optimization.

FIG. 17 is a diagram (part 2) illustrating an example of a table used for baseband clock phase optimization.

FIG. 18 is a diagram illustrating a calculation method used when creating the table in FIG. 17;

FIG. 19 is a block diagram illustrating a configuration example of a conventional digital wireless transmission device.

FIG. 20 is a diagram schematically showing what band characteristics the signal is processed in the circuit of FIG. 19;

FIG. 21 is a diagram illustrating a deviation of orthogonality.

[Explanation of symbols]

Reference Signs List 101 I, Q signal generation circuit 102 Band limiting filter 103 Modulation circuit 104 High frequency processing circuit 105 Demodulation circuit 106 Intersymbol interference detection circuit 201 Quadrature signal generation correction circuit 202 Local signal generation circuit 203 Phase quadrature correction value generation circuit 204 Phase correction Value processing circuit 301 FIR type digital filter 302 Filter tap coefficient operation circuit 303 Filter tap coefficient holding circuit 304 Filter tap coefficient correction value holding circuit 401 Phase rotation value setting circuit 402 Adjustment count value-I, Q balance value table circuit 403 Adjustment Best use value calculation and holding circuit 404 Clock phase adjustment circuit 405 Quadrature degree detection correction value generation circuit 406 I, Q axis projection amplitude detection, balance determination circuit 407 Convergence determination / phase rotation amount instruction circuit 408 Local (LO) phase adjustment circuit 501 I and Q axis projection amplitude detection circuit 502 Clock timing adjustment circuit 503 Intersymbol interference amount acquisition timing generation circuit 504 Intersymbol interference amount detection circuit 505 Each tap integration circuit 506 Convergence judgment correction value conversion circuit

Claims (14)

[Claims] 1. Filter means for changing a filter characteristic, which limits the band of a mapped baseband signal, transmitting means for modulating and transmitting a signal transmitted through the filter means, Compensating means for specifying a deterioration amount and changing a filter characteristic of the filter means based on the specified deterioration amount, thereby compensating for deterioration of a signal transmitted from the transmitting means. Wireless device. 2. The radio apparatus according to claim 1, wherein the modulating method of said transmitting means is quadrature modulation in which a mapped baseband signal is superimposed on an I-phase carrier and a Q-phase carrier. 3. The method according to claim 1, wherein said compensating means detects orthogonality on a phase plane of a signal transmitted from said transmitting means, and performs orthogonality compensation by operating a modulation operation of said transmitting means. The wireless device according to claim 2. 4. The radio apparatus according to claim 1, wherein said filter means is an FIR type digital filter, and can correct a filter tap coefficient to change to an arbitrary filter characteristic. 5. The compensating means stores the phase of the baseband clock and the balance value of the orthogonality in association with each other while rotating the phase of the baseband clock in order to set the filter tap coefficient. By holding and setting the phase value of the clock with the best degree balance,
The wireless device according to claim 4, wherein the degradation of the transmission signal is compensated. 6. The correction coefficient of the filter tap coefficient by averaging an error due to a phase fluctuation of a carrier of the transmission signal and extracting only an intersymbol interference amount caused by an amplitude of a baseband signal. The wireless device according to claim 4, wherein: 7. The radio apparatus according to claim 6, wherein the phase of the carrier wave is configured to converge to an optimum value by a feedback system circuit. 8. A step of providing a filter having a variable filter characteristic, a step of limiting a band of a mapped baseband signal by the filter, and a step of modulating a signal transmitted through the filter. (D) specifying the amount of deterioration of the signal transmitted from the step (b), and changing the filter characteristic of the filter based on the specified amount of deterioration, so that the transmitting means Compensating for degradation of the transmitted signal. 9. The signal degradation compensation according to claim 8, wherein the modulation method in the step (c) is quadrature modulation in which a mapped baseband signal is superimposed on an I-phase carrier and a Q-phase carrier. Method. 10. In the step (d), a quadrature on a phase plane of the signal transmitted in the step (c) is detected, and a modulation operation of the transmitting means is operated.
The method according to claim 9, wherein orthogonality compensation is performed. 11. The filter according to claim 1, wherein the filter is a FIR type digital filter, and corrects a filter tap coefficient.
The method according to claim 8, wherein the filter characteristic can be changed to an arbitrary filter characteristic. 12. In the step (d), in order to set a filter tap coefficient, the phase of the baseband clock is rotated while the phase of the baseband clock is rotated.
12. The degradation of the transmission signal by compensating orthogonality balance values and storing and setting a phase value of the clock that provides the best orthogonality balance. Signal degradation compensation method. 13. In the step (d), an error due to a phase fluctuation of a carrier of the transmission signal is averaged, and only an inter-symbol interference amount caused by an amplitude of a baseband signal is extracted to thereby reduce the filter tap coefficient. The method according to claim 11, further comprising acquiring a correction coefficient. 14. The method according to claim 13, wherein the phase of the carrier is configured to converge to an optimum value by a feedback system circuit.