JP2000235794A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device preventing destruction of an input/ output buffer caused by collision of data, even if any one of the control terminal of output control breaks down in a test performed by connecting plural semiconductor devices incorporating plural semiconductor elements where output data terminals are shaved. SOLUTION: A decoder circuit 1 generates an internal address signal of a FLASH memory chip FM based on inputted plural address signals when a signal CEB inputted from a terminal is a 'L' level. A decoder circuit 2 generates an internal address signal of a SRAM chip SM based on inputted plural address signals when a signal CEB inputted from a terminal is a 'L' level. An input/output buffer control circuit 3 controls output states of input/ output buffers OIFO-OIF15 of FLASH memory chip FM based on a signal CEfB, a signal OEB, and a signal WEB. An input/output buffer control circuit 4 controls output states of input/output buffers OISO-OIS15 of SRAM chip SM based on a signal CEsB, a signal OEB, and a signal WEB.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a function of preventing simultaneous output of data from a plurality of memories to which address terminals and data terminals are commonly wired.

[0002]

2. Description of the Related Art In recent years, with the advancement of functions of electronic devices and the portability of electronic devices, high-density mounting of semiconductor devices on mounting substrates has been required. Therefore, with the increase in the density of the mounting of the semiconductor device on the mounting substrate, as one of the semiconductor devices, a solder ball is mounted on the back surface of the substrate (FIG. 15A) on which a plurality of semiconductor chips are fixed (mounted) in a package. A BGA type semiconductor device in which bump electrodes 106 are arranged as shown in FIG. 15B is used. FIG. 15B is a cross-sectional view of the semiconductor device of FIG.
It is sectional drawing in the line A '.

[0005] In FIG. 15, reference numeral 101 denotes an SRAM chip, and a FLASH memory chip 102 is provided on the upper surface side. The vertical relationship of the overlapping may be such that the chip having the larger chip size comes to the lower part. By overlapping in this manner, the size of the semiconductor device 1 can be significantly reduced. For example, a conventional TSOP (T
(hin-Small-Out-line-Package)
30% of the mounting area when one SRAM chip and one FLASH memory are used.

Further, the SRAM chip 101 and the FLASH
The memory chip 102 is designed such that most of the bonding pads 101A and 102A in the overlapping portion have the same signal. That is, SRA
Bonding pad 101A of M chip 101 and FLA
Bonding pad 102A of SH memory chip 102
In order to optimize the pin arrangement and wiring, pads for inputting and outputting address signals and data signals are arranged so as to be substantially at the same position, and are used as control signals such as a RESET signal and a chip enable (CE) signal. The pads are arranged so that they can be connected to different pads.

Reference numeral 103 denotes a bonding wire formed of a conductor such as gold, copper, or aluminum, and electrically connects the bonding pad 102A to the bonding pad 100B on the surface of the base material 100. Reference numeral 104 denotes a bonding wire formed of a conductor such as gold, copper, or aluminum.
0 is electrically connected to the bonding pad 100A on the surface. The bonding pad 100A and the bonding pad 100B are formed by a conductor (copper or nickel plating, tin plating,
It is connected via a wiring 105 made of one of gold plating or a combination of copper and the plating in a layered manner.

Reference numeral 106 denotes a metal ball, which is electrically connected to the wiring 105, and electrically connects the wiring on the mounting board (not shown) to the wiring 105. The metal ball 106 is made of a metal material such as solder, tin alloy, or gold, or a material that can be electrically connected, such as carbon or a conductive film.
Further, the shape is not limited to a spherical shape, and may be a hemispherical shape, a cylindrical shape, or the like. The metal ball 106 is made of a material such as solder, tin alloy, and gold. Reference numeral 107 denotes a sealing resin, which protects the SRAM chip 101, the FLASH memory chip 102, the bonding wires 103, and the respective bonding pads from moisture and the like.

In the above-mentioned BGA type semiconductor device, the number of arranged bump electrodes 106 is limited due to the limitation of the chip size, and terminals of address signals and data signals of a plurality of semiconductor chips are shared. For example, SRAM (Static Randum A
ccess Memory) In the case of a stacked MCP in which the chip 101 and the FLASH memory chip 102 are stacked, as shown in FIG. 16, the data terminals and the address terminals of the SRAM chip 101 and the FLASH memory chip 102 are connected to a common bonding pad. I have.

That is, the SRAM chip 101 and the FL
The data signals DQ0 to DQ15 from the ASH memory chip 102 are connected to the bonding pads T in common.
DQ0 is output to the bonding pad TDQ15,
The address signals A0 to A22 of the RAM and the flash memory are shared with the bonding pad TA.
0 is input from the bonding pad TA22.
Further, the OEB (output enable bar) terminals of the SRAM chip 101 and the FLASH memory chip 102 are also electrically connected to the bonding pad TOEB in common.

[0009]

Normally, before a semiconductor memory device is shipped, a burn-in test is performed. This burn-in test is an acceleration test in which a high voltage is applied to the semiconductor memory device in a high temperature state, and is a test for removing an initial failure of the semiconductor memory device. Then, at the time of the burn-in test of the semiconductor memory device, a plurality of semiconductor memory devices are simultaneously operated to shorten the test time. At this time, when only one semiconductor element is sealed in the package, a test is performed by connecting the semiconductor memory devices UTD1 to UTDm in parallel as shown in FIG.

Here, the CEB terminals of the semiconductor memory devices UTD1 to UTDm are connected to the terminal T103, are fixed at "L" level, and are in a state where the internal circuit can operate. That is, the ADRS terminal (bonding pad TA0 to bonding pad TA22)
Each address of the memory can be accessed by an address signal input from the memory device, and stress is applied to all the cells sequentially or simultaneously.

The OEB terminal is connected to the terminal T104 and is fixed at "H" level, and the output is in a high impedance state. In another test mode, the quality of the semiconductor memory device can be determined by connecting each output terminal to a tester.

Here, even if the OEB terminal goes to "L" level for some reason, the output terminals TD10 to TDm of the semiconductor memory devices UTD1 to UTDm will be described.
Since n is open, each semiconductor memory device UT
D1 to each data terminal D0 to data terminal Dn of the semiconductor memory device UTDm (data terminal TD10 to data terminal TD1n,...)
.., The input / output buffers corresponding to the data terminals TDm0 to TDmn) are not destroyed.

However, in the stacked MCP type semiconductor memory device, since the data terminal and the address terminal are shared inside the package as shown in the prior art,
A control signal is supplied to a plurality of semiconductor memory devices at the same time, a plurality of semiconductor memory devices are connected in parallel, and a plurality of semiconductor memory devices are simultaneously operated to remove an initial defective semiconductor memory device. The following problems occur.

As shown in FIG. 18, when simultaneously operating (reading) a plurality of semiconductor memory devices UTD1 to UTDm during a burn-in test, the OEB terminals of all the semiconductor memory devices are set to "H" level, and The operation test is performed by setting the CEfB terminal and the CEsB terminal of all the semiconductor memory devices to the “L” level. Also,
The data terminals TDD1,0 to TDD1,15,... Of the semiconductor memory devices UTD1 to UTDm, respectively.
..., data terminals TDDm, 0 to data terminals TDDm, 15 (bonding pads TDQ0 to bonding pads T, respectively)
DQ15) are open.

At this time, the shared address terminal (bonding pad) TA0 to the address terminal TA22
(FIG. 15), an address signal input via the terminal ADRS is supplied to the SRAM chip 101 and the FLASH memory chip 102. And the SRAM chip 1
01 and the FLASH memory chip 102 perform an operation of reading data of a memory cell designated by an internal address decoder.

However, each of the SRAM chip 101 and the FLASH memory chip 102 in the semiconductor memory devices UTD1 to UTDm has the OEB terminal at "H".
, The data output operation is not performed on the data terminals TDD1,0 to TDD1,15,..., The data terminals TDDm, 0 to TDDm, 15. Therefore, the data output signals of the SRAM chip 101 and the FLASH memory chip 102 do not collide, and the input / output buffer of the semiconductor memory device is not destroyed.

However, in this stack MCP, one of the plurality of semiconductor memory devices fails, the leakage between the OEB terminal and the ground terminal increases, or the OEB terminal and the ground terminal short-circuit. Then, the OEB terminal of this semiconductor memory device becomes “L” level, and the SRAM chip 1
01 and the FLASH memory chip 102 from the data terminals TDD1,0 to TDD1,15 (data terminal T
DD2,0 to data terminal TDD2,15, ..., data terminal T
DDm, 0 to data terminals TDDm, 15) are output with data signals DQ0 to DQ15, respectively. Then, at this time, when one outputs a data output signal of “H” level and the other outputs a data output signal of “L” level, an excessive current flows to both input / output buffers, and the SRAM chip 101 and the FLASH The input / output buffer of the memory chip 102 is destroyed.

At the same time as the OEB terminal of the semiconductor memory device goes to "L" level, the OEB terminal of another semiconductor memory device connected in parallel with this semiconductor memory device also goes to "L" level. SRAM chip 101 and FLASH memory chip 10 in semiconductor memory device
2 are data terminals TDD1,0 to data terminal TD in the same manner as in the destroyed semiconductor memory device described above.
D1,15 (data terminal TDD2,0 to data terminal TDD2,1
5,..., Data terminal TDDm, 0 to data terminal TDDm, 1
The data signals DQ0 to DQ15 are output to 5) to destroy each input / output buffer.

For this reason, the above-described conventional stack MCP
When the OEB terminal of any one of the plurality of semiconductor storage devices connected in parallel at the time of the burn-in test is broken down to the “L” level, There is a problem that the input / output buffer of the storage device is destroyed.

The present invention has been made under such a background. In a test performed by connecting a plurality of semiconductor devices each including a plurality of chips having a common data output terminal, any one of the other devices is used. An object of the present invention is to provide a semiconductor device in which even if a control signal terminal for performing output control of an input / output buffer for outputting data of the semiconductor device fails, the input / output buffer is not destroyed due to collision of a plurality of data due to the failure.

[0021]

According to the first aspect of the present invention,
In a semiconductor device, in a semiconductor device in which a plurality of semiconductor elements sharing an output terminal are sealed in one package, a first semiconductor element, a first output buffer provided in the first semiconductor element, A second semiconductor device having a second output buffer connected to a common output terminal,
First output buffer control means for controlling an output state of the first output buffer based on a first control signal supplied to the first semiconductor element, and a second output buffer control means supplied to the second semiconductor element. And a second output buffer control means for controlling an output state of the second output buffer based on the second control signal and the first control signal.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, when the second output buffer control means enables the output of the first output buffer by the first control signal, When the second control signal is in a state of validating the second output buffer, the output state of the second output buffer is set to a high impedance state.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the first control signal controls whether or not the operation of the first semiconductor element is enabled. A first element selection signal, and a first element output signal for controlling whether or not to enable the first output buffer, wherein the second control signal is for the second semiconductor element. A second element selection signal that controls whether or not to enable the operation, and a second element output signal that controls whether to enable the second output buffer. Features.

According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the first input / output control means controls the first semiconductor device in response to the first element selection signal. When the device is enabled,
The first element output signal controls whether to enable the first output buffer, and when the second semiconductor element is enabled, the second element output signal and the first element It is characterized in that whether to enable the second output buffer is controlled by a selection signal.

According to a fifth aspect of the present invention, there is provided a semiconductor device in which a plurality of semiconductor elements sharing an output terminal are sealed in a single package. A second semiconductor element having a second output buffer connected to a common output terminal with a first output buffer provided in the element, a first control signal supplied to the first semiconductor element and First output buffer control means for controlling an output state of the first output buffer based on a second control signal supplied to a second semiconductor element; and the first control signal and the second control signal And a second output buffer control means for controlling an output state of the second output buffer based on the above.

According to a sixth aspect of the present invention, in the semiconductor device according to the fifth aspect, when the first control signal is in a state in which the output of the first output buffer is made valid, the second control signal is output. When the second output buffer is in a state of validating, and when the second control signal is in a state of validating the output of the second output buffer, the first control signal is the first output When the buffer becomes valid, the first output buffer control means sets the first output buffer to a high impedance state, and the second output buffer control means sets the output state of the second output buffer. In a high impedance state.

According to a seventh aspect of the present invention, in the semiconductor device according to the fifth aspect, when the first output buffer and the second output buffer are both in a high impedance state, the first control signal is first applied to the first output buffer. When the output of the output buffer becomes valid, the second output buffer control means may control the second output buffer even when the second control signal makes the second output buffer valid. Is kept in a high-impedance state, and conversely, if the second control signal first makes the output of the second output buffer valid, the first output buffer control means The first output buffer is kept in a high impedance state even when the control signal enables the first output buffer.

According to an eighth aspect of the present invention, in the semiconductor device according to the seventh aspect, the first output buffer and the control means are configured to control the first control signal and the second control signal and the second output buffer control means. Are respectively provided with latch circuits for storing which of the control signals (1) and (2) is in a state in which the first output buffer and the second output buffer are respectively enabled first.

According to a ninth aspect of the present invention, in the semiconductor device according to any one of the fifth to eighth aspects, the first control signal enables or disables the operation of the first semiconductor element. A first element selection signal that controls whether the first output buffer is enabled or not, and a first element output signal that controls whether the first output buffer is enabled. A second element selection signal for controlling whether or not to enable the operation of the second element, and a second element output signal for controlling whether to enable the second output buffer. Features.

According to a tenth aspect of the present invention, in the semiconductor device according to any one of the fifth to ninth aspects, the first input / output control means controls the first semiconductor device in response to the first element selection signal. When the device is enabled, the first device output signal and the second device selection signal control whether to enable the first output buffer, and the second semiconductor device is enabled. In this case, whether or not the first output buffer is enabled is controlled by the second element output signal and the first element selection signal.

[0031]

Embodiments of the present invention will be described below with reference to the drawings. <First Embodiment> FIG. 1 is a block diagram showing a configuration of a stacked MCP type semiconductor memory device (semiconductor memory devices UT1 to UTm in FIG. 6) according to a first embodiment of the present invention. In this figure, 1 is FLASH
This is a decoder circuit of the memory chip FM, and when a chip enable signal CEfB input from a terminal is, for example, “L” level, based on a plurality of input address signals,
Generate an internal address signal.

That is, when the chip enable signal is at "L" level, the decoder circuit 1
FLA based on a plurality of address signals input from
An internal address signal for selecting a memory cell indicated by the address signal in the SH memory chip FM is output.

Similarly, reference numeral 2 denotes a decoder circuit of the SRAM chip SM. When the chip enable signal CEsB (CS1sB) input from the terminal is at the "L" level, for example, the internal address is determined based on a plurality of input address signals. Generate a signal.

That is, when the chip enable signal is at “L” level, the decoder circuit 2
S (corresponding to the address signals A0 to A22 input to the bonding pads TA0 to TA22 in FIG. 16) input from S (corresponding to the bonding pads TA0 to TA22 in FIG. 16). , SRAM chip SM
Output an internal address signal for selecting a memory cell indicated by the address signal ADRS.

Reference numeral 3 denotes an input / output buffer control circuit of the FLASH memory chip FM, which controls output states of the input / output buffers OIF0 to OIF15. Further, the input / output buffer control circuit 3 sends the input / output buffers OIF0 to OIF15 to the input / output buffers OIF0 to OIF15 based on the chip enable signal CEfB input from the terminal, the output enable signal OEB input from the terminal, and the write enable signal WEB. Of the input / output buffer OIF0 to the input / output buffer OI0.
It controls the input / output of F15 and the memory cell unit F.

That is, the input / output buffer control circuit 3
For example, a chip enable signal CEf input from a terminal
B and the output enable signal OEB input from the terminal are both at the “L” level, and when the write enable signal WEB input from the terminal is at the “H” level, the control signal CTF and the control signal RDF cause In the memory cell section F, the data signal stored in the memory cell selected by the internal address signal is output from the input / output buffers OIF0 to OIF15. The input / output buffers OIF0 to OIF15 are respectively provided with bonding pads TDQ0 to bonding pad T
Connected to DQ15.

When, for example, the chip enable signal CEfB input from the terminal is “L”, the input / output buffer control circuit 3 outputs an “L” level control signal TMF to the memory cell unit F, and Activate part F. Further, the input / output buffer control circuit 3 determines that the chip enable signal CEfB input from the terminal and the output enable signal OEB input from the terminal are both at the “L” level, and the write enable signal input from the terminal is When WEB is at the “H” level, the memory cell unit F is set to a mode for reading data stored in the memory cells.

The input / output buffers OIF0 to OIF15
Also inputs an external data signal to the FLASH memory chip FM. When the data signal is input, the input / output buffers OIF0 to OIF15 perform level adjustment, waveform shaping, and the like of the data signal input from the outside.

At this time, the input / output buffer control circuit 3
For example, a chip enable signal CEf input from a terminal
B and a write enable signal WEB input from the terminal
Are both at "L" level and the output enable signal OEB input from the terminal is at "H" level, the control signal CTF and the control signal RDF select the memory cell unit F by the internal address signal. The data stored in the selected memory cell is output from the input / output buffers OIF0 to OIF15.

Reference numeral 4 denotes an input / output buffer control circuit of the SRAM chip SM, which controls output states of the input / output buffers OIS0 to OIS15. Further, the input / output buffer control circuit 4 includes a chip enable signal CEsB input from a terminal, a chip enable signal CEfB input from a terminal, an output enable signal OEB input from a terminal, and a write input signal from a terminal. Based on the enable signal WEB, the input / output buffer OIS0
制 御 Generates a control signal CTS and a control signal RDS to the input / output buffer OIS15, and controls input / output of the input / output buffers OIS0 to OIS15.

That is, the input / output buffer control circuit 4
For example, a chip enable signal CEs input from a terminal
B and the output enable signal OEB input from the terminal are both at the “L” level, and the chip enable signal CEfB input from the terminal and the write enable signal WEB are at the “H” level. The signal CTS and the control signal RDS cause the memory cell unit S
In S, the data stored in the memory cell selected by the internal address signal is output from the input / output buffers OIF0 to OIF15. Input / output buffer O
IS0 to input / output buffer OIS15 are connected to bonding pads TDQ0 to TDQ15, respectively.

That is, only when the FLASH memory chip FM is not selected, that is, when the chip enable signal CEfB is at “H” level, the input / output buffer OI
From F0 to the input / output buffer OIF15, the address signal AD
RS indicates the memory cell section S of the SRAM chip SM
It is possible to permit the output of the data stored in S.

When, for example, the chip enable signal CEsB input from the terminal is “L”, the input / output buffer control circuit 4 outputs an “L” level control signal TMF to the memory cell unit F, Activate part F. Further, the input / output buffer control circuit 3 determines that the chip enable signal CEfB input from the terminal and the output enable signal OEB input from the terminal are both at the “L” level, and the write enable signal input from the terminal is When WEB is at the “H” level, the memory cell unit F is set to a mode for reading data stored in the memory cells.

The input / output buffers OIS0 to OIS15
Also inputs an external data signal to the SRAM chip SM. When this data signal is input, the input / output buffers OIS0 to OIS15 perform level adjustment, waveform shaping, and the like of the data signal input from the outside.

At this time, the input / output buffer control circuit 4
For example, a chip enable signal CEs input from a terminal
B and a write enable signal WEB input from the terminal
Are both at "L" level and the output enable signal OEB input from the terminal is at "H" level, the memory cell section SS is selected by the internal address signal by the control signal CTS and the control signal RDS. The data stored in the selected memory cell is output from the input / output buffers OIS0 to OIS15.

Here, the output wiring from the input / output terminals of the input / output buffers OIF0 to OIF15 and the output wiring from the input / output terminals of the input / output buffers OIS0 to OIS15 are defined as bonding pads TDQ0.
To the bonding pads TDQ15 (corresponding to the data terminals TDD1,0 to TDD1,15,..., Data terminals TDDm, 0 to TDDm, 15 in FIG. 18 respectively). Therefore, the input / output buffer OIF
0 to each output signal from the input / output terminal of the input / output buffer OIF15 and each output signal from the input / output terminal of the input / output buffer OIS0 to the input / output buffer OIS15 are output signals DQ0 to output signal, respectively. The signal is output to the bonding pads TDQ0 to TDQ15 as DQ15.

Next, referring to FIG. 2, the input / output buffer O of FIG.
IF0 (input / output buffer OIF1 to input / output buffer OIF
15, I / O buffer OIS0 to I / O buffer OIS1
5) One configuration example will be described. FIG. 2 shows an input / output buffer O
It is a block diagram which shows one structure 0 of IF0.

In this figure, OUT is an output buffer section, and a control signal CTF (input / output buffer OIS0 to input / output buffer OIS15) input from the input / output buffer control circuit 3 (input / output buffer control circuit 4) is controlled. The output state is controlled by the signal CTS).

In the output buffer OUT, the NAND circuit NAND1 performs a NAND operation on the value of the input control signal CTF and the data DTF read from the memory cell, and outputs the signal SP as the operation result. Output to the gate of the channel transistor TP.

Inverter INV1 outputs an inverted signal of control signal CTF input from input / output buffer control circuit 3 to NOR circuit NOR1. The NOR circuit NOR1 performs a negative OR operation on the value of the inverted signal of the control signal CTF input from the inverter INV1 and the value of the data DTF read from the memory cell, and outputs the signal SN as the operation result to the n-channel transistor TN. Output to the gate.

The p-channel transistor TP has a source connected to the power supply Vdd and a drain connected to the drain of the n-channel transistor TN. The p-channel transistor TP is ON / OFF controlled by an input signal SP.

Here, the p-channel transistor TP
Is ON / OFF depending on the value of data DTF input to NAND circuit NAND1 when control signal CTF is at “H” level.
It is turned off. That is, the p-channel transistor T
P indicates that when the data DTF is at the “H” level, the signal SP is at the “L” level and is in the ON state, and when the data DTF is at the “L” level, the signal SP is at the “H” level.
The state becomes the FF state.

On the other hand, the p-channel transistor TP
When the control signal CTF is at “L” level, the NAND circuit NA
OF regardless of the value of data DTF input to ND1
The state is set to the F state. That is, the p-channel transistor TP outputs the NAND circuit NAND even when the data DTF is at the “H” level and when the data DTF is at the “L” level.
1 is masked by the control signal CTF at the “L” level, the signal SP is at the “H” level, and is in the OFF state.

The n-channel transistor TN has a source grounded and a drain p-channel transistor TP.
Connected to the drain. Further, the n-channel transistor TN is turned on by the input signal SN.
/ OFF control.

Here, the n-channel transistor TN
Indicates that the control signal CTF is at “H” level and the inverter INV
When the inversion signal output from 1 is at "L" level, it is turned on by the value of data DTF input to NOR circuit NOR1.
/ OFF. That is, when data DTF is at “H” level, n-channel transistor TN outputs signal SN.
Is at the “L” level and is in the OFF state, and the data DTF
Is at the "L" level, the signal SP is at the "H" level and is in the ON state.

On the other hand, the n-channel transistor TN
When the control signal CTF is at "L" level and the inverted signal output from the inverter INV1 is at "H" level, regardless of the value of the data DTF input to the NOR circuit NOR1, O
The state is set to the FF state. That is, the n-channel transistor TN outputs the NOR circuit NOR1 even when the data DTF is at the “H” level and when the data DTF is at the “L” level.
Are masked by the control signal CTF of “H” level,
The signal SN is at the “L” level and is in the OFF state.

IN is an input section, and a data signal D to be written into a memory cell of the memory cell section F (memory cell section SS).
Q0 (data signal DQ1 to data signal DQ15) is externally input. Inverter INV2 inverts the polarity of data signal DQ0 input from the outside, and outputs the inverted signal to buffer BUF1.

The buffer BUF1 is connected to the inverter INV2.
Again inverts the inverted signal of the data signal DQ0 input from, and outputs it as data DTF. Also, the buffer BU
F1 is a tri-state buffer, and the control signal RD
When F (control signal RDS) is at “L” level, the output is in a high impedance state. Furthermore, the buffer BUF
1 operates as an inverter when the control signal RDF is at “H” level.

Next, an example of the configuration of the input / output buffer control circuit 3 shown in FIG. 1 will be described with reference to FIG. FIG. 3 is a block diagram illustrating a configuration example of the input / output buffer control circuit 3. In the figure, an inverter INV3 inverts an input chip enable signal CEfB, and outputs an inverted signal of the inversion result to the inverter INV4. Inverter INV4 inverts the inverted signal of chip enable signal CEfB again, and outputs control signal TMF as the inverted result.

The NOR circuit NOR2 performs a negative OR operation on the input output enable signal OEB and the control signal TMF input from the inverter INV4, and outputs the operation result as a control signal CTF. That is, the NOR circuit NOR2 outputs the control signal CTF at the “H” level only when both the input output enable signal OEB and the control signal TMF are at the “L” level. On the other hand, the NOR circuit NOR2 outputs the control signal CTF at "L" level when any of the input output enable signal OEB and the control signal TMF is input at "H" level.

The NOR circuit NOR3 performs a negative OR operation on the input write enable signal WEB, the control signal TMF input from the inverter INV4, and the control signal CTF output from the NOR circuit NOR2. As a control signal RDF. That is, the NOR circuit NOR3 outputs the control signal RDF at the "H" level only when all of the input output enable signal OEB, the control signal TMF, and the control signal CTF are at the "L" level.

On the other hand, the NOR circuit NOR3 outputs the control signal RDF at "L" level when any of the output enable signal OEB, the control signal TMF and the control signal CTF is input at "H" level. I do. At this time, the control signal RDF becomes the output enable signal O
EB is at “H” level, and chip enable signal CE
Only when fB and the write enable signal WEB are at “L” level, the signal is output at “H” level.
Becomes the write mode.

Next, an example of the configuration of the input / output buffer control circuit 4 shown in FIG. 1 will be described with reference to FIG. FIG. 4 is a block diagram illustrating a configuration example of the input / output buffer control circuit 4. In this figure, an inverter INV5 inverts the input chip enable signal CEsB, and outputs an inverted signal of the inverted result to the inverter INV6. Inverter INV6 inverts the inverted signal of chip enable signal CEsB again, and outputs control signal TMS as an inverted result.

The NOR circuit NOR4 receives the input chip enable signal CEsB and the chip enable signal CEf.
Performs a logical OR operation with B and outputs the operation result to the signal Cfs
Output as That is, the NOR circuit NOR4 outputs the signal Cfs at the “H” level only when both the input chip enable signal CEsB and the chip enable signal CEfB are at the “L” level. On the other hand, the NOR circuit NOR4 receives the input chip enable signal CEsB.
And one of the chip enable signals CEfB is “H”
When input at the level, the signal Cfs is output at the “L” level.

The NOR circuit NOR5 performs a negative OR operation of the output enable signal OEB input thereto, the signal Cfs input from the NOR circuit NOR4, and the control signal TMS input from the inverter INV6, and calculates the operation result. As a control signal CTS. That is, NOR circuit NOR5 outputs control signal CTS at "H" level only when all of output enable signal OEB, signal Cfs and control signal TMS are at "L" level.

On the other hand, when one of the input enable signal OEB, the signal Cfs, and the control signal TMS is input at "H" level, the NOR circuit NOR5 receives the output enable signal OEB.
Outputs control signal CTS at "L" level. Therefore, even if the output enable signal OEB and the chip enable signal CEsB are at “L” level, if the chip enable signal CEfB is at “L”, the signal Cfs becomes “H” level, and the control signal CTS becomes “H” level. Level.

Therefore, when the FLASH memory chip FM is selected, the output enable signal OE
B and the chip enable signal CEsB become “L” level, the input / output buffer OIS
0-input / output buffer OIS15 does not enter the output state.

The NOR circuit NOR6 performs a negative OR operation on the input write enable signal WEB, the control signal TMS input from the inverter INV6, and the control signal CTS output from the NOR circuit NOR5. As a control signal RDS. That is, the NOR circuit NOR6 receives the input write enable signal WE.
B, control signal TMS and control signal CTS are all "L"
Only when the level is at the level, control signal RDS is output at "H" level.

On the other hand, when any of the input write enable signal WEB, control signal TMS and control signal CTS is input at "H" level, NOR circuit NOR6 outputs control signal RDS at "L" level. . Therefore, the control signal RDS is output at the "H" level only when the output enable signal OEB is at the "H" level and the chip enable signal CEsB and the write enable signal WEB are at the "L" level. Becomes the write mode.

The correspondence between the terminals in FIG. 16 and the terminals shown in FIG. 1 and the function of each terminal will be described below.
Here, the first embodiment of the present invention (and a modified example of the first embodiment, a second embodiment, and a third embodiment described later) and a conventional example are arranged in the following positional relationship of terminals. And the circuit configuration of the internal semiconductor element is different. In FIG. 16, B2 to B7, C1 to C8, E1 to E8,
F1 to F3, F6 to F8, G1 to G3, G6 to G8, H
1 to H8, I1 to I8, J2 to J7 are openings.

That is, the openings B2 to B7 and the opening C1
To C8, openings E1 to E8, openings F1 to F3, openings F6 to F8, openings G1 to G3, openings G6 to G8, openings H1 to H8, openings I1 to I8, openings J2 to J7.
The metal balls 106 (FIG. 1)
5 (b)) are connected.

Further, TA0 to TA22, TDQ0 to TD
Q15, TVSS, TVss, TSA, TNC, TVC
Cf, TVCCs, CIOf, CIOs, TRY / BY
B, TRESETB, TWEB, TUB, TLB, TC
EfB, TCE1sB, TCE2s, and TOEB are bonding pads, and correspond to, for example, the bonding pad 100A and the bonding pad 100B in FIG.

The openings B2 to B7 and the openings C1 to C7
C8, openings E1 to E8, openings F1 to F3, opening F
6 to F8, the openings G1 to G3, the openings G6 to G8, the openings H1 to H8, the openings I1 to I8, and the metal balls 106 on the lower surfaces corresponding to the openings J2 to J7,
5 through the bonding pad T as shown in FIG.
A0 to TA22, bonding pads TDQ0 to TDQ
15, bonding pad TVSS, bonding pad TVss, bonding pad TSA, bonding pad TNC, bonding pad TVCCf, bonding pad TVCCs, bonding pad CIO
f, bonding pads CIOs, bonding pads TRY / BYB, bonding pads TRESETB,
Bonding pads TWEB, TUB, bonding pad TLB, bonding pad TCefB, bonding pad TCE1sB, bonding pad TCE2
s and the bonding pad TOEB. Here, the symbol “B” at the end of the symbol of the above-mentioned bonding pad indicates that the input signal is input in negative logic.

The bonding pads TA0 to TA2
2, bonding pads TDQ0 to TDQ15, bonding pad TVSS, bonding pad TVss,
Bonding pad TSA, bonding pad TN
C, bonding pad TVCCf, bonding pad TVCCs, bonding pad CIOf, bonding pad CIOs, bonding pad TRY / BY
B, bonding pad TRESETB, bonding pad TWEB, TUB, bonding pad TLB,
Bonding pad TCefB, bonding pad T
CE1sB, the bonding pad TCE2s and the bonding pad TOEB are the bonding pad 100A.
And a bonding pad 100B, for example, a bonding wire 103 or a bonding wire 104.
15 (see FIG. 15A), it is electrically connected to the bonding pad of the SRAM chip SM and the bonding pad of the FLASH memory chip FM.

Further, each of the above-described bonding pads and each opening corresponding to the metal ball 106 electrically connected to the bonding pad by the wiring 105 is formed by:
Two wirings 105 are arranged between the openings so that two wirings 105 can be patterned.

Then, the bonding pads TA0 to TA
Reference numeral 22 denotes an address signal A of the SRAM chip SM.
0 to A22 (address signal ADRS) are connected to bonding pads. Similarly, the bonding pads TA0 to TA22 are connected to bonding pads corresponding to the address signals A0 to A22 of the FLASH memory chip FM, respectively. Unused bonding pads appear depending on the memory capacity used in the semiconductor memory device 1. For example, if address signals A0 to A22 are used, the memory capacity can correspond to 128M bits (4M bits × 16 bits output × 2). .

The bonding pads TDQ0 to TDQ0
Q15 is the data signal D of the SRAM chip SM, respectively.
Connected to bonding pads corresponding to Q0 to DQ15. Similarly, bonding pads TDQ0 to TDQ1
5 are connected to bonding pads corresponding to the data signals DQ0 to DQ15 of the FLASH memory chip FM, respectively.

The data signal of the FLASH memory chip FM has 16 bits of the data signals DQ0 to DQ15. For example, when an "H" level signal is applied to the bonding pad TCIOOf, the data signals DQ0 to DQ15 are provided.
15 16-bit outputs and the bonding pad TC
When an “L” level signal is applied to IOf, 8-bit outputs of data signals DQ0 to DQ7 are obtained.

Similarly, the data signals of SRAM chip SM have 16 bits of data signals DQ0 to DQ15. For example, when an "H" level signal is applied to bonding pads TCIOs, data signals DQ0 to DQ15 are provided.
15 16-bit outputs and the bonding pad TC
When an "L" level signal is applied to IOs, 8-bit data signals DQ0 to DQ7 are output.

FL is applied to the bonding pad TCefB.
Chip enable signal CEf for setting whether to enable or disable the ASH memory chip FM
B is supplied. For example, the bonding pad TCef
When the “L” level chip enable signal CEfB is applied to B, the FLASH memory chip FM is enabled. On the other hand, when “H” level chip enable signal CEfB is applied to bonding pad TCefB, FLA
SH memory chip FM is disabled (output prohibited state)
Becomes

The bonding pad TCE1sB has S
A chip enable signal CE1sB for setting whether to enable or disable the RAM chip SM is supplied. For example, the bonding pad TCE1sB
Is supplied with an "L" level chip enable signal CE1sB, the SRAM chip SM is enabled. On the other hand, when "H" level chip enable signal CE1sB is applied to bonding pad TCE1sB, SRAM
The chip SM is disabled.

The bonding pad TCE2s has an SR
A chip enable signal CE2s for setting whether to enable or disable the AM chip SM is supplied. For example, when an “H” level chip enable signal CE2s is applied to the bonding pad TCE2s, the SRAM chip SM is enabled. On the other hand, when an “L” level chip enable signal CE2s is applied to the bonding pad TCE2s, the SRAM chip SM
Is disabled.

The bonding pad TOEB has FLA
An output enable signal OEB for setting whether to enable or disable the output of the data signals DQ0 to DQ15 of the SH memory chip FM is supplied. For example, when an “L” level output enable signal OEB is applied to the bonding pad TOEB,
Data signals DQ0 to DQ1 of the LASH memory chip FM
The output of 5 is enabled. On the other hand, when an “H” level output enable signal OEB is applied to the bonding pad TOEB, the output of the data signals DQ0 to DQ15 of the FLASH memory chip FM is disabled.

The bonding pad TWEB has SRA
When data is stored in the M chip SM and the FLASH memory chip FM, a write enable signal WEB which is set to “L” level is supplied. Bonding pad TLBB
The data signal DQ is applied to the bonding pad TUBB.
0 to DQ15 are converted to lower byte data signals DQ0 to DQ.
7 and an upper byte data signal DQ8 to DQ15, a signal LBB and a signal UBB which are auxiliary signals for addressing when used separately.

The bonding pads TVss and TVSS have the SRAM chip SM and the FLA
The power VSS is supplied to the SH memory chip FM. A power supply VCC for the FLASH memory chip FM is supplied to the bonding pad TVCCf. The power supply VCC for the SRAM chip SM is supplied to the bonding pads TVCs.

The bonding pad TNC has an SRAM
Since a signal of a special function (write inhibit, test) for the chip SM and the FLASH memory chip FM is input, it is not connected to an external wiring in a normal case. The bonding pad RESETB has an SRAM chip SM
And a reset signal for the FLASH memory chip FM. For example, when a reset signal is input at “L” level, the SRAM chip SM and the FLASH memory chip FM are reset and initialized.

The bonding pads TRY and RYB have
The RY / RYB signal for detecting whether the FLASH memory chip FM is executing the automatic algorithm operation is output from the FLASH memory chip FM. That is, the RY / RYB signal is output as "0" during the writing or erasing operation, and the RY / RYB signal is output as "1" during the standby for the automatic algorithm operation.

The bonding pad TSA has an SRAM
The address signal of the chip SM is input. When the input / output of the SRAM chip SM is used in an 8-bit configuration (controlled by the control signal CIOs), a signal used as an address signal is input. On the other hand, an address signal of the SRAM chip SM is input. When the input / output of the SRAM chip SM is used in a 16-bit configuration, it becomes an invalid terminal.

Next, an example of the operation of the above-described first embodiment will be described with reference to FIGS. 1, 5 and 18. FIG. 5 shows the semiconductor memory device UT1 (semiconductor memory devices UT2 to UT2) shown in FIG.
6 is a timing chart showing the operation of the semiconductor memory device UTm). For example, as shown in FIG. 18, the VDD (power) terminals of the semiconductor storage devices UT1 to UTm are connected to the terminal T10 to supply a power supply voltage. In addition, the GND (ground) of the semiconductor memory devices UT1 to UTm
The terminal is connected to the terminal T11 and grounded. Further, the ADRS (address) terminals (corresponding to the bonding pads TA0 to TA22 in FIG. 16) of the semiconductor memory devices UT1 to UTm are connected to the terminal T12, and an address signal ADRS is supplied from outside.

Further, the OEB (output enable) terminals of the semiconductor memory devices UT1 to UTm are connected to the terminal T15, and the output enable signal O is output.
EB is supplied. Here, when an output enable signal OEB of “H” level is input to the OEB terminal,
F in the semiconductor memory devices UT1 to UTm
The LASH memory chip FM and the SRAM chip SM
In the read state, it is impossible to output data from the memory cell unit F and the memory cell unit SS indicated by the address signals from the input / output buffers OIF0 to OIF15 and the input / output buffers OIS0 to OIS15. It becomes a state.

On the other hand, when an "L" level output enable signal OEB is input to the OEB terminal, FLASH in the semiconductor memory devices UT1 to UTm is output.
When the memory chip FM and the SRAM chip SM are in the read state, the memory cells F and S
The data stored in the memory cell pointed to by the address signal of S is input / output buffer OIF0 to input / output buffer O
IF15, I / O buffer OIS0 to I / O buffer OI
It becomes a state where it is possible to output from S15. A write enable signal WEB is input from a WEB (write enable) terminal (not shown). In the semiconductor memory device UT1 (semiconductor memory devices UT2 to UTm), when the chip enable signal CEfB or the chip enable signal CEsB is at the “L” level, the chip in the enabled state has the write enable signal WEB at the “L” level. In this case, writing becomes possible, and in the case of "H" level, writing is not permitted.

Next, according to the timing chart of FIG.
The operation of the semiconductor storage device UT1 (semiconductor storage devices UT2 to UTm) of FIG. 1 will be described. At time t0, for example, the output enable signal OEB is at “H” level, the write enable signal WEB is at “L” level, the chip enable signals CEfB and CEsB are at “H”, and the control signal CTF And the control signal CTS is at the “L” level. At this time, the FLASH memory chips FM and SR
Since the AM chips SM are both disabled,
The data signals DQ0 to DQ15 are in a high impedance state.

Next, at time ta, an external device (not shown) causes the output enable signal OEB to transition from "H" level to "L" level and the write enable signal WEB to transition from "L" level to "H" level. The address signal ADRS is input from an external device (not shown).

Thus, the FLASH memory chip FM
For both the SRAM chip SM and the SRAM chip SM, the read mode of the data stored in the memory cell is instructed.
However, since the chip enable signal CEfB and the chip enable signal CEsB are “H”, FLA
The SH memory chip FM and the SRAM chip SM are not selected by the external device, and the read operation is not enabled.

Next, at time t1, an external device (not shown) changes the chip enable signal CEfB from "H" level to "L" level. With this, FLASH
The memory chip FM is selected by an external device (not shown). As a result, the input / output buffer control circuit 3 causes the control signal CTF to transition from “L” level to “H” level. At this time, the input / output buffer control circuit 3 outputs the control signal RDF at the “L” level and the control signal TMF at the “L” level.

Then, the FLASH memory chip FM
Data DTF0 to data DTF15 are read from the memory cell indicated by the address signal ADRS in the memory cell unit F. As a result, the input / output buffers OIF0 to OIF15 output the data DTF0 due to the transition of the control signal CTF from the “L” level to the “H” level.
To DTF15 are output as data signals DQ0 to DQ15, respectively. Here, FIG. 5 shows only the output state (DF1) of the data signal DQ0.

On the other hand, an external device (not shown) keeps the chip enable signal CEsB at “H” level. Therefore, the SRAM chip SM has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 4 outputs the control signal CTS as “L” level. As a result, the outputs of the input / output buffers OIS0 to OIS15 are in a high impedance state. At this time, the input / output buffer control circuit 4
The control signal RDS is output at "L" level, and the control signal TMS is output at "L" level.

Next, at time t2, an external device (not shown) causes the chip enable signal CEfB to transition from "L" level to "H" level. With this, FLASH
The memory chip FM changes from the selected state to the non-selected state.
As a result, the input / output buffer control circuit 3 outputs the control signal CT
F is changed from “H” level to “L” level. Then, the input / output buffers OIF0 to OIF15
Output is in a high impedance state. At this time,
The input / output buffer control circuit 3 sets the control signal RDF to “L”.
At this time, the control signal TMF is output at "H" level.

Next, at time t3, an external device (not shown) causes the chip enable signal CEsB to transition from "H" level to "L" level. Thus, the SRAM chip SM is selected by an external device (not shown). As a result, the input / output buffer control circuit 4 outputs the control signal CTS.
From the “L” level to the “H” level. At this time, the input / output buffer control circuit 4 outputs the control signal RDS at “L” level and the control signal TMS at “L” level.

Then, the SRAM chip SM reads the data DTS0 to DTS15 from the memory cell indicated by the address signal ADRS in the memory cell section SS. As a result, the input / output buffer OIS0 to the input / output buffer OI
In S15, the data DTS0 to data DTS are output when the control signal CTS changes from “L” level to “H” level.
TS15 is connected to data signal DQ0 to data signal DQ15, respectively.
Output as Here, FIG. 5 shows only the output state (DS1) of the data signal DQ0.

On the other hand, an external device (not shown) keeps the chip enable signal CEfB at “H” level. Therefore, the FLASH memory chip FM has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 3 outputs the control signal CTF as “L” level. Thereby, the input / output buffer OIF0
The output of the input / output buffer OIF15 is in a high impedance state. At this time, the input / output buffer control circuit 3 sets the control signal RDF to "L" level and
MF is output at “L” level.

Next, at time t4, an external device (not shown) changes the chip enable signal CEsB from "L" level to "H" level. As a result, the SRAM chip SM changes from the selected state to the non-selected state. As a result, the input / output buffer control circuit 4 causes the control signal CTS to transition from “H” level to “L” level. And
The input / output buffers OIS0 to OIS15 are
The output goes into a high impedance state. At this time, the input / output buffer control circuit 4 outputs the control signal RDS at "L" level and the control signal TMS at "H" level.

Next, at time t5, an external device (not shown) causes the chip enable signal CEfB to transition from "H" level to "L" level. With this, FLASH
The memory chip FM is selected by an external device (not shown). As a result, the input / output buffer control circuit 3 causes the control signal CTF to transition from “L” level to “H” level. At this time, the input / output buffer control circuit 3 outputs the control signal RDF at the “L” level and the control signal TMF at the “L” level.

Then, the FLASH memory chip FM
Data DTF0 to data DTF15 are read from the memory cell indicated by the address signal ADRS in the memory cell unit F. As a result, the input / output buffers OIF0 to OIF15 output the data DTF0 due to the transition of the control signal CTF from the “L” level to the “H” level.
To DTF15 are output as data signals DQ0 to DQ15, respectively. Here, FIG. 5 shows only the output state (DF2) of the data signal DQ0.

On the other hand, an external device (not shown) keeps the chip enable signal CEsB at “H” level. Therefore, the SRAM chip SM has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 4 outputs the control signal CTS as “L” level. As a result, the outputs of the input / output buffers OIS0 to OIS15 are in a high impedance state. At this time, the input / output buffer control circuit 4
The control signal RDS is output at "L" level, and the control signal TMS is output at "L" level.

Next, at time t6, an external device (not shown) causes the chip enable signal CEsB to transition from "H" level to "L" level. Thus, the SRAM chip SM is selected by an external device (not shown). However, since the chip enable signal CEfB is at the “L” level, the input / output buffer control circuit 4 outputs the signal Cfs
Becomes "H" level, and control signal CTS remains at "L" level. At this time, the input / output buffer control circuit 4
Sets the control signal RDS to the “L” level and the control signal TMS
At the “L” level.

For this reason, the SRAM chip SM is selected by an external device (not shown). However, since the control signal CTS is at "L" level, the input / output buffer OIS0
~ The output of the input / output buffer OIS15 is kept at high impedance. Therefore, the FLASH memory chip F
Since the output signals of the M and SRAM chips SM have high impedance at the outputs of the input / output buffers OIS0 to OIS15, the output enable signal OEB
Does not collide even if the level becomes "L" level.

Here, for example, during the burn-in test, the semiconductor memory device UT of the semiconductor memory devices shown in FIG.
The terminal to which the output enable signal of 1 is input is
"L" due to failure to short-circuit with internally grounded wiring
Let's say it is level. As a result, the wiring connected to the terminal T15 becomes “L” level.

However, the input / output buffer control circuits 3 and 4 described above use the input / output buffers OIF0 to OIF15 and the input / output buffers OIS0 to OIS0 of the semiconductor memory devices UT1 to UTm. The output buffer OIS15 sets the input / output buffers OIS0 to
Since the output of the input / output buffer OIS15 is in a high impedance state, it is protected from destruction due to data collision.

Next, at time t7, an external device (not shown) changes the chip enable signal CEfB from "L" level to "H" level. With this, FLASH
The memory chip FM changes from the selected state to the non-selected state.
As a result, the input / output buffer control circuit 3 outputs the control signal CT
F is changed from “H” level to “L” level. Then, the input / output buffers OIF0 to OIF15
Output is in a high impedance state. At this time,
The input / output buffer control circuit 3 sets the control signal RDF to “L”.
At this time, the control signal TMF is output at "H" level.

As a result, the chip enable signal CEs
Since B is at the “L” level and the SRAM chip SM is selected by an external device (not shown), the input / output buffer control circuit 4 changes the control signal CTS from the “L” level to the “H” level. At this time, the input / output buffer control circuit 4 outputs the control signal RDS at “L” level and the control signal TMS at “L” level.

The SRAM chip SM reads the data DTS0 to DTS15 from the memory cell indicated by the address signal ADRS in the memory cell section SS. As a result, the input / output buffer OIS0 to the input / output buffer OI
In S15, the data DTS0 to data DTS are output when the control signal CTS changes from “L” level to “H” level.
TS15 is connected to data signal DQ0 to data signal DQ15, respectively.
Output as Here, FIG. 5 shows only the output state (DS2) of the data signal DQ0.

On the other hand, an external device (not shown) has changed the chip enable signal CEfB from “L” level to “H” level. Therefore, the FLASH memory chip FM has not been selected by an external device (not shown). As a result,
The input / output buffer control circuit 3 sets the control signal CTF to “L”.
Output as level. As a result, the outputs of the input / output buffers OIF0 to OIF15 are in a high impedance state. At this time, the input / output buffer control circuit 3 sets the control signal RDF to “L” level,
The control signal TMF is output at "L" level.

Next, at time t8, an external device (not shown) causes the chip enable signal CEsB to transition from "L" level to "H" level. As a result, the SRAM chip SM changes from the selected state to the non-selected state. As a result, the input / output buffer control circuit 4 causes the control signal CTS to transition from “H” level to “L” level. And
The input / output buffers OIS0 to OIS15 are
The output goes into a high impedance state. At this time, the input / output buffer control circuit 4 outputs the control signal RDS at "L" level and the control signal TMS at "H" level.

Next, at time t9, an external device (not shown) causes the chip enable signal CEsB to transition from "H" level to "L" level. Thus, the SRAM chip SM is selected by an external device (not shown). As a result, the input / output buffer control circuit 4 outputs the control signal CTS.
From the “L” level to the “H” level. At this time, the input / output buffer control circuit 4 outputs the control signal RDS at “L” level and the control signal TMS at “L” level.

Then, the SRAM chip SM reads the data DTS0 to DTS15 from the memory cell indicated by the address signal ADRS in the memory cell section SS. As a result, the input / output buffer OIS0 to the input / output buffer OI
In S15, the data DTS0 to data DTS are output when the control signal CTS changes from “L” level to “H” level.
TS15 is connected to data signal DQ0 to data signal DQ15, respectively.
Output as Here, FIG. 5 shows only the output state (DS3) of the data signal DQ0.

On the other hand, an external device (not shown) keeps the chip enable signal CEfB at “H” level. Therefore, the FLASH memory chip FM has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 3 outputs the control signal CTF as “L” level. Thereby, the input / output buffer OIF0
The output of the input / output buffer OIF15 is in a high impedance state. At this time, the input / output buffer control circuit 3 sets the control signal RDF to “L” level and
MF is output at “L” level.

Next, at time t10, an external device (not shown) causes the chip enable signal CEfB to transition from the "H" level to the "L" level. With this, FLASH
The memory chip FM is selected by an external device (not shown). As a result, the input / output buffer control circuit 3 causes the control signal CTF to transition from “L” level to “H” level. At this time, the input / output buffer control circuit 3 outputs the control signal RDF at the “L” level and the control signal TMF at the “L” level.

At the same time, the input / output buffer control circuit 3 changes the control signal CTF from the “L” level to the “H” level, so that the input / output buffer control circuit 4 changes the control signal CTS from the “H” level to the “L” level. Transition to. Thereby, the input / output buffer OIS0 to the input / output buffer OIS15
Is in a high impedance state.

The FLASH memory chip FM reads data DTF0 to DTF15 from the memory cell indicated by the address signal ADRS in the memory cell unit F. As a result, the input / output buffers OIF0 to OIF15 output the data DTF0 due to the transition of the control signal CTF from the “L” level to the “H” level.
To DTF15 are output as data signals DQ0 to DQ15, respectively. Here, FIG. 5 shows only the output state (DF3) of the data signal DQ0.

Here, for example, during the burn-in test, the semiconductor memory device UT of the semiconductor memory device shown in FIG.
The terminal to which the output enable signal of 1 is input is
"L" due to failure to short-circuit with internally grounded wiring
Let's say it is level. As a result, the wiring connected to the terminal T15 becomes “L” level.

However, the input / output buffer control circuit 3 and the input / output buffer control circuit 4 described above use the input / output buffers OIF0 to OIF15 and the input / output buffers OIS0 to OIS0 of the semiconductor memory devices UT1 to UTm. The output buffer OIS15 sets the input / output buffers OIS0 to
Since the output of the input / output buffer OIS15 is in a high impedance state, it is protected from destruction due to data collision.

Next, at time t11, an external device (not shown) causes the chip enable signal CEsB to transition from "L" level to "H" level. As a result, the SRAM chip SM is not selected by an external device (not shown).
That is, it is in a non-selected state. As a result, the input / output buffer control circuit 4 outputs the control signal CTS at the “L” level, the control signal RDS at the “L” level, and the control signal TMS at the “L” level.

Next, at time t12, an external device (not shown) changes the chip enable signal CEfB from "L" level to "H" level. With this, FLASH
The memory chip FM changes from the selected state to the non-selected state.
As a result, the input / output buffer control circuit 3 outputs the control signal CT
F is changed from “H” level to “L” level. Then, the input / output buffers OIF0 to OIF15
Output is in a high impedance state. At this time,
The input / output buffer control circuit 3 sets the control signal RDF to “L”.
At this time, the control signal TMF is output at "H" level.

In the modification of the first embodiment, the semiconductor memory devices (UTT1 to UTT1) shown in FIG.
m) is configured such that the chip enable signal CEfB, the chip enable signal CEsB, and the output enable signal OEB are input to the input / output buffer control circuit 3A of the FLASH memory chip FMA, contrary to the first embodiment. Further, the input / output buffer control circuit 4A of the SRAM chip SMA enables / disables the input / output buffers OIS0 to OIS15 based on the chip enable signal CEsB and the output enable signal OEB.
Performs disable control.

Therefore, in the modified semiconductor memory device (UTT1 to UTTm), even when the output enable signal OEB and the chip enable signal CEfB are at the "L" level, the chip enable signal CEsB is at the "L" level.
Level, and when the SRAM chip SMA is in the enable state, the input / output buffers OIF0 to OIF15 of the FLASH memory chip FMA are in the output enable state in which the data stored in the memory cell unit F can be output. Instead, it is in a high impedance state.

In the semiconductor memory devices UTT1 to UTTm and the semiconductor memory devices UT1 to UTm, the same components are denoted by the same reference numerals as in FIG. 1, and detailed description is omitted. Semiconductor memory devices UTT1 to UTTm and semiconductor memory device UT
1 to the semiconductor memory device UTm is that the input / output buffer control circuit 3 and the input / output buffer control circuit 4 are respectively
It has been replaced by

An example of the configuration of the input / output buffer 3A shown in FIG. 6 will be described with reference to FIG. FIG. 7 is a block diagram illustrating a configuration example of the input / output buffer control circuit 3A. In this figure, the inverter INV10 inverts the input chip enable signal CEfB, and outputs an inverted signal of the inversion result to the inverter INV11. Inverter IN
V11 inverts the inverted signal of the chip enable signal CEfB again, and outputs the control signal TMF as the inverted result.

The NOR circuit NOR10 receives the chip enable signal CEfB and the chip enable signal CE
Performs a negative OR operation with sB and outputs the operation result as a signal Cs
Output as f. That is, the NOR circuit NOR10 is
Only when both the input chip enable signal CEfB and the chip enable signal CEsB are at the “L” level, the signal Csf is output at the “H” level. On the other hand, the NOR circuit NOR10 receives the input chip enable signal C
When any one of EsB and the chip enable signal CEfB is input at “H” level, the signal Csf is output at “L” level.

The NOR circuit NOR11 performs a NOR operation on the output enable signal OEB input, the signal Cfs input from the NOR circuit NOR4, and the control signal TMF input from the inverter INV11,
The calculation result is output as a control signal CTF. That is,
The NOR circuit NOR11 changes the control signal CTF to "H" only when all of the output enable signal OEB, the signal Csf and the control signal TMF are at "L" level.
Output at level.

On the other hand, NOR circuit NOR11 outputs control signal CTF at "L" level when any of input output enable signal OEB, signal Csf and control signal TMF is input at "H" level. . Therefore, the control signal CTF is the output enable signal O
Even if the EB and the chip enable signal CEfB are at the “L” level, if the chip enable signal CEsB is at the “L” level, the signal Csf goes to the “H” level and goes to the “L” level.

Therefore, when the SRAM chip SMA is selected, even if the output enable signal OEB and the chip enable signal CEfB go to the “L” level, the input / output buffer O of the FLASH memory chip FMA is
IF0 to input / output buffer OIF15 are not in the output state.

The NOR circuit NOR12 performs a NOR operation on the input write enable signal WEB, the control signal TMF input from the inverter INV11, and the control signal CTF output from the NOR circuit NOR11.
The calculation result is output as a control signal RDF. That is,
The NOR circuit NOR12 outputs the control signal RDF at "H" level only when all of the input write enable signal WEB, control signal TMF, and control signal CTF are at "L" level.

On the other hand, when one of the input write enable signal WEB, control signal TMF, and control signal CTF is input at "H" level, the NOR circuit NOR12 receives the write enable signal WEB.
Outputs control signal RDF at "L" level. Therefore, the control signal RDF is output at the “H” level only when the output enable signal OEB is at the “H” level and the chip enable signal CEfB and the write enable signal WEB are at the “L” level. Becomes the write mode.

Next, an example of the configuration of the input / output buffer control circuit 4A shown in FIG. 6 will be described with reference to FIG. FIG. 8 is a block diagram illustrating a configuration example of the input / output buffer control circuit 4A. In the figure, the inverter INV12 inverts the input chip enable signal CEsB, and outputs an inverted signal of the inverted result to the inverter INV13. The inverter INV13 has a chip enable signal CEsB
Of the control signal TM as an inversion result.
Output S.

The NOR circuit NOR13 receives the output enable signal OEB and the inverter INV13.
And performs a logical OR operation with the control signal TMS input from the controller, and outputs the operation result as a control signal CTS. That is, NOR circuit NOR13 outputs control signal CTS at "H" level only when both output enable signal OEB and control signal TMS are at "L" level. On the other hand, the NOR circuit NOR13 receives the output enable signal OEB and the control signal T
When any of the MSs is input at the “H” level, the control signal CTS is output at the “L” level.

The NOR circuit NOR14 performs a NOR operation on the input write enable signal WEB, the control signal TMS input from the inverter INV13, and the control signal CTS output from the NOR circuit NOR13,
The calculation result is output as a control signal RDS. That is,
NOR circuit NOR14 outputs control signal RDS at "H" level only when all of output enable signal OEB, control signal TMS and control signal CTS which are input are at "L" level.

On the other hand, NOR circuit NOR14 outputs control signal RDS at "L" level when any of input output enable signal OEB, control signal TMS and control signal CTS is input at "H" level. I do. At this time, when the output enable signal OEB is at “H” level and the chip enable signal C
Only when the EsB and the write enable signal WEB are at the “L” level, the signal is output at the “H” level, and the memory cell unit SS enters the write mode.

Each FLASH memory chip FM in semiconductor memory devices UTT1 to UTTm
A, SRAM chip SMA operation is performed by the input / output buffer 3A.
Are the same as the input / output buffer 4, and the input / output buffer 4A
Are the same as the input / output buffer 3, and the configuration of both input / output buffers is reversed. As a result, the operation in the timing chart shown in FIG.
The relationship between the FLASH memory chip FM and the SRAM chip SM in the semiconductor memory device UTm from T1 is reversed, and detailed description is omitted.

Therefore, the semiconductor memory devices UT1 to UT1 to
When the semiconductor memory device UTm and the semiconductor memory devices UTT1 to UTTm are in a state of simultaneous data output, the output of the other input / output buffer is always in a high impedance state by one chip enable signal. Input / output buffer OIF0 to input / output buffer OI
F15 and input / output buffer OIS0 to input / output buffer O
Data is not output simultaneously from IS15. Therefore, according to the present invention, it is possible to prevent the input / output buffers OIF0 to OIF15 and the input / output buffers OIS0 to OIS15 from being destroyed due to the collision of the data signals DQ0 to DQ15.

The semiconductor memory devices UT1 to UTm and the semiconductor memory devices UTT1 to UTTm of the first embodiment and the modification of the first embodiment have been described as being semiconductor devices. It is also effective for a semiconductor element of a logic circuit having an input / output buffer sharing a terminal.

Further, the semiconductor memory devices UT1 to U according to the above-described first embodiment and its modification are described.
Tm and semiconductor memory device UTT1 to semiconductor memory device UTT
m has been described in the case where the OEB terminal is shared, but even when the OEB terminal is provided for each semiconductor element, a failure in which the OEB terminal of one of the semiconductor elements is grounded may occur. When this happens, it is possible to prevent the input / output buffer of the other semiconductor element from being brought into the output enable state, thereby preventing the input / output buffer from being destroyed. At this time, in order to control the output state of the other semiconductor element, either the OEB signal or the CEB signal of one semiconductor element is input to the input / output buffer control circuit.

Further, the semiconductor memory devices UT1 to UTm and the semiconductor memory devices UTT1 to UTTm according to the first embodiment and the modified example described above have been described by taking a test as an example. The semiconductor memory device of the present invention can prevent a failure of an input / output buffer even when the input / output buffer is simultaneously output from another semiconductor element even when mounted on a substrate.

Further, in the semiconductor memory devices UT1 to UTm according to the first embodiment and the modified example described above, the output terminal of the semiconductor element is changed to the output terminal D.
Although the description has been made with the sixteen Q0 to output terminals DQ15, any number of output terminals may be used.

<Second Embodiment> An embodiment of the present invention has been described above in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and the gist of the present invention will be described. Even a design change or the like within a range not departing from the present invention is included in the present invention. Here, in the configuration of the second embodiment shown in FIG. 9, the same components as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and detailed description is omitted.

The configuration of FIGS. 15 and 16 is the same as that of the first embodiment, and the circuit configuration of the internal semiconductor element is different. Here, the first embodiment semiconductor memory device UT1
The difference between the semiconductor memory device UTm and the semiconductor memory devices UTA1 to UTAm shown in FIG.
The LASH memory chip FM is the FLASH memory chip F
This is the point that has been changed to MA. The other configurations of the semiconductor memory devices UT1 to UTm of the first embodiment and the semiconductor memory devices UTA1 to UTAm shown in FIG. 9 are the same.

Next, referring to FIG. 9, FIG. 10 and FIG.
An operation example of the first embodiment described above will be described. FIG.
10 is a timing chart showing the operation of the semiconductor memory device UTA1 (semiconductor memory devices UTA2 to UTAm) shown in FIG. For example, as shown in FIG.
VDD of semiconductor memory devices UTA1 to UTAm
A (power) terminal is connected to the terminal T10 to supply a power voltage. Further, the semiconductor storage devices UT1 to UTm
(Ground) terminal is connected to the terminal T11 and grounded. Further, the ADRS (address) terminals of the semiconductor memory devices UTA1 to UTAm are connected to the terminal T12, and an address signal ADRS is supplied from outside.

Further, the OEB (output enable) terminals of the semiconductor memory devices UTA1 to UTAm are connected to the terminal T15, and the output enable signal OEB is supplied. Here, when the output enable signal OEB at the “H” level is input to the OEB terminal, the FLASH memory chip FMA and the SRAM chip SM in the semiconductor memory devices UTA1 to UTAm are in the read state, respectively. The data from the memory cell unit F and the memory cell unit SS indicated by the signal are input / output buffers OIF0 to OIF1.
5. It becomes impossible to output from the input / output buffers OIS0 to OIS15.

On the other hand, when the output enable signal OEB at the "L" level is input to the OEB terminal, the FLA in the semiconductor memory devices UTA1 to UTAm is output.
When in the read state, the SH memory chip FMA and the SRAM chip SM transfer the data stored in the memory cells indicated by the address signals of the memory cell unit F and the memory cell unit SS to the input / output buffers OIF0 to OIF15, A state is now possible in which data can be output from the input / output buffers OIS0 to OIS15.

Next, according to the timing chart of FIG. 10, the semiconductor memory device UTA1 (semiconductor memory device UTA1) of FIG.
The operation of TA2 to semiconductor memory device UTAm) will be described. Here, time t1 to time t1 used in FIG.
2 is different from time t1 to time t12 used in FIG.

At time t0, for example, the output enable signal OEB is at the “H” level, the write enable signal WEB is at the “L” level, and the chip enable signal CEfB and the chip enable signal CEsB.
Is “H”, and the control signal CTF and the control signal CTS are at “L” level. At this time, since the FLASH memory chip FMA and the SRAM chip SM are both disabled, the data signals DQ0 to DQ15 are in a high impedance state.

Next, at time ta, an external device (not shown) causes the output enable signal OEB to transition from “H” level to “L” level, and the write enable signal WEB to transition from “L” level to “H” level. The address signal ADRS is input from an external device (not shown).

As a result, the FLASH memory chip FM
For both the SRAM chip SM and the SRAM chip SM, the read mode of the data stored in the memory cell is instructed.
However, since the chip enable signal CEfB and the chip enable signal CEsB are “H”, FLA
The SH memory chip FMA and the SRAM chip SM are not selected by the external device, and the read operation is not enabled.

Next, at time t1, an external device (not shown) changes the chip enable signal CEfB from "H" level to "L" level. With this, FLASH
The memory chip FMA is selected by an external device (not shown). As a result, the input / output buffer control circuit 3A changes the control signal CTF from the “L” level to the “H” level because the chip enable signal CEsB is at the “H” level. At this time, the input / output buffer control circuit 3
The control signal RDF is output at "L" level, and the control signal TMF is output at "L" level.

Then, the FLASH memory chip FMA
Reads data DTF0 to data DTF15 from the memory cell indicated by the address signal ADRS in the memory cell unit F. As a result, the input / output buffers OIF0 to OIF15 output the data DTF0 due to the transition of the control signal CTF from the “L” level to the “H” level.
To DTF15 are output as data signals DQ0 to DQ15, respectively. Here, FIG. 10 shows only the output state (DF1) of the data signal DQ0.

On the other hand, an external device (not shown) keeps the chip enable signal CEsB at “H” level. Therefore, the SRAM chip SM has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 4 outputs the control signal CTS as “L” level. As a result, the outputs of the input / output buffers OIS0 to OIS15 are in a high impedance state. At this time, the input / output buffer control circuit 4
The control signal RDS is output at "L" level, and the control signal TMS is output at "L" level.

Next, at time t2, an external device (not shown) changes the chip enable signal CEfB from "L" level to "H" level. With this, FLASH
The memory chip FMA changes from the selected state to the non-selected state. As a result, the input / output buffer control circuit 3A causes the control signal CTF to transition from “H” level to “L” level. The outputs of the input / output buffers OIF0 to OIF15 enter a high impedance state. At this time, the input / output buffer control circuit 3A outputs the control signal RD
F is output at "L" level, and control signal TMF is output at "H" level.

Next, at time t3, an external device (not shown) causes the chip enable signal CEsB to transition from "H" level to "L" level. Thus, the SRAM chip SM is selected by an external device (not shown). As a result, the input / output buffer control circuit 4 outputs the control signal CfB since the chip enable signal CEfB is at the “H” level.
TS is changed from “L” level to “H” level. At this time, the input / output buffer control circuit 4 outputs the control signal RDS
At the "L" level, and the control signal TMS at the "L" level.

Then, the SRAM chip SM reads the data DTS0 to DTS15 from the memory cell indicated by the address signal ADRS in the memory cell section SS. As a result, the input / output buffer OIS0 to the input / output buffer OI
In S15, the data DTS0 to data DTS are output when the control signal CTS changes from “L” level to “H” level.
TS15 is connected to data signal DQ0 to data signal DQ15, respectively.
Output as Here, FIG. 5 shows only the output state (DS1) of the data signal DQ0.

On the other hand, an external device (not shown) keeps the chip enable signal CEfB at “H” level. For this reason, the FLASH memory chip FMA has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 3A outputs the control signal CTF as “L” level. Thereby, the input / output buffer OI
The outputs from F0 to the input / output buffer OIF15 are in a high impedance state. At this time, the input / output buffer control circuit 3A outputs the control signal RDF at "L" level and the control signal TMF at "L" level.

Next, at time t4, an external device (not shown) changes the chip enable signal CEsB from "L" level to "H" level. As a result, the SRAM chip SM changes from the selected state to the non-selected state. As a result, the input / output buffer control circuit 4 causes the control signal CTS to transition from “H” level to “L” level. And
The input / output buffers OIS0 to OIS15 are
The output goes into a high impedance state. At this time, the input / output buffer control circuit 4 outputs the control signal RDS at "L" level and the control signal TMS at "H" level.

Next, at time t5, an external device (not shown) causes the chip enable signal CEfB to transition from "H" level to "L" level. With this, FLASH
The memory chip FMA is selected by an external device (not shown). As a result, the input / output buffer control circuit 3A changes the control signal CTF from the “L” level to the “H” level because the chip enable signal CEsB is at the “H” level. At this time, the input / output buffer control circuit 3A
Sets the control signal RDF to the “L” level and the control signal TMF
At the “L” level.

Then, the FLASH memory chip FMA
Reads data DTF0 to data DTF15 from the memory cell indicated by the address signal ADRS in the memory cell unit F. As a result, the input / output buffers OIF0 to OIF15 output the data DTF0 due to the transition of the control signal CTF from the “L” level to the “H” level.
To DTF15 are output as data signals DQ0 to DQ15, respectively. Here, FIG. 5 shows only the output state (DF2) of the data signal DQ0.

On the other hand, an external device (not shown) keeps the chip enable signal CEsB at “H” level. Therefore, the SRAM chip SM has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 4 outputs the control signal CTS as “L” level. As a result, the outputs of the input / output buffers OIS0 to OIS15 are in a high impedance state. At this time, the input / output buffer control circuit 4
The control signal RDS is output at "L" level, and the control signal TMS is output at "L" level.

Next, at time t6, an external device (not shown) causes the chip enable signal CEsB to transition from "H" level to "L" level. Thus, the SRAM chip SM is selected by an external device (not shown). However, since the chip enable signal CEfB is at the “L” level, the input / output buffer control circuit 4 outputs the signal Cfs
Becomes "H" level, and control signal CTS remains at "L" level. At this time, the input / output buffer control circuit 4
Sets the control signal RDS to the “L” level and the control signal TMS
At the “L” level.

For this reason, the SRAM chip SM is selected by an external device (not shown). However, since the control signal CTS is at "L" level, the input / output buffer OIS0
~ The output of the input / output buffer OIS15 is kept at high impedance. When the chip enable signal CEsB changes to the “L” level, the input / output buffer control circuit 3A changes the control signal CTF from the “H” level because the signal Csf changes from the “L” level to the “H” level. Transition to the “L” level.

As a result, the FLASH memory chip FM
A input / output buffer OIF0 to A / O buffer OIF15
Output is in a high impedance state. Therefore, the FLASH memory chip FM and the SRAM chip S
Since the output signal of M has high impedance at the outputs of the input / output buffers OIS0 to OIS15, there is no data collision even when the output enable signal OEB is at the "L" level.

Here, for example, during the burn-in test, the semiconductor memory device UT of the semiconductor memory device shown in FIG.
It is assumed that the terminal to which the output enable signal A1 is input has been set to the “L” level due to a fault that short-circuits with the internally grounded wiring. Thereby, the terminal T15
Is at the "L" level.

However, the input / output buffer control circuit 3A and the input / output buffer control circuit 4 described above use the input / output buffers OIF0 to OIF15 and the input / output buffers OIS0 to OIS0 of the semiconductor memory devices UTA1 to UTAm. When the output buffer OIS15 is in the data simultaneous output state, both output states are in a high-impedance state, so that the output buffer OIS15 is protected from destruction due to data collision.

Next, at time t7, an external device (not shown) causes the chip enable signal CEfB to transition from "L" level to "H" level. With this, FLASH
The memory chip FMA changes from the selected state to the non-selected state. As a result, the input / output buffer control circuit 3A causes the control signal CTF to transition from “H” level to “L” level. The outputs of the input / output buffers OIF0 to OIF15 enter a high impedance state. At this time, the input / output buffer control circuit 3 outputs the control signal RDF
Are output at "L" level and the control signal TMF is output at "H" level.

As a result, the chip enable signal CEs
Since B is at the “L” level and the SRAM chip SM is selected by an external device (not shown), the input / output buffer control circuit 4 changes the control signal CTS from the “L” level to the “H” level. At this time, the input / output buffer control circuit 4 outputs the control signal RDS at “L” level and the control signal TMS at “L” level.

Then, the SRAM chip SM reads data DTS0 to data DTS15 from the memory cell indicated by the address signal ADRS in the memory cell section SS. As a result, the input / output buffer OIS0 to the input / output buffer OI
In S15, the data DTS0 to data DTS are output when the control signal CTS changes from “L” level to “H” level.
TS15 is connected to data signal DQ0 to data signal DQ15, respectively.
Output as Here, FIG. 5 shows only the output state (DS2) of the data signal DQ0.

On the other hand, an external device (not shown) has changed the chip enable signal CEfB from “L” level to “H” level. For this reason, the FLASH memory chip FMA
Not selected by an external device (not shown). As a result, the input / output buffer control circuit 3A outputs the control signal CTF as “L” level. As a result, the outputs of the input / output buffers OIF0 to OIF15 are in a high impedance state. At this time, the input / output buffer control circuit 3A outputs the control signal RDF at "L" level and the control signal TMF at "L" level.

Next, at time t8, an external device (not shown) changes the chip enable signal CEsB from "L" level to "H" level. As a result, the SRAM chip SM changes from the selected state to the non-selected state. As a result, the input / output buffer control circuit 4 causes the control signal CTS to transition from “H” level to “L” level. And
The input / output buffers OIS0 to OIS15 are
The output goes into a high impedance state. At this time, the input / output buffer control circuit 4 outputs the control signal RDS at "L" level and the control signal TMS at "H" level.

Next, at time t9, an external device (not shown) causes the chip enable signal CEsB to transition from "H" level to "L" level. Thus, the SRAM chip SM is selected by an external device (not shown). As a result, the input / output buffer control circuit 4 outputs the control signal CTS.
From the “L” level to the “H” level. At this time, the input / output buffer control circuit 4 outputs the control signal RDS at “L” level and the control signal TMS at “L” level.

The SRAM chip SM reads the data DTS0 to DTS15 from the memory cell indicated by the address signal ADRS in the memory cell section SS. As a result, the input / output buffer OIS0 to the input / output buffer OI
In S15, the data DTS0 to data DTS are output when the control signal CTS changes from “L” level to “H” level.
TS15 is connected to data signal DQ0 to data signal DQ15, respectively.
Output as Here, FIG. 5 shows only the output state (DS3) of the data signal DQ0.

On the other hand, an external device (not shown) keeps the chip enable signal CEfB at “H” level. For this reason, the FLASH memory chip FMA has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 3A outputs the control signal CTF as “L” level. Thereby, the input / output buffer OI
The outputs from F0 to the input / output buffer OIF15 are in a high impedance state. At this time, the input / output buffer control circuit 3A outputs the control signal RDF at "L" level and the control signal TMF at "L" level.

Next, at time t10, an external device (not shown) causes the chip enable signal CEfB to transition from "H" level to "L" level. With this, FLASH
The memory chip FMA is selected by an external device (not shown). As a result, the input / output buffer control circuit 4 changes the control signal CTS from the “H” level to the “L” level because the chip enable signal CEfB goes to the “L” level and the signal Cfs goes to the “H” level.

As a result, the outputs of the input / output buffers OIS0 to OIS15 enter a high impedance state. At this time, the input / output buffer control circuit 4 outputs the control signal RDS at “L” level and the control signal TMS at “L” level.

Similarly, the input / output buffer control circuit 3A
Although the chip enable signal CEfB has transitioned from “H” level to “L” level, the chip enable signal C
Since EfB is at "L" level, signal Csf is at "H" level and control signal CTF is output at "L" level.
As a result, the outputs of the input / output buffers OIF0 to OIF15 enter a high impedance state.

Here, for example, during the burn-in test, the semiconductor memory device UT of the semiconductor memory device shown in FIG.
The terminal to which the output enable signal of 1 is input is
"L" due to failure to short-circuit with internally grounded wiring
Let's say it is level. As a result, the wiring connected to the terminal T15 becomes “L” level.

However, the input / output buffer control circuit 3A and the input / output buffer control circuit 4 described above use the input / output buffers OIF0 to OIF15 and the input / output buffers OIS0 to OIS0 of the semiconductor memory devices UTA1 to UTAm. When the output buffer OIS15 is in the data simultaneous output state, both output states are in a high-impedance state, so that the output buffer OIS15 is protected from being destroyed by data collision.

Next, at time t11, an external device (not shown) changes the chip enable signal CEsB from the "L" level to the "H" level. As a result, the SRAM chip SM is not selected by an external device (not shown).
That is, it is in a non-selected state. As a result, the input / output buffer control circuit 4 outputs the control signal CTS at the “L” level, the control signal RDS at the “L” level, and the control signal TMS at the “L” level.

Thus, the input / output buffer control circuit 3A
When the chip enable signal CEsB goes to the “H” level, the signal Csf goes to the “L” level, causing the control signal CTF to transition from the “L” level to the “H” level. At this time, the input / output buffer control circuit 3A outputs the control signal RDF at "L" level and the control signal TMF at "L" level.

Then, the FLASH memory chip FMA
Reads data DTF0 to data DTF15 from the memory cell indicated by the address signal ADRS in the memory cell unit F. As a result, the input / output buffers OIF0 to OIF15 output the data DTF0 due to the transition of the control signal CTF from the “L” level to the “H” level.
To DTF15 are output as data signals DQ0 to DQ15, respectively. Here, FIG. 5 shows only the output state (DF3) of the data signal DQ0.

On the other hand, an external device (not shown) keeps the chip enable signal CEsB at “H” level. Therefore, the SRAM chip SM has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 4 outputs the control signal CTS as “L” level. As a result, the outputs of the input / output buffers OIS0 to OIS15 are in a high impedance state. At this time, the input / output buffer control circuit 4
The control signal RDS is output at "L" level, and the control signal TMS is output at "L" level.

Next, at time t12, an external device (not shown) causes the chip enable signal CEfB to transition from "L" level to "H" level. With this, FLASH
The memory chip FM changes from the selected state to the non-selected state.
As a result, the input / output buffer control circuit 3 outputs the control signal CT
F is changed from “H” level to “L” level. Then, the input / output buffers OIF0 to OIF15
Output is in a high impedance state. At this time,
The input / output buffer control circuit 3 sets the control signal RDF to “L”.
At this time, the control signal TMF is output at "H" level.

Therefore, the input / output buffers OIF0 to OIF15 and the input / output buffers OIS0 to OIS15 in the semiconductor memory devices UTA1 to UTAm are both in the state where data is output simultaneously. The output goes into a high impedance state. Therefore, the semiconductor memory device U according to the second embodiment
TA1 to the semiconductor memory device UTAm include an input / output buffer OI
F0 to input / output buffer OIF15 and input / output buffer O
IS0 to collision of each output signal from input / output buffer OIS15, that is, data signal DQ0 to data signal DQ15
The input / output buffer can be prevented from being destroyed due to the collision of data.

The semiconductor memory devices UTA1 to UTAm according to the second embodiment have been described as the case where memories are used as semiconductor elements. However, a logic circuit having an input / output buffer sharing an output terminal is described. It is also effective for the semiconductor device of the above.

Further, the semiconductor memory devices UTA1 to UTAm according to the above-described second embodiment have been described in the case where the OEB terminal is shared.
Even when the OEB terminal is provided for each semiconductor element, when the OEB terminal of one semiconductor element is grounded, the input / output buffers of both semiconductor elements are set to the output enable state. And the destruction of the input / output buffer can be prevented. At this time, in order to control the output state of both the semiconductor elements, either the OEB signal or the CEB signal of the semiconductor elements is input to the respective input / output buffer control circuits.

Further, the semiconductor memory devices UTA1 to UTAm of the second embodiment described above have been described by taking a test as an example. However, the semiconductor memory device of the present invention is mounted on a substrate. In addition, when the input / output buffer is simultaneously output from another semiconductor element, the input / output buffer can be prevented from failing.

Further, in the semiconductor memory devices UTA1 to UTAm of the second embodiment described above, the output terminals of the semiconductor elements are connected to the output terminals DQ0 to DQ15.
However, any number of output terminals may be used.

<Third Embodiment> While one embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and the gist of the present invention will be described. Even a design change or the like within a range not departing from the present invention is included in the present invention. Here, in the configuration of the third embodiment shown in FIG. 11, the same components as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and detailed description is omitted.

The configuration of FIGS. 15 and 16 is the same as that of the first embodiment, and the circuit configuration of the internal semiconductor element is different. Here, the semiconductor memory device UT of the first embodiment
1 to the semiconductor memory device UTBm and the semiconductor memory devices UTB1 to UTBm shown in FIG.
The FLASH memory chip FM is replaced by the FLASH memory chip FMB, and the SRAM chip SM is replaced by the SRAM chip SMB.
It has been changed to The other configurations of the semiconductor storage devices UT1 to UTm of the first embodiment are the same as those of the semiconductor storage devices UTB1 to UTBm shown in FIG.

Next, an example of the configuration of the input / output buffer control circuit 3B shown in FIG. 11 will be described with reference to FIG. FIG.
Is a block diagram illustrating a configuration example of an input / output buffer control circuit 3B. In this figure, the inverter INV20
Inverts the input chip enable signal CEfB, and outputs an inverted signal of the inverted result to the inverter INV21. Inverter INV21 inverts the inverted signal of chip enable signal CEfB again, and outputs control signal TMF as the inverted result.

When the chip enable signal CEfB input to the terminal S is at the “H” level and the chip enable signal CEsB input to the terminal R is at the “L” level, data is set to the latch LT1. From "H"
A level signal Cf is output. Conversely, the latch LT1
Is the chip enable signal CEfB input to the terminal S
Is at the “L” level and the chip enable signal CEsB input to the terminal R is at the “H” level, the data is set, and the “L” level signal Cf is output from the terminal Q.

When the chip enable signal CEfB input to the terminal S is at the “L” level and the chip enable signal CEsB input to the terminal R is at the “L” level, the latch LT1 is output from the terminal Q. Signal C
The level of f does not change. Further, in the latch LT1, the “H” level signal input to the terminal R is given priority, and the chip enable signal CEfB input to the terminal S is set to “H”.
Level, the chip enable signal C input to the terminal R
When EsB is at the “H” level, data is set and an “L” level signal Cf is output from terminal Q.

NOR circuit NOR20 performs a negative OR operation on input enable signal OEB, signal Cf input from latch LT1, and control signal TMF input from inverter INV21, and outputs the operation result. Output as control signal CTF. That is, in the NOR circuit NOR20, all of the output enable signal OEB, the signal Cf, and the control signal TMF that are input are “L”.
The control signal CTF is output at the “H” level only when the level is at the “H” level. On the other hand, when any one of the input enable signal OEB, the signal Cf, and the control signal TMF is input at “H” level, the NOR circuit NOR20 outputs the control signal CTF at “L” level.

The NOR circuit NOR21 performs a negative OR operation on the input write enable signal WEB, the control signal TMF input from the inverter INV4, and the control signal CTF output from the NOR circuit NOR20. As a control signal RDF. That is, the NOR circuit NOR3 sets the control signal RDF to "H" only when all of the input output enable signal OEB, the control signal TMF, and the control signal CTF are at "L" level.
Output at level.

On the other hand, when any of the output enable signal OEB, the control signal TMF, and the control signal CTF is input at "H" level, the NOR circuit NOR21 outputs the control signal RDF at "L" level. I do. At this time, when the output enable signal OEB is at the “H” level and the chip enable signal C
Only when EfB and the write enable signal WEB are at the “L” level, the signal is output at the “H” level, and the memory cell unit F enters the write mode.

Next, an example of the configuration of the input / output buffer control circuit 4B shown in FIG. 11 will be described with reference to FIG. FIG.
Is a block diagram illustrating a configuration example of an input / output buffer control circuit 4B. In this figure, the inverter INV22
Inverts the input chip enable signal CEsB, and outputs an inverted signal of the inverted result to the inverter INV23. Inverter INV23 inverts the inverted signal of chip enable signal CEsB again, and outputs control signal TMS as an inverted result.

When the chip enable signal CEsB input to the terminal S is at the “H” level and the chip enable signal CEfB input to the terminal R is at the “L” level, data is set to the latch LT2. From "H"
The level signal Cs is output. Conversely, the latch LT2
Is the chip enable signal CEsB input to the terminal S
Is "L" level, and the chip enable signal CEfB input to the terminal R is at "H" level, data is set and the terminal Q outputs the "L" level signal Cs.

When the chip enable signal CEsB input to the terminal S is at the “L” level and the chip enable signal CEfB input to the terminal R is at the “L” level, the latch LT2 outputs the signal from the terminal Q. Signal C
The level of s does not change. Further, in the latch LT2, the “H” level signal input to the terminal R is given priority, and the chip enable signal CEsB input to the terminal S is set to “H”.
Level, the chip enable signal C input to the terminal R
When EfB is at the “H” level, data is set and an “L” level signal Cs is output from terminal Q.

The NOR circuit NOR22 performs a negative OR operation on the input output enable signal OEB, the signal Cs input from the latch LT2, and the control signal TMS input from the inverter INV23, and outputs the operation result. Output as control signal CTS. That is, in the NOR circuit NOR22, all of the output enable signal OEB, the signal Cs, and the control signal TMS that are input are “L”.
Only when the level is at the level, the control signal CTS is output at the “H” level. On the other hand, when any one of the input enable signal OEB, the signal Cs, and the control signal TMS is input at “H” level, the NOR circuit NOR22 outputs the control signal CTS at “L” level.

The NOR circuit NOR23 performs a NOR operation on the input write enable signal WEB, the control signal TMS input from the inverter INV23, and the control signal CTS output from the NOR circuit NOR22,
The calculation result is output as a control signal RDS. That is,
The NOR circuit NOR23 outputs the control signal RDS at "H" level only when all of the output enable signal OEB, the control signal TMS, and the control signal CTS are at "L" level.

On the other hand, NOR circuit NOR23 outputs control signal RDS at "L" level when any of input output enable signal OEB, control signal TMS and control signal CTS is input at "H" level. I do. At this time, when the output enable signal OEB is at “H” level and the chip enable signal C
Only when the EsB and the write enable signal WEB are at the “L” level, the signal is output at the “H” level, and the memory cell unit SS enters the write mode.

Next, an example of the operation of the third embodiment will be described with reference to FIGS. 11, 12, 13, 14, and 18. FIG. FIG. 14 shows the semiconductor memory device UT shown in FIG.
B1 (semiconductor storage device UTB2 to semiconductor storage device UTB)
6 is a timing chart showing the operation of m). For example,
As shown in FIG. 18, the VDD (power) terminals of the semiconductor memory devices UTB1 to UTBm are connected to the terminal T10 to supply a power voltage. In addition, the semiconductor storage device UT
1 to terminal T of the semiconductor memory device UTm
Connect to 11 and ground. Further, the semiconductor storage device UT
1 to the ADRS (address) terminal of the semiconductor memory device UTm are connected to the terminal T12, and an address signal ADRS
Is supplied.

The OEB (output enable) terminals of the semiconductor memory devices UTB1 to UTBm are connected to the terminal T15, and the output enable signal OEB is supplied. Here, when the output enable signal OEB at the “H” level is input to the OEB terminal, the FLASH memory chip FMB and the SRAM chip SMB in the semiconductor memory devices UTB1 to UTBm are respectively set to the address in the read state. The data from the memory cell unit F and the memory cell unit SS indicated by the signal are transferred to the input / output buffers OIF0 to OI0.
F15, I / O buffer OIS0 to I / O buffer OIS1
It becomes impossible to output from 5.

On the other hand, when the output enable signal OEB at the "L" level is input to the OEB terminal, FLA in the semiconductor memory devices UTB1 to UTBm is output.
The SH memory chip FMB and the SRAM chip SMB
In the read state, the data stored in the memory cells indicated by the address signals of the memory cell unit F and the memory cell unit SS are read from the input / output buffers OIF0 to OIF15 and the input / output buffers OIS0 to OIS15. It is possible to output.

Next, according to the timing chart of FIG.
The semiconductor memory device UTB1 (semiconductor memory device UTB2) of FIG.
The operation of the semiconductor memory device UTBm) will be described. Here, from time t0 to time t1 used in FIG.
2 is different from time t0 to time t12 used in FIG. 5 and FIG.

At time t 0, for example, the output enable signal OEB is at “H” level, the write enable signal WEB is at “L” level, and the chip enable signal CEfB and the chip enable signal CEsB
Is “H”, and the control signal CTF and the control signal CTS are at “L” level. At this time, since the FLASH memory chip FMB and the SRAM chip SMB are both disabled, the data signals DQ0 to DQ15 are in a high impedance state.

Next, at time ta, an external device (not shown) causes the output enable signal OEB to transition from “H” level to “L” level, and the write enable signal WEB to transition from “L” level to “H” level. The address signal ADRS is input from an external device (not shown).

As a result, the FLASH memory chip FM
The read mode of data stored in the memory cell is instructed for each of the B and SRAM chips SMB. However, since the chip enable signal CEfB and the chip enable signal CEsB are “H”, F
LASH memory chip FMB and SRAM chip SMB
Is not selected by the external device, and the read operation is not enabled.

Next, at time t1, an external device (not shown) causes the chip enable signal CEfB to transition from "H" level to "L" level. With this, FLASH
The memory chip FMB is selected by an external device (not shown). As a result, the chip enable signal CEfB input to the terminal S of the latch LT1 becomes “L” level,
Since the chip enable signal CEsB input to the terminal R is at “H” level, the latch LT1 outputs the signal Cf at “L” level.

As a result, the input / output buffer control circuit 3B
Since the output enable signal OEB, the signal Cf, and the control signal TMF to be input are at the “L” level,
The control signal CTF is changed from “L” level to “H” level. At this time, the input / output buffer control circuit 3B
Sets the control signal RDF to the “L” level and the control signal TMF
At the “L” level.

Then, the FLASH memory chip FMB
Reads data DTF0 to data DTF15 from the memory cell indicated by the address signal ADRS in the memory cell unit F. As a result, the input / output buffers OIF0 to OIF15 output the data DTF0 due to the transition of the control signal CTF from the “L” level to the “H” level.
To DTF15 are output as data signals DQ0 to DQ15, respectively. Here, FIG. 14 shows only the output state (DF1) of the data signal DQ0.

On the other hand, an external device (not shown) keeps the chip enable signal CEsB at “H” level. For this reason, the SRAM chip SMB has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 4B outputs the control signal CTS as “L” level.

Here, in the latch LT2, when the chip enable signal CEsB input to the terminal S is at the “H” level and the chip enable signal CEfB input to the terminal R
Is at the "L" level, the signal Cs is output at the "H" level. As a result, the outputs of the input / output buffers OIS0 to OIS15 are in a high impedance state. At this time, the input / output buffer control circuit 4
Sets the control signal RDS to the “L” level and the control signal TMS
At the “L” level.

Next, at time t2, an external device (not shown) causes the chip enable signal CEfB to transition from "L" level to "H" level. With this, FLASH
The memory chip FMB changes from the selected state to the non-selected state. As a result, the chip enable signal CEfB input to the terminal S of the latch LT1 becomes “H” level, and the chip enable signal CEsB input to the terminal R becomes “H”.
Therefore, the latch LT1 keeps the signal Cf at the “L” level.

Thereby, the input / output buffer control circuit 3B
Indicates that the input chip enable signal CEfB is “H”
Therefore, the control signal CTF changes from “H” level to “L” level. And the input / output buffer O
The outputs of IF0 to input / output buffer OIF15 are in a high impedance state. At this time, the input / output buffer control circuit 3B outputs the control signal RDF at "L" level and the control signal TMF at "H" level.

Next, at time t3, an external device (not shown) causes the chip enable signal CEsB to transition from "H" level to "L" level. Thus, the SRAM chip SMB is selected by an external device (not shown).
As a result, the chip enable signal CEsB input to the terminal S of the latch LT2 becomes “L” level, and the chip enable signal CEfB input to the terminal R is at “H” level, so that the latch LT2 changes the signal Cs to “L”. Output at the "level.

Thus, the input / output buffer control circuit 4B
Since the output enable signal OEB, the signal Cs, and the control signal TMS that are input become “L” level,
The control signal CTS is changed from “L” level to “H” level. At this time, the input / output buffer control circuit 4B outputs the control signal RDS at "L" level and the control signal TMS at "L" level.

Then, the SRAM chip SMB reads the data DTS0 to DTS15 from the memory cell indicated by the address signal ADRS in the memory cell section SS.
As a result, the input / output buffer OIS0 to the input / output buffer O
IS15 changes data DTS0 to data DTS15 from data signal DQ0 to data signal DQ1 when control signal CTS transitions from "L" level to "H" level.
Output as 5. Here, FIG. 14 shows the data signal DQ0.
Is shown only in the output state (DS1).

On the other hand, an external device (not shown) keeps the chip enable signal CEfB at “H” level. Therefore, the FLASH memory chip FMB has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 3B outputs the control signal CTF as “L” level. Thereby, the input / output buffer OI
The outputs from F0 to the input / output buffer OIF15 are in a high impedance state. At this time, the input / output buffer control circuit 3B outputs the control signal RDF at "L" level and the control signal TMF at "L" level.

Next, at time t 4, an external device (not shown) changes the chip enable signal CEsB from “L” level to “H” level. As a result, the SRAM chip SMB changes from the selected state to the non-selected state. As a result, the chip enable signal CEsB input to the terminal S of the latch LT2 becomes “H” level, and the chip enable signal CEfB input to the terminal R is “H” level, so that the latch LT2 changes the signal Cf to “L”. Level.

Thus, the input / output buffer control circuit 4B
Indicates that the input chip enable signal CEsB is “H”.
Therefore, the control signal CTS is changed from “H” level to “L” level. And the input / output buffer O
The outputs of the IS0 to the input / output buffer OIS15 are in a high impedance state. At this time, the input / output buffer control circuit 4B outputs the control signal RDS at "L" level and the control signal TMS at "H" level.

Next, at time t5, an external device (not shown) causes the chip enable signal CEfB to transition from "H" level to "L" level. With this, FLASH
The memory chip FMB is selected by an external device (not shown). As a result, the chip enable signal CEfB input to the terminal S of the latch LT1 becomes “L” level,
Since the chip enable signal CEsB input to the terminal R is at “H” level, the latch LT1 outputs the signal Cf at “L” level.

Thus, input / output buffer control circuit 3B
Since the output enable signal OEB, the signal Cf, and the control signal TMF to be input are at the “L” level,
The control signal CTF is changed from “L” level to “H” level. At this time, the input / output buffer control circuit 3B outputs the control signal RDF at "L" level and the control signal TMF at "L" level.

Then, the FLASH memory chip FMB
Reads data DTF0 to data DTF15 from the memory cell indicated by the address signal ADRS in the memory cell unit F. As a result, the input / output buffers OIF0 to OIF15 output the data DTF0 due to the transition of the control signal CTF from the “L” level to the “H” level.
To DTF15 are output as data signals DQ0 to DQ15, respectively. Here, FIG. 14 shows only the output state (DF2) of the data signal DQ0.

On the other hand, an external device (not shown) keeps the chip enable signal CEsB at “H” level. For this reason, the SRAM chip SMB has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 4B outputs the control signal CTS as “L” level. As a result, the outputs of the input / output buffers OIS0 to OIS15 are in a high impedance state. At this time, the input / output buffer control circuit 4
B sets the control signal RDS to the “L” level and sets the control signal TM
S is output at the “L” level.

Next, at time t 6, an external device (not shown) changes the chip enable signal CEsB from “H” level to “L” level. Thus, the SRAM chip SMB is selected by an external device (not shown).
However, in the latch LT2, although the chip enable signal CEsB input to the terminal S becomes “L” level,
Since the chip enable signal CEfB input to the terminal R has already been at the “L” level, the signal Cs output from the terminal Q is held at the “H” level.

Thus, the input / output buffer control circuit 4B
Since the chip enable signal CEfB and the chip enable signal CEsB are at the “L” level and the signal Cs is held at the “H” level, the control signal CTS is output at the “L” level. At this time, the input / output buffer control circuit 4B outputs the control signal RDS at "L" level and the control signal TMS at "L" level.

Therefore, the SRAM chip SMB has been selected by an external device (not shown). However, since the control signal CTS is at "L" level, the input / output buffer OIS
0 to keep the output of the input / output buffer OIS15 at high impedance. Therefore, the output signals of the FLASH memory chip FMB and the SRAM chip SMB have high impedance at the outputs of the input / output buffers OIS0 to OIS15, and therefore do not collide even if the output enable signal OEB is at the "L" level.

Here, for example, during the burn-in test, the semiconductor memory device UT of the semiconductor memory device shown in FIG.
It is assumed that the terminal to which the output enable signal B1 is input has been set to the "L" level due to a fault that short-circuits with the internally grounded wiring. Thereby, the terminal T15
Is at the "L" level.

However, the input / output buffer control circuit 3B and the input / output buffer control circuit 4B described above use the input / output buffers OIF0 to OIF15 and the input / output buffers OIS0 to OIS0 of the semiconductor memory devices UTB1 to UTBm. The output buffer OIS15 is
When data is output simultaneously, the input / output buffer
Since the outputs of IS0 to input / output buffer OIS15 are in a high impedance state, they are protected from destruction due to data collision.

Next, at time t7, an external device (not shown) changes the chip enable signal CEfB from "L" level to "H" level. With this, FLASH
The memory chip FMB changes from the selected state to the non-selected state. As a result, the chip enable signal CEfB input to the terminal S of the latch LT1 becomes “H” level, and the chip enable signal CEsB input to the terminal R becomes “H”.
Therefore, the latch LT1 keeps the signal Cf at the “L” level.

As a result, the input / output buffer control circuit 3B
Indicates that the input chip enable signal CEfB is “H”
Therefore, the control signal CTF changes from “H” level to “L” level. And the input / output buffer O
The outputs of IF0 to input / output buffer OIF15 are in a high impedance state. At this time, the input / output buffer control circuit 3B outputs the control signal RDF at "L" level and the control signal TMF at "H" level.

Since the SRAM chip SMB has been selected by an external device (not shown), the latch LT2
Is the chip enable signal CEsB input to the terminal S
Is at “L” level, the chip enable signal CEfB input to the terminal R is reset to “H” level, and the signal Cs output from the terminal Q is changed from “H” level to “L” level. Let it.

Thus, the input / output buffer control circuit 4B
Since all of the input chip enable signal CEsB, control signal TMS, and signal Cs are at the “L” level,
The control signal CTS is changed from “L” level to “H” level. At this time, the input / output buffer control circuit 4B outputs the control signal RDS at "L" level and the control signal TMS at "L" level.

The SRAM chip SMB reads data DTS0 to DTS15 from the memory cell indicated by the address signal ADRS in the memory cell section SS.
As a result, the input / output buffer OIS0 to the input / output buffer O
IS15 changes data DTS0 to data DTS15 from data signal DQ0 to data signal DQ1 when control signal CTS transitions from "L" level to "H" level.
Output as 5. Here, FIG. 14 shows the data signal DQ0.
Is shown only in the output state (DS2).

On the other hand, an external device (not shown) has changed the chip enable signal CEfB from “L” level to “H” level. Therefore, the FLASH memory chip FMB
Not selected by an external device (not shown). As a result, the input / output buffer control circuit 3B outputs the control signal CTF as “L” level. As a result, the outputs of the input / output buffers OIF0 to OIF15 are in a high impedance state. At this time, the input / output buffer control circuit 3B outputs the control signal RDF at "L" level and the control signal TMF at "L" level.

Next, at time t8, an external device (not shown) causes the chip enable signal CEsB to transition from "L" level to "H" level. As a result, the SRAM chip SMB changes from the selected state to the non-selected state. As a result, the chip enable signal CEsB input to the terminal S of the latch LT2 becomes “H” level, and the chip enable signal CEfB input to the terminal R is “H” level, so that the latch LT2 changes the signal Cf to “L”. Level.

As a result, the input / output buffer control circuit 4B
Indicates that the input chip enable signal CEsB is “H”.
Therefore, the control signal CTS is changed from “H” level to “L” level. And the input / output buffer O
The outputs of the IS0 to the input / output buffer OIS15 are in a high impedance state. At this time, the input / output buffer control circuit 4B outputs the control signal RDS at "L" level and the control signal TMS at "H" level.

Next, at time t9, an external device (not shown) causes the chip enable signal CEsB to transition from "H" level to "L" level. Thus, the SRAM chip SMB is selected by an external device (not shown).
As a result, the chip enable signal CEsB input to the terminal S of the latch LT2 becomes “L” level, and the chip enable signal CEfB input to the terminal R is at “H” level, so that the latch LT2 changes the signal Cs to “L”. Output at the "level.

Thus, the input / output buffer control circuit 4B
Since the output enable signal OEB, the signal Cs, and the control signal TMS that are input become “L” level,
The control signal CTS is changed from “L” level to “H” level. At this time, the input / output buffer control circuit 4B outputs the control signal RDS at "L" level and the control signal TMS at "L" level.

Then, the SRAM chip SMB reads the data DTS0 to DTS15 from the memory cell indicated by the address signal ADRS in the memory cell section SS.
As a result, the input / output buffer OIS0 to the input / output buffer O
IS15 changes data DTS0 to data DTS15 from data signal DQ0 to data signal DQ1 when control signal CTS transitions from "L" level to "H" level.
Output as 5. Here, FIG. 14 shows the data signal DQ0.
Is shown only in the output state (DS3).

On the other hand, an external device (not shown) keeps the chip enable signal CEfB at “H” level. Therefore, the FLASH memory chip FMB has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 3B outputs the control signal CTF as “L” level. Thereby, the input / output buffer OI
The outputs from F0 to the input / output buffer OIF15 are in a high impedance state. At this time, the input / output buffer control circuit 3B outputs the control signal RDF at "L" level and the control signal TMF at "L" level.

Next, at time t10, an external device (not shown) changes the chip enable signal CEfB from the "H" level to the "L" level. With this, FLASH
The memory chip FMB is selected by an external device (not shown). However, the latch LT1 outputs the chip enable signal CEfB input to the terminal R while the chip enable signal CEfB input to the terminal S goes to the “L” level.
Since sB is already at the “L” level, the signal Cf output from the terminal Q is held at the “H” level.

Thus, input / output buffer control circuit 3B
Since the chip enable signal CEfB and the chip enable signal CEsB are at the “L” level, the signal Cf is maintained at the “H” level, so that the control signal CTF is output at the “L” level. At this time, the input / output buffer control circuit 3B outputs the control signal RDF at "L" level and the control signal TMF at "L" level.

Therefore, the FLASH memory chip FMB
Is selected by an external device (not shown), but since the control signal CTF is at "L" level, the outputs of the input / output buffers OIF0 to OIF15 remain at high impedance. Therefore, the output signals of the FLASH memory chip FMB and the SRAM chip SMB are output from the input / output buffers OIF0 to OIF15.
Does not collide even if the output enable signal OEB becomes "L" level.

Here, for example, during the burn-in test, the semiconductor memory device UT of the semiconductor memory device shown in FIG.
It is assumed that the terminal to which the output enable signal B1 is input has been set to the "L" level due to a fault that short-circuits with the internally grounded wiring. Thereby, the terminal T15
Is at the "L" level.

However, the input / output buffer control circuit 3B and the input / output buffer control circuit 4B described above use the input / output buffers OIF0 to OIF15 and the input / output buffers OIS0 to OIS0 of the semiconductor memory devices UTB1 to UTBm. The output buffer OIS15 is
When data is output simultaneously, the input / output buffer
Since the outputs of IF0 to input / output buffer OIF15 are in a high impedance state, they are protected from destruction due to data collision.

Next, at time t11, an external device (not shown) causes the chip enable signal CEsB to transition from "L" level to "H" level. As a result, the SRAM chip SMB is not selected by an external device (not shown), that is, is in a non-selected state. As a result, the latch LT
Chip enable signal CEsB input to the terminal S
Becomes "H" level, and the chip enable signal CEfB input to the terminal R is at "H" level, so that the latch LT2 keeps the signal Cs at "L" level.

Thus, the input / output buffer control circuit 4B
Indicates that the input chip enable signal CEsB is “H”.
Therefore, the control signal CTS is changed from “H” level to “L” level. And the input / output buffer O
The outputs of the IS0 to the input / output buffer OIS15 are in a high impedance state. At this time, the input / output buffer control circuit 4B outputs the control signal RDS at "L" level and the control signal TMS at "L" level.

Since the FLASH memory chip FMB is selected by an external device (not shown), the latch LT1 outputs the chip enable signal C input to the terminal S.
EfB is at the “L” level, the chip enable signal CEsB input to the terminal R is reset to the “H” level, and the signal Cf output from the terminal Q is reset to the “H” level.
A transition is made from the level to the “L” level.

Thus, input / output buffer control circuit 3B
Since the input chip enable signal CEfB, control signal TMF, and signal Cf all have the “L” level,
The control signal CTF is changed from “L” level to “H” level. At this time, the input / output buffer control circuit 3B outputs the control signal RDF at "L" level and the control signal TMF at "L" level.

Then, the FLASH memory chip FMB
Reads data DTF0 to data DTF15 from the memory cell indicated by the address signal ADRS in the memory cell unit F. As a result, the input / output buffers OIF0 to OIF15 output the data DTF0 due to the transition of the control signal CTF from the “L” level to the “H” level.
To DTF15 are output as data signals DQ0 to DQ15, respectively. Here, FIG. 14 shows only the output state (DF3) of the data signal DQ0.

On the other hand, an external device (not shown) has changed the chip enable signal CEsB from “L” level to “H” level. For this reason, the SRAM chip SMB has not been selected by an external device (not shown). As a result, the input / output buffer control circuit 4B outputs the control signal CTS as “L” level. Thereby, the input / output buffer O
The outputs of IS0 to input / output buffer OIS15 are in a high impedance state. At this time, the input / output buffer control circuit 4B outputs the control signal RDS at "L" level and the control signal TMS at "L" level.

Next, at time t12, an external device (not shown) changes the chip enable signal CEfB from the "L" level to the "H" level. With this, FLASH
The memory chip FMB changes from the selected state to the non-selected state. As a result, the chip enable signal CEfB input to the terminal S of the latch LT1 becomes “H” level, and the chip enable signal CEsB input to the terminal R becomes “H”.
Therefore, the latch LT1 keeps the signal Cf at the “L” level.

Thus, input / output buffer control circuit 3B
Indicates that the input chip enable signal CEfB is “H”
Therefore, the control signal CTF changes from “H” level to “L” level. And the input / output buffer O
The outputs of IF0 to input / output buffer OIF15 are in a high impedance state. At this time, the input / output buffer control circuit 3B outputs the control signal RDF at "L" level and the control signal TMF at "H" level.

Accordingly, the input / output buffers OIF0 to OIF15 and the input / output buffers OIS0 to OIS15 in the semiconductor memory devices UTB1 to UTBm are not connected to the input / output buffers OIS0 to OIS15 at the same time. The output state in which the chip enable signal becomes the “L” level is enabled. Then, the output state of the input / output buffer for which the chip enable signal has become the “L” level later becomes the high impedance state.
For this reason, the semiconductor memory device UTB according to the third embodiment
1 to the semiconductor storage device UTBm
~ I / O buffer OIF15 and I / O buffer OIS
The collision of each output signal from 0 to the input / output buffer OIS15, that is, the destruction of the input / output buffer due to the collision of the data signals DQ0 to DQ15 can be prevented.

Although the semiconductor memory devices UTB1 to UTBm according to the third embodiment have been described as memories as semiconductor elements, a logic circuit having an input / output buffer sharing an output terminal is described. It is also effective for the semiconductor device of the above.

Further, the semiconductor memory devices UTB1 to UTBm according to the third embodiment have been described in the case where the OEB terminals are shared.
Even when the OEB terminal is provided for each semiconductor element, when the OEB terminal of one semiconductor element is grounded, the input / output buffers of both semiconductor elements are set to the output enable state. And the destruction of the input / output buffer can be prevented. At this time, in order to control the output state of both the semiconductor elements, either the OEB signal or the CEB signal of the semiconductor elements is input to the respective input / output buffer control circuits.

Further, the semiconductor memory devices UTB1 to UTBm of the third embodiment described above have been described by taking a test as an example. However, the semiconductor memory device of the present invention is mounted on a substrate. In addition, when the input / output buffer is simultaneously output from another semiconductor element, the input / output buffer can be prevented from failing.

Further, in the semiconductor memory devices UTB1 to UTBm of the third embodiment described above, the output terminals of the semiconductor elements are changed from the output terminals DQ0 to DQ15.
However, any number of output terminals may be used.

[0266]

According to the first aspect of the present invention, in a semiconductor device in which a plurality of semiconductor elements sharing an output terminal are sealed in one package, the first semiconductor element and the first semiconductor element are provided. A second semiconductor element having a second output buffer connected to a common output terminal with a first output buffer provided on the element, and a first control signal supplied to the first semiconductor element. A first output buffer control means for controlling an output state of the first output buffer,
A second control signal supplied to the second semiconductor element, and a second output buffer control means for controlling an output state of the second output buffer based on the first control signal. Since the second output buffer is controlled in accordance with the control state of the first output buffer, it is possible to prevent the first output buffer and the second output buffer from being in a state where output is simultaneously enabled. This has the effect of preventing collision of a plurality of data at the output terminal and preventing the first output buffer and the second output buffer from being destroyed by the data collision.

According to the second aspect of the present invention, when the second output buffer control means enables the output of the first output buffer by the first control signal, the second control signal is output from the second control signal. When the second output buffer is enabled, the output state of the second output buffer is set to a high impedance state, so that the first output buffer and the second output buffer are simultaneously output. This has the effect of preventing the valid state, preventing the collision of a plurality of data at the output terminal, and preventing the first output buffer and the second output buffer from being destroyed by the data collision.

According to the third aspect of the present invention, the first control signal controls whether or not the operation of the first semiconductor element is enabled, and the first element selection signal, And a first element output signal for controlling whether to enable or disable the output buffer of the second semiconductor element, and controls whether or not the second control signal enables the operation of the second semiconductor element. Since the second element selection signal and the second element output signal for controlling whether to validate the second output buffer, the second output based on the first element selection signal Since the buffer control means controls the output state of the second output buffer, it is possible to prevent the first output buffer and the second output buffer from being in the output state at the same time and to prevent collision of a plurality of data at the output terminal. , The first output buffer and the second The effect of the output buffer is prevented from broken by collision of the data.

According to the fourth aspect of the present invention, the first input / output control means controls the first element when the first semiconductor element is enabled by the first element selection signal. An output signal controls whether or not to enable the first output buffer, and when the second semiconductor element is enabled, the second element output signal and the second element selection signal enable the second semiconductor element to be activated. Since the second output buffer control means controls the output state of the second output buffer based on the first element selection signal to control whether or not to enable the output buffer of the first output buffer, Prevents the second output buffer from being in the output state at the same time, prevents multiple data collisions at the output terminal, and prevents the first output buffer and the second output buffer from being destroyed due to data collision. You There is an effect.

According to the fifth aspect of the present invention, in a semiconductor device in which a plurality of semiconductor elements sharing an output terminal are sealed in a single package, the first semiconductor element and the first semiconductor element may be provided. A second semiconductor element having a second output buffer connected to a common output terminal provided by the first output buffer provided, a first control signal supplied to the first semiconductor element, and the second semiconductor element; Based on a second control signal supplied to the semiconductor element, a first output buffer control means for controlling the output state of the first output buffer, based on the first control signal and the second control signal A second output buffer control means for controlling the output state of the second output buffer, to control the second output buffer according to the control state of the first output buffer, Ma Performs the control of the first output buffer according to the control state of the second output buffer, so that the output of the first output buffer and the second output buffer is simultaneously enabled. Thus, there is an effect that the first output buffer and the second output buffer are prevented from being destroyed due to the data collision.

According to the sixth aspect of the present invention, when the first control signal enables the output of the first output buffer, the second control signal enables the second output buffer. And when the second control signal is in a state of validating the output of the second output buffer, when the first control signal is in a state of validating the first output buffer The first output buffer control means sets the first output buffer to a high impedance state, and the second output buffer control means sets the output state of the second output buffer to a high impedance state. When both output buffers are in a valid state, both output buffers are in a high impedance state, so that the first output buffer and the second output buffer are simultaneously in a state in which output is valid. Is the possible to prevent, prevent collision of a plurality of data at the output terminal, the first output buffer and the second output buffer is effective to prevent being damaged by a collision of the data.

According to the seventh aspect of the present invention, in the semiconductor device according to the fifth aspect, when both the first output buffer and the second output buffer are in a high impedance state,
If the first control signal is in a state where the output of the first output buffer is made valid first, the second output buffer control means sets the second control signal to enable the second output buffer. The second output buffer is kept in a high impedance state even when the state of the second output buffer is in the state where the output of the second output buffer is made valid first. One output buffer control means keeps the first output buffer in a high impedance state even when the first control signal makes the first output buffer valid. If the buffer is enabled by the first control signal, and the second output buffer is subsequently enabled by the first control signal, since the second output buffer is in a high impedance state, the first output Ba The output of the first output buffer and the second output buffer are prevented from being simultaneously enabled, the collision of a plurality of data at the output terminal is prevented, and the first output buffer and the second output buffer collide with each other. Has the effect of preventing it from being destroyed.

According to an eighth aspect of the present invention, in the semiconductor device according to the seventh aspect, the first output buffer and the control means are configured to control the first control signal and the second Since each of the second control signals includes a latch circuit for storing which of the first output buffer and the second output buffer is enabled first, for example, the other first output buffer is enabled. Since the latch state is stored in the second output buffer control means in the second output buffer control means, even if a second control signal for enabling the second output buffer is input, the second output buffer Keeps the output state at high impedance, thereby preventing the first output buffer and the second output buffer from being in an output valid state at the same time, and transmitting a plurality of data at the output terminal. Prevent collision, the first output buffer and the second output buffer is effective to prevent being damaged by a collision of the data.

According to the ninth aspect, the first control signal controls whether or not the operation of the first semiconductor element is enabled, A first element output signal for controlling whether to enable the output buffer, and a second element for controlling whether the second control signal enables the operation of the second semiconductor element. And the second output buffer control means based on the first element selection signal because the second output buffer control means Controls the output state of the second output buffer, and the first output buffer control means controls the output state of the first output buffer based on the second element selection signal. Output buffer and output state simultaneously To prevent that that prevents a collision of a plurality of data at the output terminal, the first output buffer and the second output buffer is effective to prevent from being destroyed by a collision of the data

According to the tenth aspect, when the first semiconductor element is enabled by the first element selection signal, the first input / output control means sets the first element. The output signal and the second element selection signal controls whether to enable the first output buffer, and when the second semiconductor element is enabled, the second element output signal and the second In order to control whether or not to enable the first output buffer by one element selection signal, the second output buffer control means controls the output state of the second output buffer based on the first element selection signal. Since the first output buffer control means controls the output state of the first output buffer based on the second element selection signal, the first output buffer and the second output buffer are simultaneously set to the output state. Prevent, Preventing collision of a plurality of data in the force terminal, a first output buffer and the second output buffer is effective to prevent from being destroyed by a collision of the data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 shows an output buffer OIF0 (OIF1 to
FIG. 2 is a block diagram showing a configuration of OIF15, OIS0 to OIS15).

FIG. 3 is a block diagram showing a configuration of the input / output buffer control circuit 3 shown in FIG. 1 (FIGS. 6, 9, and 11).

FIG. 4 is a block diagram showing a configuration of an input / output buffer control circuit 4 shown in FIG.

FIG. 5 is a flowchart showing an operation of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a modification of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of an input / output buffer control circuit 3A shown in FIG.

8 is a block diagram showing a configuration of an input / output buffer control circuit 4A shown in FIG.

FIG. 9 is a block diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 10 is a flowchart showing an operation of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 12 shows an input / output buffer control circuit 3B shown in FIG.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 13 shows an input / output buffer control circuit 4B shown in FIG.
FIG. 3 is a block diagram showing the configuration of FIG.

FIG. 14 is a flowchart showing the operation of the semiconductor memory device according to the third embodiment of the present invention.

FIG. 15 is a conceptual diagram showing an internal structure of a stacked MCP type semiconductor memory device.

FIG. 16 shows a metal ball 106 and an SRAM chip 10
1 (SM, SMA, SMB) bonding pad and FLASH memory chip 102 (FM, FMA, FM)
FIG. 4B is a pattern diagram showing an electrical connection with a bonding pad of FIG.

FIG. 17 is a conceptual diagram showing a connection in a burn-in test of a conventional semiconductor memory device.

FIG. 18 is a conceptual diagram showing a connection in a burn-in test of the stacked MCP type semiconductor memory device.

[Explanation of symbols]

1, 2 address decoder 3, 4, 3A, 4A, 3B, 4B input / output buffer control circuit F, SS memory cell unit FM, FMA, FMB FLASH memory chip SM, SMA, SMB SRAM chip OIF0, ..., OIF15 input / output buffer OIS0,..., OIS15 I / O buffer UT1, UT2,..., UTm Semiconductor storage device UTT1, UTT2,.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B015 HH01 JJ18 JJ44 KB33 RR07 5B025 AA01 AA07 AD05 AD15 AE09 5L106 AA02 AA10 DD01 DD35 EE03 GG05

Claims (10)

[Claims] 1. A semiconductor device in which a plurality of semiconductor elements sharing an output terminal are sealed in one package, wherein: a first semiconductor element; and a first output buffer provided in the first semiconductor element. A second semiconductor device having a second output buffer connected to a common output terminal, and an output state of the first output buffer based on a first control signal supplied to the first semiconductor device. A first output buffer control means for controlling a second control signal supplied to the second semiconductor element, and an output state of the second output buffer based on the first control signal. A semiconductor device comprising: a second output buffer control unit. 2. The second output buffer control means, wherein the second control signal activates the second output buffer when the first control signal activates the output of the first output buffer. 2. The semiconductor device according to claim 1, wherein the output state of the second output buffer is set to a high-impedance state when the state described above is satisfied. 3. A first element selection signal for controlling whether or not the first control signal enables the operation of the first semiconductor element, and whether the first output buffer is enabled. A first element output signal that controls whether or not the second element selection signal controls whether or not the second control signal enables the operation of the second semiconductor element. 3. The semiconductor device according to claim 1, further comprising a second element output signal for controlling whether or not the second output buffer is enabled. 4. The first output buffer according to the first element output signal when the first semiconductor element is enabled by the first element selection signal. Whether the second output buffer is enabled by the second element output signal and the first element selection signal when the second semiconductor element is enabled. 4. The semiconductor device according to claim 1, wherein the control is performed. 5. A semiconductor device in which a plurality of semiconductor elements sharing an output terminal are sealed in one package, wherein: a first semiconductor element; and a first output buffer provided in the first semiconductor element. A second semiconductor element having a second output buffer connected to a common output terminal, and a first control signal supplied to the first semiconductor element and a second control signal supplied to the second semiconductor element. Based on the second control signal, first output buffer control means for controlling the output state of the first output buffer, based on the first control signal and the second control signal,
A semiconductor device comprising: a second output buffer control unit that controls an output state of the second output buffer. 6. When the first control signal is in a state of validating the output of the first output buffer, and when the second control signal is in a state of validating the second output buffer, And when the second control signal is in the state of validating the output of the second output buffer, when the first control signal is in the state of validating the first output buffer, the first control signal 6. The output buffer control means sets the first output buffer to a high impedance state, and the second output buffer control means changes the output state of the second output buffer to a high impedance state.
13. The semiconductor device according to claim 1. 7. When both the first output buffer and the second output buffer are in a high-impedance state, and the first control signal first makes the output of the first output buffer valid, The second output buffer control means keeps the second output buffer in a high impedance state even when the second control signal makes the second output buffer valid, and conversely, When the second control signal is in a state of validating the output of the second output buffer, the first output buffer control means is in a state in which the first control signal validates the first output buffer. 6. The semiconductor device according to claim 5, wherein the first output buffer remains in a high impedance state. 8. The first output buffer and the control means, wherein the second output buffer control means determines which one of the first control signal and the second control signal is to be transmitted first to the first output buffer and the second control signal, respectively. 8. The semiconductor device according to claim 7, further comprising a latch circuit for storing whether the second output buffer is enabled. 9. A first element selection signal for controlling whether or not the first control signal enables an operation of the first semiconductor element, and whether or not to enable a first output buffer. And a first element output signal for controlling the
A second element selection signal for controlling whether the second control signal enables the operation of the second semiconductor element and a second element for controlling whether to enable the second output buffer; 9. The semiconductor device according to claim 5, wherein the semiconductor device comprises: 10. The first element output signal and the second element when the first semiconductor element is enabled by the first element selection signal. A control signal controls whether or not to enable the first output buffer. When the second semiconductor device is enabled, the first output buffer is enabled by the second device output signal and the first device selection signal. 10. The semiconductor device according to claim 5, wherein whether the output buffer is enabled is controlled.