JP2011233195A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which an erroneous writing is prevented even if a writing operation instruction signal is erroneously inputted thereto when an operation state of a circuit in an LSI is unstable.SOLUTION: The semiconductor device comprises: a VPRG level detection circuit 4 which detects the voltage level of a power-supply terminal VPRG for writing; a W/R control circuit 5 which produces a writing control signal WE and a reading control signal RE in accordance with a detection signal IVPRG from the VPRG level detection circuit, a writing instruction signal PRGE, and a clock signal CLK; and an internal power switch circuit 6 which receives the power-supply voltage of a first power-supply terminal VDD33 and the power-supply terminal VPRG and selects VPRG when writing or VDD33 except when writing to output the selected level as VPP in accordance with the writing control signal WE. An anti-fuse memory cell array 7 is provided with a switch which is connected between VPP and a bit line and turned on or off in accordance with writing data DIN and the writing control signal WE.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a nonvolatile memory device.

  Among so-called one-time programmable memories using a non-volatile memory element in which data can be written only once, an anti-fuse element has a high voltage applied to the anti-fuse element during data writing. Application is performed to change the antifuse element from an insulated state (a non-conductive state between both ends of the antifuse element) to a connected state (a conductive state between both ends of the antifuse element), so that writing is performed only once. In a semiconductor device equipped with an antifuse element, data writing (program) to the antifuse element is performed, for example, in a wafer test process of the semiconductor device.

  When the internal state of the semiconductor device is unstable, such as when the power is turned on after assembly of a semiconductor device such as an LSI or after product shipment, a high voltage is applied to the antifuse element in an insulated state, and the antifuse element is There is a possibility of breaking the original data (insulated state) due to the connection state. Note that the antifuse element cannot be rewritten in the sense that once it is set to a connected state by writing logic 1 data, for example, it cannot be rewritten, but for example logic 0 An antifuse element that remains in an insulated state by writing data may be set to a connected state by application of a high voltage, that is, erroneously written, when in an unstable state such as when the power is turned on.

  In relation to a nonvolatile memory element that cannot rewrite data, such as an antifuse element, Patent Document 1 discloses a nonvolatile memory element that cannot rewrite data, and reads data from the nonvolatile memory element. A read operation instruction signal for instructing the start of the read operation for reading in synchronization with the external input clock, and a write instruction signal for instructing the start of the write operation for writing data to the nonvolatile memory element A write operation control circuit that is input asynchronously with respect to the external input clock, and a reset circuit that resets the operation of the read operation control circuit in response to the supply of the write instruction signal. A configuration is disclosed in which the constituent elements can be prevented from being destroyed. In Patent Document 1, when a write instruction signal is input, the operation of the read operation control circuit is immediately reset, and a high voltage is applied to the read circuit or the like to prevent the element from being destroyed. In FIG. 1 and the like of Patent Document 1, the antifuse element is connected between the power supply VDD and the storage node SN, and on / off is controlled between the storage node SN and the negative potential VBP by the output of the write operation control combination circuit. The write gate (nMOS transistor) to be connected is connected.

JP 2008-65963 A (P2008-65963A)

  The analysis of related technology is given below.

  If the operation state of a circuit inside a semiconductor device (eg, LSI) is unstable, such as when the power is turned on, if a write instruction signal is erroneously input, a high voltage is applied to the antifuse element, and erroneous writing is performed. there is a possibility.

  SUMMARY An advantage of some aspects of the invention is to solve at least one of the problems described above, and the structure is as follows.

According to one aspect of the present invention, a write power supply terminal and a non-volatile storage element are provided. In a data write process, a write voltage applied to the write power supply terminal from the outside of a semiconductor device is supplied to the non-volatile memory. Data is written by applying to the storage element of
When the voltage level of the write power supply terminal is monitored and the write power supply terminal is a voltage that does not satisfy the condition of the write voltage, even if a write instruction is generated, A circuit block that keeps a write control signal that controls writing of data inactive,
A semiconductor device is provided in which the power supply terminal for writing is electrically coupled to a predetermined terminal that is set to a fixed potential that does not satisfy the condition of the writing voltage, after the data writing step.

  According to the present invention, when the operation state of the circuit inside the semiconductor device is unstable, even if the write instruction signal is erroneously input, no erroneous write is performed.

It is a figure which shows an example of a structure of the semiconductor device of one Embodiment of this invention. It is a figure which shows the setting at the time of the wafer test of the semiconductor device of one Embodiment of this invention. It is a figure which shows the setting at the time of the assembly of the semiconductor device of one Embodiment of this invention. FIG. 2 is a diagram illustrating an example of a configuration of a VPRG level detection circuit of FIG. 1 and a W / R control circuit of FIG. FIG. 2 is a diagram illustrating an embodiment of a circuit that exchanges signals with the antifuse macro of FIG. 1. FIG. 2 is a diagram illustrating an example of a configuration of an internal power switch circuit and an antifuse cell in FIG. 1. It is a figure which shows the applied voltage of a VPRG terminal by a list. It is a timing waveform diagram which shows the operation example of a comparative example. FIG. 6 is a timing waveform diagram showing an operation example of an embodiment of the present invention. It is a figure which shows the structure of the VPRG level detection circuit of another Example of this invention.

  An embodiment of the present invention will be described. In one of preferred embodiments (MODES), the present invention provides a power supply for writing in a semiconductor device including a nonvolatile memory element in which data is written by applying a predetermined writing voltage, such as an antifuse element. The terminal (VPRG) is electrically coupled to a terminal that applies a predetermined fixed potential that does not satisfy the condition of the writing voltage of the nonvolatile memory element, for example, a ground terminal, for example, after the data writing process.

  In one aspect (MODES) of the present invention, when the voltage level of the write power supply terminal (VPRG) is monitored and the write power supply terminal (VPRG) is a voltage that does not satisfy the condition of the write voltage, A circuit group (circuit block) is provided that keeps a write control signal (WE) that controls writing of data to the nonvolatile memory element inactive without being activated even when a write instruction is generated.

In one embodiment of the present invention (MODES), the semiconductor device includes:
A VPRG level detection circuit (4) for detecting the voltage level of the power supply terminal (VPRG) for writing;
The detection result signal (IVPRG) from the VPRG level detection circuit (4), the write instruction signal (PRGE) for controlling the write instruction, and the clock signal (CLK) are received, and the write control signal (WE) and the read control signal (RE). W / R control circuit (5) for controlling activation and deactivation of
When the power supply voltage of the first power supply terminal (VDD33) and the power supply voltage of the power supply terminal for writing (VPRG) are received and the write control signal (WE) is in the active state, the voltage of the power supply terminal for writing (VPRG) When the write control signal (WE) is inactive, the internal power switch circuit (6) that selects the voltage of the power supply terminal VDD33 and outputs it to the high voltage terminal (VPP) of the cell array (7);
A cell transistor (disposed at the intersection of the word line (WL) and the bit line (BL)) that is turned on when the word line (WL) is selected and connects the nonvolatile memory element (76) to the bit line (BL). 75) and a non-volatile storage element (76), a memory cell (74),
A switch (72) connected between the output (VPP) of the internal power switch circuit (6) and the bit line (BL);
The nonvolatile memory element receives write data (DIN) and a write control signal (WE), the write control signal (WE) is in an active state, and the write data (DIN) is logic 1 or 0 When the data (76) is one data that changes the state (for example, logic 1 data), the switch (72) is turned on, and the output (VPP) of the internal power switch circuit (6) and the bit line ( BL)
When the write control signal (WE) is in the active state and the write data (DIN) is the other data of the logical paths 1 and 0 (for example, logic 0), or the write control signal (WE) is inactive A logic circuit (71) is provided that turns off the switch (72) when in a state and makes the output (VPP) of the power supply switching circuit and the bit line non-conductive. In one embodiment of the present invention, the semiconductor device includes a read circuit (77) that generates read data (DOUT) from a voltage read from the memory cell to the bit line (BL). In the following, description will be made in accordance with examples.

  FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention. FIG. 1 shows the configuration (circuit arrangement) of a semiconductor device (LSI chip) 1 in a state before connecting a power supply pad VPRG for writing to a ground terminal. The antifuse macro 3 includes an antifuse cell array 7, a VPRG level detection circuit 4, a W / R control circuit 5, and an internal power switch circuit 6. The antifuse cell array 7 includes a plurality of antifuse elements (not shown) arranged in an array.

  The VPRG level detection circuit 4 monitors the voltage level of the power supply pad VPRG for writing and supplies a level detection signal (binary signal) IVPRG to the W / R control circuit 5.

The W / R control circuit 5
Data input (write data) DIN,
A write instruction signal PRGE,
A clock signal CLK;
A VPRG detection signal IVPRG from the VPRG level detection circuit 4;
Enter
At the time of data writing, the write enable signal (write control signal) WE is activated and output,
At the time of data reading, a read enable signal RE (read control signal) is activated and output. Although not particularly limited, the write enable signal WE and the read enable signal RE are active (active state) when High and inactive (inactive state) when Low.

  The internal power supply switch circuit 6 is a circuit that receives the power supply voltage VPRG for writing and the power supply voltage VDD33 for standard I / O circulation and switches the voltage (high voltage) VPP supplied to the antifuse cell array 7. The internal power switch circuit 6 applies VPRG to the high voltage terminal VPP at the time of writing and VDD33 to other than the time of writing.

  FIG. 2 shows an example of a semiconductor device (LSI) on a wafer when data is written in a wafer test process for testing a chip on a wafer using a tester and a wafer prober (not shown). The probe 8 of the wafer prober contacts the pad (bonding pad) 2 of the LSI chip 1, and 6.5 V is applied to VPRG and 3.3 V is applied to VDD 33 from the probe 8. Further, writing (programming) is performed in the antifuse cell array (7 in FIG. 1) under the control of the tester and wafer prober. Although not particularly limited, for example, a test of a memory array (not shown) mounted on the LSI chip 1 is performed under the control of a tester and a wafer prober (not shown). In order to perform the replacement, information for replacing the access address to the fail cell with the access address of the redundant cell is programmed in the antifuse cell array (7 in FIG. 1).

  FIG. 3 shows that in this embodiment, after the data writing performed in the wafer test process, in the bonding process of the assembly process, the VPRG pad is bonded to the lead frame 9 of the GND pin (0V) by the bonding wire 10. Shows the state. The power supply pad of VDD 33 is wire bonded to the lead frame 9 of the power supply pin. FIG. 3 shows a QFP (Quad Flat Package) type package in which metallic connection terminals extend in four directions from each rectangular side of the semiconductor device (LSI chip) 1. Various packages such as a dual inline package (PGA), a pin grid array (PGA), a ball grid array (BGA), and a tape carrier package (TCP) type can be similarly applied.

  FIG. 4A shows an example of the configuration of the VPRG level detection circuit 4 in FIG. The VPRG level detection circuit 4 has an input connected to the VPRG pad, an inverter INV1 that outputs a low potential when the voltage of the VPRG pad is equal to or higher than a threshold, and a high potential when the voltage of the VPRG pad is lower than the threshold, and an inverted signal that receives the output of the inverter INV1 Is provided as an inverter INV2. When the voltage of the VPRG pad is not at the GND level (when the threshold value of INV1 is exceeded), a high potential IVPRG is output from the VPRG level detection circuit 4, and when the voltage of the VPRG pad is at the GND level, the low potential from the VPRG level detection circuit 4 IVPRG is output. Although not particularly limited, the inverter INV2 whose input is connected to the VPRG pad is driven by the power supply voltage VDD33 (3.3V) for I / O, and the inverter INV2 is driven by an internal power supply voltage (VDD = 1. 5V), and the level detection signal IPRG as an output thereof may be a binary signal having an amplitude of 0 to 1.5V.

FIG. 4B is a diagram showing an example of the configuration of the W / R control circuit 5 of FIG. The W / R control circuit 5
The IVPRG output from the VPRG level detection circuit 4, the write instruction signal PRGE (active state at high potential) output from the internal circuit (eg, an antifuse controller described later) of the LSI chip 1, and the clock signal CLK are input. NAND circuit NAND1;
An inverter INV4 that outputs a signal obtained by inverting the output of the NAND1 as a write enable signal WE;
A NAND circuit NAND2 for inputting a signal obtained by inverting PRGE by the inverter INV3 and the clock signal CLK;
An inverter INV5 that outputs a signal obtained by inverting the output of the NAND2 as a read enable signal RE;
It has.

  When (IVPRG, PRGE, CLK) = (High, High, High), WE = High (active state: write operation is performed), and otherwise, WE = Low (inactive state).

  When (PRGE, CLK) = (Low, High), RE = High (active state: read operation is performed), and otherwise, RE = Low (inactive state).

  FIG. 5 is a diagram illustrating an example of a circuit block that exchanges data, control signals, and the like with the antifuse macro 3 of FIG. The antifuse controller 11 gives write data DIN, a write instruction signal PRGE, and a clock CLK to the antifuse macro 3. The reset signal RST input to the antifuse controller 11 is activated by a reset circuit (not shown) after a predetermined clock cycle has elapsed after power-on, and the antifuse controller 11 is reset in response to the activation. Read data DOUT from the antifuse macro 3 is stored in the volatile storage device 12. Although not particularly limited, as the storage device 12, for example, an SRAM redundancy register that holds replacement address information for repairing defective cells of an SRAM (Static Random Access Memory) mounted on the same chip as the antifuse macro 3 or the like Is used.

  When the internal state of the LSI chip before activation of the reset signal RST is unstable, such as when the power is turned on, the write instruction signal may be erroneously input to the antifuse macro 3. In this embodiment, As described above, since the VPRG pad is connected to GND in the assembly process after the completion of data writing, IVPRG output from the VPRG level detection circuit 4 is fixed to Low (ground potential). For this reason, even when the internal state of the LSI chip is unstable, such as when the power is turned on, the write enable signal WE output from the W / R control circuit 5 is fixed to Low to avoid erroneous writing to the antifuse element. Is done.

  FIG. 6A shows an example of the configuration of internal power switch circuit 6 in FIG. As shown in FIG. 6A, the internal power switch circuit 6 includes a pMOS transistor 61 having a source connected to a power supply VDD33 (= 3.3V) and a gate connected to a write enable signal WE, and a power supply for writing. A pMOS transistor 62 having a source connected to VPRG (= 6.5V) and a gate connected to a signal obtained by inverting the write enable signal WE by the inverter 63, and the drains of the pMOS transistors 61 and 62 are connected in common. The antifuse cell array 7 is connected to the VPP terminal (high voltage terminal).

  FIG. 6B is a diagram showing a main configuration of the antifuse cell array 7. Note that in FIG. 6B, for ease of explanation, one cell, one bit line BL, and one word line WL are shown, and a plurality of bit lines and intersections of a plurality of word lines are shown. A plurality of cells arranged in a matrix are omitted.

  Referring to FIG. 6B, a NAND circuit 71 (NAND) 71 for inputting DIN and write enable signal WE, a source connected to the VPP terminal, a gate connected to the output of NAND 71, and a drain connected to bit line BL are connected. The pMOS transistor 72 is provided. When DIN = High and WE = High, that is, when writing logic 1 data, the output of the NAND 71 becomes Low, the pMOS transistor 72 becomes conductive, and the potential of the bit line BL becomes the potential of the VPP terminal.

  The word driver 73 that drives the selected word line WL sets the selected word line WL to the GND potential. Unselected word lines are held at the high voltage VPP.

  The memory cell 74 has an antifuse element (AF) 76 connected to GND, a gate connected to the word line WL, a source connected to the bit line BL, and a drain connected to one end of the antifuse element (AF) 76. The pMOS transistor 75 (cell transistor) is provided.

  The selected word line WL is driven to the Low potential by the word driver 73, the pMOS transistor 75 is turned on, and the voltage (= VPRG) of the bit line BL is applied to the antifuse element (AF) 76 at the time of data writing. The both ends of the antifuse element (AF) 76 are connected).

  At the time of data reading, the read enable signal RE from the W / R control circuit 5 (see FIG. 1) is set to a high potential (active state), and the write enable signal WE is set to a low potential (inactive state). For this reason, the output of the NAND 71 becomes High, and the pMOS transistor 72 is turned off (non-conducting). In addition, for example, in response to the transition of the read enable signal RE from Low (inactive state) to High (active state), the reading is performed before the selection of the word line WL (at the time before being driven to the Low potential). The circuit 77 precharges the bit line BL to a predetermined voltage (for example, VBP = 2.2V). In the example shown in FIG. 6B, the bit line precharge circuit (not shown) is included in the read circuit 77 driven by the power supply VBP, and the power supply VBP is connected to the bit line BL. As a result, the bit line BL is precharged.

  After the bit line BL is precharged, the address is decoded by an address decoder (not shown). As a result, the selected word line WL is driven to the low potential (GND) by the word driver 73. The pMOS transistor 75 of the memory cell 74 whose gate is connected to the word line (WL) driven to the low potential is turned on. For example, in the memory cell 74 in which logic 1 is written, the bit line BL connected to the memory cell 74 is electrically connected to GND via the pMOS transistor 75 in the on state and the antifuse element (AF) 76 in the connected state. It becomes a potential. In the memory cell 74 in which logic 0 is written, since the anti-fuse element (AF) 76 is in an insulating state, even if the pMOS transistor 75 is turned on, the bit line BL is at the precharge voltage VBP (= 2.2 V). It remains.

  The read circuit 77 compares the voltage of the bit line BL with a reference voltage VREF (for example, an intermediate potential between 0V and 2.2V), and outputs a comparison result as binary read data DOUT (comparator). including.

Although not particularly limited, the read circuit 77 is configured such that when the voltage read from the memory cell 74 to the bit line BL is a voltage (GND potential) lower than VREF (both ends of the antifuse element are connected).
DOUT = High (eg, logic 1),
When the voltage of the bit line BL is the precharge voltage VBP (= 2.2 V) (both ends of the antifuse element are in an insulated state),
DOUT = Low (eg, logic 0)
Is output. The output DOUT of the readout circuit 77 may be a logic signal having an amplitude of 0 to 1.5V, for example. Although not particularly limited, in this embodiment, when the read enable signal RE is Low, the read circuit 77 is inactivated (the precharge circuit and the voltage comparison circuit are both off), and the output of the read circuit 77 is turned off ( Hi-Z state).

  At the time of data writing when the write enable signal WE is at a high level, VPRG (6.5 V) is selected as the output of the VPP terminal in the internal power switch circuit 6, and at the time of data writing at DIN = High (usually a wafer test process) VPRG (6.5 V) supplied from the bit line BL to the source of the pMOS transistor 75 of the memory cell 74 connected to the selected word line WL is turned on in the on state pMOS transistor 75. Is applied to one end of the anti-fuse element (AF) 76, and what is in an insulated state becomes a connected state (a conductive state is provided between both ends of the anti-fuse element (AF) 76).

  When the write enable signal WE is Low, VDD 33 is applied to the VPP terminal in the internal power switch circuit 6.

  By the way, unlike the present invention, such as after the assembly process or after product shipment, when 3.3 V, which is the same as VDD33, is applied to the write power supply terminal VPRG, the write enable signal WE becomes High due to a malfunction such as when the power is turned on. When DIN becomes High, the pMOS transistor 72 in FIG. 6B is turned on, and 3.3 V is applied to the antifuse element 76 of the memory cell 74 connected to the word line WL that has become the bit line BL and Low. It will be. As a result, the data of the antifuse element 76 may be destroyed.

  On the other hand, according to the present embodiment, the write power supply terminal VPRG is connected to the GND pin, and when the power is turned on, the output IVPRG of the VPRG level detection circuit 4 is at the Low level. Even if the signal PRGE becomes High, the write enable signal WE output from the W / R control circuit 5 is fixed to Low, the output of the NAND 71 in FIG. 6B is fixed to High, and the pMOS transistor 72 is turned off. Thus, writing to the antifuse element 76 is not performed. Further, the precharge voltage (for example, VBP) of the bit line BL is only applied to one end of the anti-fuse element 76 of the memory cell 74 selected as the data read target via the pMOS transistor 72 in the on state. The data of the antifuse element 76 is not destroyed.

  FIG. 7 summarizes the potentials of the VPRG terminals after assembly during the wafer test in this embodiment. At the time of programming (writing) during the wafer test, the VPRG terminal is fixed at 6.5V and the others are fixed at 0.0V. At the time of package assembly, the VPRG terminal is connected to the GND terminal, and thereafter, the VPRG terminal is set to the GND potential.

  FIG. 8 is a timing chart for explaining a timing operation at the time of power-on in a configuration in which the write power supply terminal VPRG is not connected to the GND pin after the data write process as a comparative example (the horizontal axis is time). The reset signal RST before and after the rise of the power supply VDD (see FIG. 5), the write instruction signal PRGE from the antifuse controller 11 in FIG. 5, the clock signal CLK, the write enable signal WE from the W / R control circuit 5 in FIG. A hatched portion of the 6 (B) bit line BL represents a portion having an indefinite value. The reset in the LSI chip is performed by the reset signal RST, and the normal operation (reading operation) is performed by releasing the reset (RST = High). In addition, the clock signal CLK from the antifuse controller 11 is supplied to the antifuse macro 3 by releasing the reset (RST = High). When the power supply VDD is in an unstable state (hatched time range), 3.3 V may be applied to the bit line BL of the antifuse cell array.

  That is, in FIG. 6B, in an unstable state when the power supply VDD is turned on, the pMOS transistor (pMOS switch) 72 is turned on when the write enable signal WE is accidentally high and DIN is accidentally high, and the VPP terminal Since the power supply voltage VDD33 is applied to the bit line BL, 3.3V of the power supply voltage VDD33 is applied to the bit line BL. When the word line WL accidentally becomes a low potential, 3.3 V of the bit line BL is applied to one end of the anti-fuse element 76 of the memory cell 74, and when the anti-fuse element 76 is in an insulating state, the connection state is erroneously written. There is a possibility that.

  FIG. 9 is a diagram for explaining the timing operation when the power is turned on after the write power supply terminal VPRG is connected to the GND pin in this embodiment. In the present embodiment, as described above, the write power supply terminal VPRG is connected to the GND pin in the packaging process after the data write process in the wafer test or the like. 9 shows the reset signal RST (see FIG. 5) in the above-described embodiment, the write instruction signal PRGE from the antifuse controller 11 in FIG. 5, the clock signal CLK, and the comparison example in FIG. An example of a timing waveform at the time of power-on of the write enable signal WE from the W / R control circuit 5 and the bit line BL signal in FIG. 6B is shown.

  In FIG. 9, the write enable signal WE is fixed to Low in the hatched time range when the power is turned on, the pMOS transistor 72 of the antifuse cell array in FIG. 6B is turned off (non-conductive), and the bit line The high voltage VPP (3.3V of VDD33) is not applied to BL, and the maximum voltage applied to the bit line BL is 2.2V (precharge voltage). Therefore, according to the present embodiment, erroneous writing of the antifuse element 76 is avoided when the power is turned on.

FIG. 10 is a diagram illustrating a configuration example of the VPRG level detector 4 according to another embodiment of the present invention. A voltage comparator for comparing the voltages of VDD33 and VPRG is provided. Although not particularly limited,
When VPRG> VDD33, IVPRG = High (eg, logic 1),
When VPRG = <VDD33, IVPRG = Low (eg, logic 0)
Is output. As described above, IVPRG may be 0-VDD (internal power supply voltage: 1.5 V).

  Since the voltage comparator receives 6.5 V when writing data in the wafer test process, the power supply of the voltage comparator is set to VPRG and VSS (GND) when writing data in order to secure an input dynamic range. After the VPRG pad is connected to GND, VDD33 and VSS (GND) are supplied to the power supply of the voltage comparator.

  In the above embodiment, an antifuse element is described as an example of a non-rewritable nonvolatile memory element. However, the present invention is similarly applied to a semiconductor device including a fuse element that is blown / not blown according to a data value. Is possible.

  In the above embodiment, an SOC (System On Chip) LSI including an antifuse macro, SRAM and the like has been described as an example. However, the present invention is not limited to the SOC, and is applied to an individual semiconductor having an antifuse cell array. Of course, you may do.

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the examples and the examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 1 LSI chip 2 Bonding pad 3 Antifuse macro 4 VPRG level detection circuit 5 W / R control circuit 6 Internal power switch circuit 7 Antifuse cell array 8 Probe
9 Lead frame 10 Bonding wire 11 Antifuse controller 12 Volatile memory device (SRAM redundancy register)
61, 62 pMOS transistor 63 inverter 71 NAND
72 pMOS transistor 73 word driver 74 cell (antifuse memory cell)
75 pMOS transistor 76 antifuse element 77 readout circuit

Claims (9)

Power supply terminal for writing,
A non-volatile storage element;
With
In the data writing process, data is written by applying a voltage for writing applied to the writing power supply terminal from the outside of the semiconductor device to the nonvolatile memory element,
When the voltage level of the write power supply terminal is monitored and the write power supply terminal is a voltage that does not satisfy the condition of the write voltage, even if a write instruction is generated, A circuit unit that keeps a write control signal that controls writing of data inactive,
The semiconductor device according to claim 1, wherein the write power supply terminal is electrically coupled to a predetermined terminal set to a fixed potential that does not satisfy the write voltage condition after the data writing step.   2. The semiconductor device according to claim 1, wherein the predetermined terminal to which the write power supply terminal is electrically coupled is a ground terminal.   In the data write step, the circuit unit monitors the voltage of the write power supply terminal, and as a result, when the voltage of the write power supply terminal satisfies the condition of the write voltage, the circuit unit responds to the generation of the write instruction. The semiconductor device according to claim 1, wherein the write control signal is activated. A level detection circuit for detecting a voltage level of the power supply terminal for writing;
Activation of the write control signal and a read control signal for controlling reading of data from the nonvolatile memory element based on a detection signal from the level detection circuit and a write instruction signal for controlling the write instruction And a write / read control circuit for controlling deactivation,
The voltage of the first power supply terminal and the voltage of the power supply terminal for writing are received, and based on the write control signal, the voltage of the power supply terminal for writing is selected and output at the time of data writing, A power supply switching circuit for selectively outputting the voltage of the first power supply terminal;
A memory that is disposed at an intersection of a word line and a bit line and includes a cell transistor that is turned on when the word line is selected and connects the nonvolatile memory element and the bit line, and the nonvolatile memory element Cell,
A switch connected between the output of the power supply switching circuit and the bit line;
In response to write data and the write control signal, the write control signal is in an active state, and the write data is one of logic 1 and 0 that changes the connection state of the nonvolatile memory element. When the switch is turned on, the output of the power supply switching circuit and the bit line are conducted,
When the write control signal is in an active state and the write data is the other data of logical path 1 and 0,
Or a logic circuit that turns off the switch when the write control signal is in an inactive state, and makes the output of the power supply switching circuit non-conductive with the bit line;
The semiconductor device according to claim 1, further comprising:   5. The semiconductor device according to claim 4, further comprising a read circuit that generates read data from a voltage read from the memory cell to the bit line. The level detection circuit includes a first inverter circuit that receives the voltage of the write power supply terminal at an input terminal;
A second inverter circuit that receives the output of the first inverter circuit and outputs a detection signal;
The semiconductor device according to claim 4, wherein the semiconductor device is provided. The level detection circuit includes:
6. The semiconductor device according to claim 4, further comprising a comparator circuit that compares the voltage of the power supply terminal for writing with a predetermined power supply voltage.   3. The semiconductor device according to claim 2, wherein in the assembly process, the pad constituting the power supply terminal for writing is connected to a ground pin.   9. The semiconductor device according to claim 1, wherein the nonvolatile memory element includes an antifuse element that is changed from an insulating state to a connected state by data writing.

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