JP2000235788A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of address signal lines and data lines to be wired, to make the wiring simplified, to reduce circuit area, and to facilitate timing control. SOLUTION: In a semiconductor memory having a block-write function and a column mask function, by providing an AND gate 6 and an OR gate 7 in a Y main decoder 2 as a means setting a column mask, at the time of performing block-write, all bit low level signals have only to be sent to the Y main decoder 2 from a pre-decoder 1 to perform block-write. It is not required for signals, whose different column masks are already set for each main decoder, to be sent individually. And also, data for setting the column mask have not to be sent to a control circuit having the pre-decoder 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a so-called block write function in which a plurality of columns are regarded as one block and specific data is selectively and simultaneously written into memory cells corresponding to the block. It is suitable for use in a semiconductor memory device having

[0002]

2. Description of the Related Art Conventionally, in a conventional semiconductor memory device, when data is written, in a certain write cycle, data previously input and held in a register called a color register is stored in a matrix-like memory cell. Is configured to be written in one column.

On the other hand, a semiconductor having a block write function in which a plurality of columns can be regarded as one block and specific data can be simultaneously written to memory cells of a plurality of columns constituting the block. Storage devices have also been proposed. By using such a block write function, data processing of an arbitrary area can be performed at high speed, for example, in the case of a graphics processing in which an image of an arbitrary area on a display screen is painted with a certain color.

In such a block write function, specific data is all written into each column in a selected block at the same time, so that the processing speed is high as described above, but the degree of freedom in writing data is low. Become. Therefore,
In a certain block write cycle, a so-called column mask function has been proposed as a function of controlling execution of writing performed for each column for a plurality of columns constituting one block that executes writing simultaneously.

The column mask function is a function of allocating I / O to each column in a block and controlling execution of data writing. For example, when the data of the assigned I / O is at a high level, data writing is executed in the corresponding column, and when it is at a low level, data writing is executed in the corresponding column. It is controlled not to be performed.

FIG. 4 is a diagram showing a configuration example of a conventional semiconductor memory device having the above-described block write function and column mask function. FIG. 4 shows an example of a semiconductor memory device in a case where the number of columns in one block to which data is simultaneously written is eight.

As shown in FIG. 4, the number of columns in the Y direction is two.
Assuming that the number is 56, the column address (Y address) input from the outside is 8 bits A _{0 to} A ₇ .
The Y addresses A _{0 to} A ₇ are input to the predecoder 41. The predecoder 41 receives the input Y address A
_{0 to} A ₇ are lower 3 bits A _{0 to} A ₂ , middle 3 bits A ₃
To A _5, divided into three group of upper two bits _A 6 to A _7, by performing a decoding process on each
8-bit lower Y address A ₀₁₂ , 8-bit middle Y
The address A ₃₄₅ outputs a 4-bit upper Y address A ₆₇ .

The Y main decoder 42 includes the lower Y address A ₀₁₂ , middle Y address A ₃₄₅ and upper Y address
By performing an AND operation on each of the three inputs of the address A ₆₇ by one bit, 256 column selection signals Y from a total of 20 pre-decoded Y addresses are obtained.
_S0 to _YS255 are generated. This column selection signal Y
_S0 to Y _S255 column select line is outputted (hereinafter indicated by appropriate _Y S0 _{to Y S255} Again select line), the sense amplifier _SA 0 -SA connected one-to-one thereto
₂₅₅ has a function of selectively connecting the common I / O line 43 to the common I / O line 43.

That is, when any of the column selection signals among Y _{S0 to} Y _S255 goes high, the sense amplifier connected to the column selection line is driven, and the common I / O
It is electrically connected to the O line 43. The common I / O line 43 is connected to a main amplifier 46 for reading data and a write amplifier 47 for writing data via a precharge circuit 45, and a memory cell 44 (FIG. 4) via a bit line BL. (Only one is shown as a representative). With such a configuration, the bit line BL connected to the driven sense amplifier and the common I
Data is read from or written to the memory cell 44 of the column via the / O line 43.

An OR gate 48 is provided at the output stage of the predecoder 41, and an 8-bit lower Y address _A012 of all outputs of the predecoder 41 is inputted. Further, the OR gate 48 has an AND gate 49.
Are also input. The OR gate 48 outputs 1 to the corresponding bits for the lower Y address A ₀₁₂ of 8 bits and the output signal of the AND gate 49, respectively.
The result is ORed bit by bit and output to the Y main decoder 42.

Here, the AND gate 49 ANDs the 8-bit column mask signal and the block write flag one bit at a time. The block write flag is
When a block write for simultaneously writing the same data to each memory cell 44 in a block composed of eight columns is performed, the level is set to a high level (hereinafter, also simply referred to as “1”). When the block write is not performed, it is set to a low level (hereinafter, also simply referred to as “0”). In the column mask signal, a portion to be masked out of the 8 bits is set to “0”, and the rest is “1”.
Is set to

Therefore, when the block write is not performed, the output signal of the OR gate 48 is the same as the lower Y address A ₀₁₂ output from the predecoder 41, and
Only one of the bits is "1", and the other seven bits are "0". Similarly, for the middle Y addr A ₃₄₅ and the upper Y address A ₆₇ , only one of the eight bits and one of the four bits are “1”. Thus, the Y main decoder 42 Y _S0 any one column selection line of the to Y _S255 is selected, the writing of data is performed on a single column.

On the other hand, when performing the block write, unless the column mask is performed (all the bits of the column mask signal are "1"), all the eight bits of the output signal of the AND gate 49 become "1". The output signal of 48 also becomes "1" in all bits. As described above, when the block write is performed without performing the column mask, the lower Y address _A012 is completely ignored, and the Y main decoder 4
2, eight column selection lines (for example, column selection lines Y _{S0 to} Y _S7 ) in the block specified from the middle Y address A ₃₄₅ and the high Y address A ₆₇ are collectively selected. As a result, data writing is simultaneously performed on the selected eight columns.

In performing such a block write, if a column mask has been set, the OR gate 48
The 8-bit lower Y adder A ₀₁₂ output from
Since the bit corresponding to the bit position set to “0” in the 8-bit column mask signal is “0”, the corresponding column selection line is not selected. As a result, no data is written on the column selection line, and a column mask is realized.

FIG. 5 is a diagram showing a configuration example of an SGRAM to which the semiconductor memory device shown in FIG. 4 is applied. In the example of FIG. 5, the SGRAM has two banks, bank 0 and bank 1, each of which is B0, B1, B2,
B3 consists of four bytes. FIG. 4 shown above corresponds to the configuration of a memory circuit having only one byte.

As shown in FIG. 5, each byte B0, B1,
B2 and B3 each have one amplifier 51 and one Y
A main decoder 52 is provided. Amplifier 51
The precharge circuit 45 and the main amplifier 46 shown in FIG.
And a write amplifier 47. Also, Y
The main decoder 52 corresponds to the Y main decoder 42 shown in FIG.

Further, between bank 0 and bank 1, that is, S
A control circuit 53 is provided at the center of the GRAM. The control circuit 53 controls reading and writing of data for each byte of each bank by sending a command or address to each Y main decoder 52. The predecoder 41, the OR gate 48, and the AND gate 49 shown in FIG.

In FIG. 5, thick solid arrows indicate the flow of addresses, and hatched arrows indicate the flow of data. These addresses and data are exchanged with the outside through a plurality of terminals 54. It is supposed to be. Here, in the above-described column mask function, whether or not to write data to a certain column is determined according to the bit of the data. It is necessary to input a signal to the AND gate 49 in the control circuit 53. Further, it is necessary to input the Y addresses A _{0 to} A ₇ input from the outside to the predecoder 41 in the control circuit 53.

Further, the predecoder 4 in the control circuit 53
It is necessary to output the lower Y address A ₀₁₂ , middle Y address A ₃₄₅ and upper Y address A ₆₇ decoded by 1 to the Y main decoder 52. In this case, since the column mask is performed independently for each byte, the Y main decoder 52 is also required independently for each byte, and the signal lines for outputting the decoded Y addresses A ₀₁₂ , A ₃₄₅ , and A ₆₇ are also provided. , Are required for each Y main decoder 52. Therefore, various data lines and address lines are connected to the control circuit 53 as shown in FIG.

[0020]

FIG. 6 shows a control circuit 53.
FIG. 3 is a diagram showing in detail data lines and address lines connected to the memory cell. As described above, since the column mask is performed independently for each byte, the lower Y address _A012 of 8 bits necessary for specifying the portion to be masked is divided into eight Y main decoders 52 (each bank 0, Each byte B of 1
0, B1, B2, B3). Therefore, eight sets of eight address lines for the lower Y address _A012 are required for the bank 0 and four sets for the bank 1.

On the other hand, the middle Y address A ₃₄₅ and the upper Y address A ₆₇ can be commonly used in one bank, so that eight address lines for the middle Y address A ₃₄₅ are in bank 0 and bank 1. One set each, top Y
Four sets of four address lines for address A ₆₇ are required for each of bank 0 and bank 1. Accordingly, the address lines for outputting the Y address _{A 012, A 345, A 67} each Y main decoder 52 from the pre-decoder 41 in the control circuit 53, the bank 0 is required by 44 present respective bank 1 .

Further, 8-bit Y addresses A _{0 to} A ₇ which are the source of generating these pre-decoded Y addresses A ₀₁₂ , A ₃₄₅ and A ₆₇ are supplied to the pre-decoder 41 in the control circuit 53. Requires eight address lines. In order to supply mask data for specifying the column mask portion to the control circuit 53,
Two data lines are required. From the above, it is necessary to connect as many as 128 signal lines in total to the control circuit 53.

However, providing such a large number of signal lines requires a correspondingly large area, and has a problem in that the overall circuit scale becomes large. In particular,
The number of address signal lines output from the control circuit 53 to each of the Y main decoders 52 becomes very large, and there is a problem that the wiring area becomes considerably large by arranging these in stripes.

The data lines include a path directly input to each amplifier 51 and a path input to the control circuit 53 for specifying a column mask portion. Since the lengths of these paths are different from each other, it is necessary to control the timing with the corresponding address by two systems, and there is a problem that the timing control is very difficult. In addition, there is a problem that providing two circuits for timing control increases the scale of the circuit.

The present invention has been made in order to solve such a problem. In a semiconductor memory device having block write and column mask functions, the number of address signal lines and data lines to be wired is reduced. Another object of the present invention is to reduce the circuit area and simplify the timing control.

[0026]

According to the present invention, there is provided a semiconductor memory device having a block write function and a column mask function, wherein means for setting a column mask is provided in a main decoder. I do.

According to another aspect of the present invention, there is provided a semiconductor memory device having a block write function and a column mask function, wherein a memory section, a register section for data to be read / written to / from the memory section, and a main decoder for addresses are provided as one set. A plurality of storage units, a control circuit including a pre-decoder of an address, and a control circuit for controlling reading and writing of data in each storage unit; a first setting for setting whether or not to execute a block write in the control circuit; Means, and a second setting means for setting a column mask is provided in each main decoder constituting each storage unit.

According to another aspect of the present invention, the first setting means in the control circuit includes an AND gate for performing an AND operation on an output signal from the predecoder and a flag signal indicating whether or not the block write is executed. When a block write is executed, a signal of the same level for all bits is output from the AND gate. The second setting means in each main decoder outputs data for setting a column mask, an output signal of the AND gate, And an OR gate for calculating the logical sum of

According to the present invention configured as described above, the setting of the column mask is performed in the main decoder, not in a certain portion of the predecoder. It suffices to send a signal of the same level to all bits to perform a block write to the main decoder. For example, when a semiconductor memory device having a plurality of main decoders is configured for one control circuit having a predecoder, the control circuit commonly uses the same level signal for all bits for block write to each main decoder. It is possible to individually set a column mask in each of the main decoders to which the data is sent, so that it is not necessary to individually send a signal with a different column mask set for each main decoder. Further, there is no need to send data for setting a column mask to the control circuit.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a semiconductor memory device according to the present embodiment having a block write function and a column mask function. In FIG. 1, as in the conventional example of FIG.
This is an example of a semiconductor memory device in which the number of columns in one block in which data writing is performed simultaneously at the time of block writing is eight.

In FIG. 1, a predecoder 1 has an 8-bit column address (Y address) input from the outside.
A _{0 to} A ₇ are lower 3 bits A _{0 to} A ₂ , middle 3 bits A
_{3 to} A ₅ and upper two bits A _{6 to} A ₇ are divided into three groups, and a decoding process is performed on each of them to obtain an 8-bit lower Y address A ₀₁₂ , an 8-bit middle Y address A ₃₄₅ , 4-bit upper Y address A
₆₇ is output.

The Y main decoder 2 has an AND gate therein.
A gate 3 is provided, and the above three inputs of the lower Y address A ₀₁₂ , middle Y address A ₃₄₅ and upper Y address A ₆₇ (however, for the lower Y address A ₀₁₂ , the setting of the block write and column mask is appropriately performed. ) Is ANDed one bit at a time, thereby generating 256 column selection signals Y _{S0 to} Y _S255 from a total of 20 pre-decoded Y addresses.

Although not shown in FIG. 1, on the output side of the Y main decoder 2, the sense amplifiers SA _{0 to} SA ₂₅₅ , the bit line BL and the word line W are provided in the same manner as shown in FIG.
L, a common I / O line 43, a memory unit including a memory cell 44 and the like are connected. Further, a precharge unit 45, a main amplifier 46, and a write amplifier 47 are connected to this memory unit.

With such a configuration, Y _S0 -Y _S0
When any one of the column selection signals goes high in _S255 , the sense amplifier connected to the column selection line is driven and is electrically connected to the common I / O line 43. Thereby, the bit line BL connected to the driven sense amplifier is
Data is read from or written to the memory cell 44 in that column via the common I / O line 43.

An AND gate 4 is provided at the output stage of the predecoder 1, and an 8-bit lower Y address _A012 of all outputs of the predecoder 1 is input.
A block write flag is input to the AND gate 4 via an inverter 5. The AND gate 4 performs an AND operation on the lower Y address A ₀₁₂ of 8 bits and the inverted signal of the block write flag one bit at a time, and outputs the result to the Y main decoder 2.

Here, as described in the conventional example, the block write flag is set to "1" when a block write for simultaneously writing the same data to each memory cell in a block composed of eight columns is executed. Is set to When the block write is not performed, it is set to “0”.

Therefore, when the block write is not performed, the output signal of the AND gate 4 becomes the same as the lower Y address _A012 itself output from the predecoder 1, and only one of the eight bits is "1". The other 7 bits are "0". On the other hand, when performing the block write, the output signal of the AND gate 4 has "0" in all eight bits.

As described above, the AND gate 4 and the inverter 5 function as means for setting whether or not to execute the block write. On the other hand, means for setting a column mask when executing block write is provided in the Y main decoder 2 in this embodiment. The AND gate 6 and the OR gate 7 shown in FIG. 1 correspond to this.

The AND gate 6 ANDs the 8-bit column mask signal and the 1-bit block write flag one bit at a time. Here, in the column mask signal, a portion to be masked among the 8 bits is set to “0”, and the other bits are set to “1”. The OR gate 7 outputs the output signal of the AND gate 6 and the AND signal.
The output signal of the gate 4 is ORed bit by bit, and the result is output to the AND gate 3.

Next, the operation will be described. First, when the block write is not performed, the block write flag is set to “0”.
Therefore, the output signal of the AND gate 4 is the same as the lower Y address _A012 output from the predecoder 1, and only one of the eight bits is "1" and the other seven bits are "0". It has become. In addition, since the output signal of the AND gate 6 becomes "0" in all bits, a signal having the same bit arrangement as that of the lower Y address _A012 is input from the OR gate 7 to the AND gate 3.

At this time, other middle Y address A ₃₄₅ and upper Y address A ₆₇ input to AND gate 3
Also, only one of the eight bits and one of the four bits are "1". As a result, any one of the 256 column selection lines is selected by the Y main decoder 2, and data is written to one column.

On the other hand, when performing a block write, the block write flag is set to "1".
Are all "0" bits. Since the output signal of the AND gate 6 has the same bit arrangement as the column mask signal, the same signal as the column mask signal is input from the OR gate 7 to the AND gate 3. Thus, A
Another middle-level Y address A ₃₄₅ input to the ND gate 3
And, in the block specified by the upper Y address A ₆₇ , the block write with the mask set by the column mask signal is realized.

FIG. 2 is a diagram showing a configuration example of an SGRAM to which the semiconductor memory device shown in FIG. 1 is applied. In the example of FIG. 2, the SGRAM has two banks, bank 0 and bank 1, as in the example of FIG. 5, and each bank is composed of four bytes B0, B1, B2, and B3. FIG. 1 shown above corresponds to the configuration of a memory circuit having only one byte.

As shown in FIG. 2, each byte B0, B1,
B2 and B3 each have one amplifier 21 and one Y
A main decoder 2 is provided. The amplifier 21 includes the precharge circuit 45, the main amplifier 46, and the write amplifier 47 shown in FIG.

Further, between bank 0 and bank 1, that is, S
A control circuit 23 is provided at the center of the GRAM. The control circuit 23 controls reading and writing of data with respect to each byte of each bank by sending a command and an address to each Y main decoder 2. Predecoder 1, AND gate 4, and inverter 5 shown in FIG.
Are provided in the control circuit 23.

As described above, in the present embodiment, the setting of the column mask is not performed by the control circuit 23 having the predecoder 1 but individually in each Y main decoder 2 to which the signal relating to the block write is transmitted. To do it. Thus, at the time of execution of the block write, a signal of all bit low levels may be sent in common from the control circuit 23 to each of the Y main decoders 2 in order to perform the block write. It is not necessary to send the set signal individually. Further, the column mask signal is directly sent to each Y main decoder 2 and need not be sent to the control circuit 23.

Therefore, the number of address signal lines output from the control circuit 23 to each Y main decoder 2 can be significantly reduced as compared with the prior art, and
3 can eliminate the data line to be input. As a result, the circuit scale can be reduced by reducing the wiring area, and the timing control can be easily performed by eliminating redundant data line paths via the control circuit 23.

FIG. 3 is a diagram showing the data lines and the address lines of the configuration shown in FIG. 2 in detail. As mentioned above, the column mask is performed independently for each byte,
An 8-bit signal required for setting a mask is generated in each Y main decoder 2, and the control circuit 23 _supplies a lower Y address A _{012 of which} all bits are “0” to each Y main decoder 2.
Can be sent in common. Therefore, the lower Y address A
Only one signal line ₀₁₂ needs to be provided like the signal lines of the middle Y address A ₃₄₅ and the high Y address A ₆₇ .

Therefore, each Y address A ₀₁₂ , A
One set of address lines for ₃₄₅ and A ₆₇ may be provided for bank 0 and one set for bank 1. Thus, the address lines for outputting the Y address _{A 012, A 345, A 67} each Y main decoder 2 from the pre-decoder 1 in the control circuit 23, the bank 0, requires only one by twenty respectively bank 1.

Further, the 8-bit Y addresses A _{0 to} A _{7 from} which these pre-decoded Y addresses A ₀₁₂ , A ₃₄₅ and A ₆₇ are generated are supplied to the pre-decoder 1 in the control circuit 23. Requires eight address lines. However, since it is not necessary to supply the data for the column mask to the control circuit 23, the 32 data lines required in the conventional example of FIG. 6 are not required.

From the above, it is sufficient to connect a total of 48 signal lines to the control circuit 23, and the number of wirings is significantly reduced as compared with the conventional example which requires a total of 128 signal lines. Can be. In the case of the example of FIG. 3, the number of wires is increased by the amount of the data line directly connected to each Y main decoder 2. However, the length of the wires is short and the width of the wires may be 8 bits. There is no particular problem in terms of increasing the scale. Rather, the amount of wiring that can be reduced around the control circuit 23 is larger, and it can be said that the present embodiment is superior to the conventional example shown in FIG.

It should be noted that the shapes and structures of the respective parts shown in the above embodiments are merely examples of the embodiments for carrying out the present invention, and these limit the technical scope of the present invention. It must not be interpreted in a way. That is, the present invention can be embodied in various forms without departing from the spirit or main features thereof.

[0053]

As described above, according to the present invention, since the means for setting the column mask is provided in the main decoder, all the bits are transmitted from the predecoder to the main decoder in order to perform the block write during the execution of the block write. It is only necessary to send a signal of the same level, so that it is not necessary to individually send a signal with a different column mask set for each main decoder, and to send data for setting a column mask to a control circuit having a predecoder. There is no need to send. Accordingly, the number of address signal lines and data lines to be wired can be reduced, and the circuit area can be reduced and the timing control can be simplified.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a diagram showing a configuration example of an SGRAM to which the semiconductor memory device of the embodiment shown in FIG. 1 is applied.

FIG. 3 is a diagram showing data lines and address lines of the configuration shown in FIG. 2 in detail.

FIG. 4 is a diagram showing a configuration example of a conventional semiconductor memory device.

5 is a diagram showing a configuration example of an SGRAM to which the conventional semiconductor memory device shown in FIG. 4 is applied.

FIG. 6 is a diagram showing data lines and address lines connected to the control circuit of FIG. 5 in detail.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Predecoder 2 Y main decoder 3 AND gate 4 AND gate 5 Inverter 6 AND gate 7 OR gate 23 Control circuit

Claims (3)

[Claims] 1. A semiconductor memory device having a block write function and a column mask function, wherein a means for setting the column mask is provided in a main decoder. 2. A semiconductor memory device having a block write function and a column mask function, comprising a plurality of storage units each including a memory unit, a register unit for reading and writing data in the memory unit, and a main decoder for addresses. A control circuit including a predecoder of an address and controlling reading and writing of data in each storage unit; and a first setting unit for setting whether to execute the block write is provided in the control circuit, A semiconductor memory device, wherein a second setting means for setting the column mask is provided in each main decoder constituting each of the storage units. 3. The AND circuit according to claim 1, wherein the first setting means in the control circuit performs an AND operation on an output signal from the predecoder and a flag signal indicating whether or not the block write is executed.
A gate is provided, and when the block write is executed, the AND
The second setting means in each of the main decoders is configured to output a signal of the same level from all the bits from the gate, and the logical sum of the data for setting the column mask and the output signal of the AND gate is provided. 3. The semiconductor memory device according to claim 2, further comprising an OR gate.