JP2000235490A - Microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the availability of an on-chip DRAM. SOLUTION: The bit width of a bus B15 of a DRAM 15 is made wider than the bit width of inside data buses 115 and 116 of a data processing unit 11 and a local data bus B11 for performing access from the data processing unit 11 to a DRAM, and an extended arithmetic unit 12 for executing an arithmetic operation to data whose bit width is wider than that of data operated by an arithmetic unit 113 in the data processing unit 11 and an extended data bus B12 whose bit width is wide connected with the extended arithmetic unit 12 are provided on the same LSI. Then, the connection of the data bus is switched by a bus selector 13 so that one part of the DRAM bus B15 can be connected with the local data bus B11 at the time of performing access from the data processing unit 11 to the DRAM 15 and the DRAM bus B15 can be connected with the extended data bus B12 at the time of performing access from the extended arithmetic unit 12 to the DRAM 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-scale integrated circuit (LSI) in which a dynamic random access memory (herein referred to as DRAM) and a microprocessor are integrated.
It relates to a microprocessor arranged on a chip.

[0002]

2. Description of the Related Art As shown in FIG. 8, a typical conventional microprocessor 900 is formed on a single LSI chip, and a DRAM 1000 is provided outside the LSI. The microprocessor 900 includes the DRAM 100
A bus interface circuit 930 for data bus connection with other peripheral devices, and a DRAM 1000
A cache 940 for temporarily storing program instructions and data read from the cache 940 or the local data bus B11, and an instruction decoder 920 for decoding program instructions read from the cache 940 or the DRAM 1000 to the data bus (also referred to as a system bus) B17. , A data processing unit 11 for executing the program instruction decoded by the instruction decoder 920, and the like. The data processing unit 11 includes a program counter (PC)
111, data load / store unit 112, arithmetic logic addition operation unit (ALU) 113, register group 1
14, internal data buses 115 to 11 connecting them
Consists of 7 mag. The bit width of these data buses is, for example, 32 bits. The instruction designated by the program counter 111 of the data processing unit 11 is read from the DRAM 1000 via the external data bus B17, the bus interface circuit 930, the local data bus B11 or from the cache 940 via the local data bus B11, and the instruction decoder 920 reads the instruction. And the data processing unit 11 executes the instruction. The bit widths of local data bus B11 and external data B17 are, for example, 32 bits. When the instruction is executed, the program counter 111, the load / store unit 112, the arithmetic additional operation unit 113, the register group 114, etc. are operated, and the cache 940 or the DRA is operated.
The M1000 or the like is accessed to read or write data or instructions.

Recently, microprocessors and DRAMs
Are also proposed on a single LSI. For example, "A Multimedia 32b RISC Microp
rocessor with 16Mb DRAM, ”Digest of Technical Pape
rs of 1996 IEEE International Solid-State Circuits
See Conference, PP. 216-217 (1996). As shown in FIG. 9, in such a microprocessor 800, the DRA
A portion other than the M15 is a microprocessor portion, and the DRAM 15 is arranged on an LSI chip on which the microprocessor portion is mounted. The DRAM 15 can read and write, for example, 256-bit data via a data bus (hereinafter also referred to as a DRAM bus) B15 having this bit width. The DRAM 15, the cache 16, the bus interface circuit 17, and the instruction decoder 830 are connected to the data bus B15. The bus interface circuit 17 includes a data bus B15 and an external DR (not shown).
This is a circuit for exchanging data with the AM and other peripheral devices via the external data bus B17. The external data bus B17 is, for example, a 16-bit width data bus due to a problem of power consumption and a problem of compatibility with an external device. Actually, the bus interface circuit 17 includes a buffer for exchanging 256-bit data with the data bus B15, but is not shown for simplicity. Further, an instruction queue capable of holding 256-bit data is provided on the input side of the instruction decoder 14B, but is not shown for simplification. Therefore, DRA
M15, an instruction queue (not shown), a cache 16,
256-bit data can be exchanged with the bus interface circuit 17. Therefore, the DRAM 15 is mounted on one LSI chip on which the microprocessor is mounted.
By placing the microprocessor part and DR
It is expected that the amount of data transferred to and from the AM 15 will be increased and at the same time the power consumption will be reduced.

However, if the data processing unit 11
The bit width of the data exchanged with M15 is
Due to the configuration of the register 13 and the register group 114, the bus width (for example, 32 bits) is smaller than the bus width of the DRAM 15. Therefore, the bit width of the local data bus B11 remains at this narrow bit width, and when the DRAM 15 is accessed from the load / store
Data selector 82 for selecting 32 bits from 56 bits
0 is used. Data selector 820 is connected to a local data bus B11 having a bit width of 32 bits, for example.
Includes an aligner for transferring 32-bit data at an appropriate bit position on DRAM bus B15 to local data bus B11 or transferring 32-bit data on local data bus B11 to an appropriate bit position on data bus B15. In.

[0005]

SUMMARY OF THE INVENTION Conventional on-chip D
In a microprocessor having a RAM, the data bus connected to the DRAM has a wide bit width. The wide bit width of the DRAM cannot be used for the operation. On the other hand, in order to execute a program that has already been created, it is necessary for a microprocessor to be able to execute a conventional operation with a bit width.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a microprocessor capable of performing a conventional narrow bit width operation on data read from an on-chip DRAM and also capable of executing a larger bit width operation. It is to be.

[0007]

To achieve the above object, a microprocessor according to the present invention is provided on a single semiconductor integrated circuit chip, and the microprocessor executes a process specified by an instruction. An extended operation unit that is wider than a first data width, which is the width of data processed by the data processing unit, and that can execute an operation on data having a data width equal to or less than a second data width; A dynamic random access memory (DRAM) capable of reading and writing data having a data width of 3.

A first data bus having the first data width for exchanging data with the data processing unit is connected to the data processing unit, and exchanges data with the extended operation unit. The second to do
A second data bus having a data width of the DRAM is connected to the extended operation unit, and a third data bus having a third data width for exchanging data to be read / written with the DRAM is connected to the DRAM. And a bus selection circuit for switching one of the first and second data buses to connect to the third data bus.

Further, another microprocessor according to the present invention is provided on a single semiconductor integrated circuit chip, and the microprocessor has a data width to be processed by a data processing unit for executing a process specified by an instruction. An extended operation unit that can execute an operation on data having a data width wider than the first data width and is equal to or smaller than the second data width, and a dynamic unit that can read and write data having a third data width equal to or larger than the second data width. A random access memory (DRAM).

A first data bus having the first data width for exchanging data with the data processing unit is connected to the data processing unit and exchanges data with the extended operation unit. A second data bus having the second data width for exchanging is connected to the extended operation unit, and a second data bus having the third data width for exchanging data to be read / written with the DRAM. A third data bus is connected to the DRAM, has a fourth data width smaller than the first data width, and is provided with a fourth data bus for connection to a device external to the microprocessor. Can be

Further, the first data bus and the fourth data bus are connected to each other.
And a bus selection circuit for switching one of the second and fourth data buses to connect to the third data bus.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a microprocessor according to the present invention will be described in more detail with reference to some embodiments shown in the drawings. In the following, the same reference numerals represent the same or similar ones. Further, in the second and subsequent embodiments of the invention, only the differences from the first embodiment of the invention will be mainly described.

<First Embodiment of the Invention> A microprocessor 1 shown in FIG. 1 is provided on a single large-scale integrated circuit (LSI) chip and has a bit width of a predetermined bit width (for example, 32 bits) or less. (Hereinafter referred to as a data processing unit) 11 for processing the data, an extended operation unit 12 for executing an operation on data having a bit width equal to or smaller than a predetermined bit width (for example, 256 bits) larger than the bit width. An extended data bus B12 having the above-mentioned large bit width for extended operation unit 12 is provided, and data bus B11 (hereinafter referred to as a local data bus) connected to data processing unit 11 and extended operation unit 12 are provided. The connected extended data bus B12 is switched to the data bus of the DRAM 15 (hereinafter referred to as D). Bus selector 13 to connect to the AM bus also called) B15 is provided. The extended operation unit 12 includes a DRAM bus B15, a bus selector 1
3. Data having a wide bit width can be received from the DRAM 15 via the extended data bus B12, an operation is performed on the data, and the resulting data is transferred to the DRA via the same path.
M15. The data processing unit 11 transmits / receives data having a narrow bit width determined by the data processing unit 11 to / from the DRAM 15 via the local data bus B11, the bus selector 13, and the DRAM bus B15. The cache 16 and the bus interface circuit 17
It is connected to DRAM bus B15. An external data bus (also called a system bus) B17 is connected to a DRAM bus B15 via a bus interface circuit 17.

One of the important points in the present invention is to make the bus width of the extended data bus B12 larger than the bus width of the local data bus B11. This is in view of improving the processing capability of the microprocessor 1. desirable. In particular, it is desirable to make the bus width of the extended data bus B12 and that of the DRAM bus B15 equal in order to maximize the processing capacity. In the following description, the extended data bus B12, DR
The bus width of the AM bus B15 is equal to each other, and both are 256.
Assume a bit. Further, the local data bus B11
Is 32 bits, and the external data bus B17 is 16 bits. However, it goes without saying that the bus width of these data buses is not limited to these numerical values in the present invention. Basically, the extended operation unit 12 can execute an operation on data having a second data width wider than the first data width of the data processed by the data processing unit 11,
The RAM only needs to be able to read and write data having a third data width wider than the first data width and equal to or larger than the second data width. Therefore, the bit width of the extended data bus B12 should be smaller than the bit width of the DRAM bus B15 and larger than the bit width of the local data bus B11.

The data processing unit 11 has a program counter (PC) 1 like a conventional microprocessor.
11, a load / store circuit 112, a first arithmetic and logic unit (hereinafter sometimes referred to as a basic arithmetic unit) 113, a first
Register group 114 (hereinafter, may be referred to as a basic register group), and internal data buses 115 and 1 for connecting these.
16, 117, etc. However, such a data processing unit 11 is an example of a data processing unit to which the present invention can be applied, and the present invention is not limited to the data processing unit described here. Basically, the data processing unit 11 has a function of executing an operation specified by the instruction,
What is necessary is just to have a function of exchanging data with the DRAM 15.

The program counter 111 outputs the instruction
The instruction address for fetching from the AM 15 or the cache 16 is held and sequentially updated. Here, it is assumed that the instruction address is also 32 bits. The load / store circuit 112 receives a load request or a store request for the DRAM 15 or the program counter 11.
And a memory request circuit (not shown) for supplying a memory access request such as a fetch request for an instruction designated by the first data bus 115 to the internal data buses 115 to 117.
It includes a bus control circuit (not shown) that controls transmission and reception of data from 11 to 114 or controls connection between local data bus B11 and any of internal data buses 115 to 117.

The arithmetic unit 113 is an arithmetic unit capable of executing four arithmetic operations or simple logical operations. Of these arithmetic operations, an instruction decoded by the instruction decoder 14 is used by the arithmetic unit 113 in the data processing unit 11. When the instruction is an operation instruction requesting, the operation specified by the instruction is executed. The data processing unit 11 includes other operation units such as a shift operation circuit, but these circuits are not shown here for simplicity. The register group 114 includes a plurality of registers for holding data used for the operation or operation result data, and each register can be specified by an instruction.

Although the data processing unit 11 includes other buses such as a control bus and an address bus, these buses are not shown here for the sake of simplicity, and the description thereof is omitted for simplicity. I do. For simplicity, the data bus, the control bus, and the address bus may be simply referred to as a data bus instead of the entire bus. In the data processing unit 11, a control circuit for controlling the operations of the plurality of circuits according to the instruction decoding signal 14A output from the instruction decoder 14 is provided.
This circuit is also not shown for simplicity. In the following, it is assumed that the bit width of each of internal data buses 115 to 117 is 32 bits. It is assumed that the bit width of each register in the register group 114 and the bit width of the operation executed by the arithmetic unit 113 are also 32 bits. However, it goes without saying that the present invention is not limited to these numerical values. The same is true for the other values assumed below. For example, the local data bus B for the data processing unit 11
11. The bit width of the internal data buses 115 to 117 therein can also be set to, for example, 64 bits.

As shown in FIG. 1, the extended operation unit 12
Is a bus control circuit 122, a second arithmetic operation unit (hereinafter sometimes referred to as an extended operation unit) 123, and a second register group 1
24 (hereinafter sometimes referred to as an extension register group), and internal data buses 125, 126, and 127 for connecting them.
Etc. It is assumed that the bit width of each of the internal data buses 125 to 127 is 256 bits. However, it goes without saying that the present invention is not limited to this numerical value. The register group 124 includes a plurality of registers for holding data to be operated by the operation unit 123 or operation result data, and each register can be designated by an instruction. It is assumed that the bit width of each register in register group 124 is also 256 bits.

The arithmetic unit 123 is, for example, an arithmetic unit for performing an operation on 256-bit data, and specifically, is composed of, for example, eight partial arithmetic logic units (not shown) having the same structure. The 256-bit data on the internal data bus 125 is divided into eight pieces of partial data in units of 32 bits, and each piece of partial data is supplied to one of the plurality of partial arithmetic logic units (not shown). Similarly, the data on the internal data bus 126 is also divided, and the resulting eight pieces of partial data are supplied to one of a plurality of partial arithmetic logic units (not shown). Each partial arithmetic and logic unit executes an operation on the pair of 32-bit length partial data supplied in this manner in parallel with each of the other partial arithmetic and logic units. It is assumed that each partial arithmetic logic unit can execute four arithmetic operations or simple logical operations. The operation to be performed is specified by the instruction decoded by the instruction decoder 14. In the present invention, the structure of the arithmetic unit 123 is not limited to the arithmetic unit having such a structure. For example, the arithmetic unit 123 may be composed of 32 partial arithmetic and logic units (byte arithmetic units) that execute an operation on 8-bit data, and 16 partial arithmetic and logic units that execute an operation on 16-bit data. It may be composed of a logical operation unit, or may be composed of two partial arithmetic and logical operation units for executing an operation on 128-bit data. Thus, the operation unit 123
The use of a plurality of partial arithmetic and logic units is effective in that there are many uses. However, the arithmetic unit 123
May consist of one arithmetic and logic unit that performs an operation on 256-bit data.

The bus control circuit 122 includes an internal data bus 125 similar to the bus control circuit (not shown) included in the load / store circuit 112 in the data processing unit 11.
Control the transmission of data from the plurality of circuits connected to to the internal data bus 125 to 127,
Alternatively, the extended data bus B12 and the internal data bus 125
To control the connection with any one of.
Assume that the bit width of the extended data bus B12 is 256 bits.

A control circuit for controlling the operation of the plurality of circuits in accordance with the instruction decoding signal 14B output from the instruction decoder 14 is provided in the extended operation unit 12, but this circuit is simplified. Not shown. The control bus and address bus associated with the internal data 125 to 127 in the extended arithmetic unit 12 are not shown for simplification, and the description thereof may be omitted. Similarly, a control bus or an address bus used for the extension data bus B12 or other data buses is not shown for simplicity, and the description thereof may be omitted.

FIG. 2 shows an example of an internal circuit of the bus selector 13. The bus selector 13 includes a local data bus B11,
Read / write buffers 136 and 137 connected to the extended data bus B12 are provided. The read / write buffer 136 comprises a pair of buffers provided between 32-bit local data buses B11 and B38, respectively. , And outputs the data to the local data bus B38 or B11. Similarly, lead /
The write buffer 137 is composed of a pair of buffers provided between the 256-bit extended data buses B12 and B37, respectively.
37, and outputs the data to the extended data bus B37 or B12. The arbitration circuit 133 supplies a control signal for turning on one of the read / write buffers 136 and 137 in response to a control signal 14C from the instruction decoder 14. When the instruction decoded by the instruction decoder 14 requires data transfer between the DRAM 15 and the extended operation unit 12, the extended data buses B12 and B
37 is connected. For other instructions, the local data buses B11 and B38 are connected.

D for exchanging data with the DRAM 15
RAM I / O circuit 140 is connected to DRAM buses B15 and B256.
It is provided between bit extension data buses B36.
This circuit 140 receives a 256-bit data on the DRAM bus B15 at an appropriate timing, and supplies it to the extended data bus B36 as it is. A first internal buffer (not shown) and the 256-bit data on the extended data bus B36 At an appropriate timing, and the DRAM bus B1
5 second internal buffer (not shown) that supplies it as it is to
And In response to a control signal supplied thereto, DRAM I / O circuit 140 takes in data on DRAM bus B15 and outputs it to extended data bus B36, or takes in data on extended data bus B36 and takes in data on extended data bus B36. To supply.

A first aligner 138 is provided between the extended data bus B36 and the local data bus B38. The aligner 138 directly controls the selection of the bit line of the DRAM bus B15 connected to each bit line of the extended data bus B36, that is, the mutual connection position of these data buses. As a result, the local data bus B connected to each bit line of the DRAM bus B15 is substantially
The selection of eleven bit lines, that is, the connection positions of these data buses are controlled. The aligner 138 includes a first internal aligner (not shown) for cutting out 32 bits starting from an appropriate position of the 256-bit data supplied from the extended data bus B36 and supplying the extracted data to the local data bus B38. 3 supplied from bus B38
2 bits of data forming the extended data bus B36
And a second internal aligner (not shown) that feeds the 32 bit line at the appropriate position of the 56 bit line. The bit position adjustment performed by these aligners is performed by the memory address supplied from the data processing unit 11 to the bus selector 13 via the line 112A. Although the operations of these two internal aligners are different, since these circuits are common in that they are circuits for adjusting the bit position of data, in this embodiment, both of these internal aligners are Call.

In this embodiment, the extended data bus B12
And B36 are both 256 bits. Therefore, no aligner is required to connect these data buses,
Extended data buses B36 and B37 are directly connected. However, in the figure, the second aligner 139 connecting these data buses B36 and B37 is shown by a dotted block. This aligner is such that the bit width of the extended data bus B12 is smaller than the bit width of the DRAM bus B15.
That is, the bit width of the extension data bus B12 is used in another embodiment smaller than the bit width of the extension data bus B36. The aligner 139 includes a first internal aligner (not shown) for supplying the extended data bus B37 with the bit position of the 256-bit data supplied from the extended data bus B36 shifted, and a 256-bit supplied from the extended data bus B37. A second internal aligner (not shown) for shifting the bit position of the data having the smaller bit width and supplying the data to the 256-bit extended data bus B36.

The address decoder 131 decodes the memory address specified by the memory write request sent from the data processing unit 11 to the line 112A, and if the memory address is an address assigned to the DRAM 15, And a control signal such as read / write supplied from the data processing unit 11 via the line 112A to the DRAM.
It is supplied to the address control circuit 134. The DRAM address control circuit 134 generates a DRAM address for accessing the DRAM 15 corresponding to the memory address supplied from the address decoder 131, creates a control signal for the aligners 138 and 139, and is supplied from the address decoder 131. The read / write signal is supplied to the DRAM timing control circuit 135.
The control signals for the aligners 138 and 139 are based on the memory addresses and the first and second addresses in these aligners.
And a signal for activating one of the internal aligners (not shown) to be operated. The DRAM timing control circuit 135 controls the read / write control signal supplied from the DRAM address control circuit 134 with the D / D signal.
In response to the RAM address, a plurality of timing signals predetermined by the DRAM 15 and a control signal for the DRAM I / O circuit 140 necessary for accessing the DRAM 15 are generated, and the plurality of timing signals are transmitted via the line 13A. The control signal is supplied to the DRAM 15 and the generated control signal is supplied to the DRAM I / O circuit 140.

It is assumed that access to DRAM 15 is performed on 256-bit data based on a 32-byte address boundary. Therefore, for example, after address N, address N + 32 is taken. When data from the address N + 4 is read / written from the data processing unit 11 in a long word (32 bits), DRA
M15 is controlled so that 32-byte data starting from address N is read / written.

When the DRAM access is a read access, the bus selector 13
4 from address N + 4 to address N + 7 of 2-byte data
Byte data is connected from the DRAM bus B15 to the local data bus B11. When the DRAM access is a write access, the 4-byte data at addresses N + 4 to N + 7 of the 32-byte data to be written to the DRAM 15 is rewritten by a known partial rewrite. The 4-byte data to be partially rewritten is supplied from the local data bus B11 to the DRAM bus B15 by the bus selector 13.

The outline of the operation in the present embodiment is as follows. The data processing unit 11 fetches an instruction from the outside through the DRAM 15 or the cache 16 or the bus interface circuit 17 to the instruction decoder 14, and the instruction decoder 14 decodes the instruction and controls the data processing unit 11 or the extended operation unit 12. Generate a signal. The register in the register group 114 of the data processing unit 11 and the DRA
When an instruction for performing data transfer with M15, for example, a load instruction or a store instruction for a register in a register group is decoded, the instruction decoder 14
A control signal instructing access to line 5
The data is supplied to the data processing unit 11 via A. The load / store circuit 112 supplies a signal such as a memory address to be accessed to the bus selector 13 in response to the control signal, and the bus selector 13 converts the address decoder 131 from the control signal such as the memory address. , DRAM address control circuit 134, DRAM timing control circuit 135
As a result, a control signal including an address to the DRAM 15 is output. Further, the instruction decoder 14 outputs a signal from the bus selector 1
3, the arbitration circuit 133 in the data processing unit 1
1 to the DRAM 15 is supplied with a signal indicating the data transfer, and the arbitration circuit 133 responds to this signal to
The operation timing and data transfer direction of the write buffer 136 and the aligner 138 are controlled so as to operate at a timing adapted to the control signal output from the load / store circuit 112. At the same time, the DRAM address control circuit 134 sends the DRA to the aligner 138.
A part of the M bus B15 corresponding to the memory address is selected and controlled so as to be connected to the data bus B1,
The DRAM timing control circuit 135 has a DRAM I / O
It instructs the circuit 140 to fetch data from the DRAM bus B15 or fetch the output of the aligner 138, and controls the fetch timing. Thus,
Desired data is transferred between the data processing unit 11 and the DRAM 15.

In the instruction decoder 14, the extended operation unit 12
Is decoded, the instruction decoder 14 supplies a control signal to the extended operation unit 12 via the line 14B. Extended operation unit 12
Performs an operation according to a control signal. Registers in register group 124 in extended operation unit 12 and DRAM 1
5, for example, a load instruction or a store instruction for a register in the register group 124 is decoded by the instruction decoder 14, the instruction decoder 14 transmits some control signals necessary for the decoding to the data processing unit. 11 and another control signal to the extended operation unit 12. That is, in the present embodiment, the data processing unit 11 accesses the DRAM 15 in the same manner as when the instruction that requires data transfer between the registers in the register group 114 in the data processing unit 11 and the DRAM 15 is decoded by the instruction decoder 14. A memory access request including a memory 0 address to be issued is issued and processed in the same manner. The instruction decoder 14 sends the DRA from the extended arithmetic unit 12 to the arbitration circuit 133 in the bus selector 13.
The arbitration circuit 133 generates a signal indicating that data transfer is to be performed to the M15 or data transfer in the reverse direction, and the arbitration circuit 133 includes the read / write buffer 137 and the aligner 139 when the aligner 139 and the DRAM I / O circuit 140 are provided.
To control the data bus input / output in the timing and transfer direction adapted to the memory address and the control signal output from the data processing unit 11. When there is the aligner 139, the aligner 139 also controls the aligner 139 so as to select a portion of the DRAM bus B15 corresponding to the memory address and connect it to the extended data bus B12. Thus, the data processing unit 1
1 and the desired data is transferred between the DRAM 15.

The operation of the data processing unit 11, the extended operation unit 12, and the bus selector 13 of the microprocessor will be described below in detail.

First, the data processing unit 11 and the DRAM
15 and a data transfer and data processing unit 11
The details of the calculation by the calculator 113 will be described. FIG. 3 shows an instruction to execute two load instructions to load two data in two registers of the register group 114 in the DRAM 15 into the data processing unit 11 and to execute an addition to the two data by the ALU 113. Is executed, and an instruction to store the result data in the DRAM 15 is executed. further,
As shown in FIG. 3, the DRAM 15 stores 4-byte data D0, D1, D2,..., D7 at storage locations of byte addresses 000, 004, 008,. Byte address 02
0 is added to the storage location of data D1 and D2.
Assume that + D2 is stored.

For example, when an instruction for loading data into one of the register groups 114 in the data processing unit 11 is decoded by the instruction decoder 14, the bus (not shown) in the load / store circuit 112 in the data processing unit 11 The control circuit reads the memory address (for example, address 004 shown in FIG. 3) read from one of the registers 114 specified by the load instruction.
To the internal data bus 115 or 116. The memory access request circuit (not shown) receives the memory address, and sends a memory access request including the memory address and a control signal indicating that the memory access is a read access to the bus selector 13 via the line 112A. . From the instruction decoder 14, the bus selector 13
A control signal notifying the data transfer from the DRAM 15 to the data processing unit 11 is supplied to the arbitration circuit 133 therein, and the 256-bit data read from the DRAM 15 under the control of the DRAM address control circuit 134 and the DRAM timing control circuit 135 is supplied. The data is supplied to the extended data bus B36 via the DRAM I / O circuit 140, and the aligner 138 selects a necessary data portion of the data. In this case, the data D1 to be loaded is 3
It is 2 bytes long, and it can be determined from the load address 004 that it is located at the fourth byte from the beginning of the read 256-bit data. The aligner 138 cuts out the data D1 based on the load address 004 and outputs it to the local data bus B38. This data is further output to the local data bus B11 through the read / write buffer 136. Local data bus B11
Output to the load / store circuit 112
Supplied to The bus control circuit (not shown) in the load / store circuit 112 transfers the data D1 to the internal data bus 117. This data is transferred via the internal data bus 117 to one of the registers 114 specified by the instruction. Thus, the execution of the load instruction is completed.

A similar operation is performed for data D2 using memory address 008 in FIG. Thus, the data D1 and D2 required for the operation are loaded into the two registers in the register group 114.

When the instruction decoder 14 decodes an operation performed by the operation unit 113, for example, an operation instruction requesting addition, the bus control circuit (not shown) operates the first group designated by the operation instruction in the register group 114. , The first and second data (data D 1 and D 2 in this case) read from the second register are transferred to internal data buses 115 and 11.
6 The arithmetic unit 113 performs an arithmetic operation on these data, and the bus control circuit (not shown) outputs the 32-bit arithmetic result data D1 +
D2 is sent to the internal data bus 117. This data is stored in the register group 114 via the internal data bus 117 in one register designated by this instruction.

When an instruction for storing data in one register of the register group 114 in the DRAM 15 is decoded by the instruction decoder 14, the bus control circuit (not shown) in the load / store circuit 112
4, memory addresses read from the first and second registers specified by the load instruction (02 in this example).
0) and 32-bit store data (D1 in this example)
+ D2) to the internal data buses 115 and 116, respectively. The memory access request circuit (not shown)
The memory address is received, and a memory access request including the memory address and a control signal indicating that the memory access is a write access is sent to the bus selector 13 via the line 112A. Bus selector 13 is line 13A
, A control signal for the DRAM 15 is generated from the memory access request in the same manner as described above, and transferred to the DRAM 15 via the line 13A. The bus control circuit (not shown) transmits the store data to the local data bus B11.
To send to. The bus selector 13 transfers this data to the DRAM 15 via the DRAM bus B15. DRAM1
5 is a DRAM bus B1 according to a control signal on line 13A.
5 is stored.

Next, the extended operation unit 12 and the DRAM 1
The details of the data transfer between 5 and the arithmetic operation by the arithmetic unit 123 of the extended arithmetic unit 12 will be described. In FIG. 4, two load instructions are executed to load two data into two registers of the register group 124 in the extended arithmetic unit 12, and an instruction for executing addition to the data by the ALU 123 is executed. The resulting data is stored in DRAM1
5 shows the flow of data when an instruction to store data in the instruction No. 5 is executed. Further, as shown in FIG.
The 4-byte data D0, D1, D2,.
D7 is stored, and byte addresses 020, 024, 02
Data D8, D9, D10,.
Assume that D15 is stored. Further, as the operation result data described later, the byte addresses 040, 04
Addition result data D1 + D8, D2 are stored in storage locations 1, 1,.
Assume that + D9 ,, is stored.

An instruction to load data such as D0 to D7 from any one of the registers in the register group 124 from the DRAM 15 is issued to the register group 1 of the data processing unit 11.
14, a first register for holding an address of data to be loaded, and a register group 1 of the extended arithmetic unit 12.
24 specifies the second register to load the data into. When the instruction decoder 14 decodes the load instruction, the instruction decoder 14 generates a control signal for the operation to the data processing unit 11.

The bus control circuit (not shown) and the memory (not shown) in the load / store circuit 112 in the data processing unit 11 are the same as the instruction for loading data into the registers in the register group 114 described above. The access request circuit sends a memory access request including the memory address read from the first register designated by the load instruction in the register group 114, in this example, 000, to the bus selector via the line 112A. 13
Send to The bus selector 13 sends a control signal corresponding to the memory access request to the DRAM 15 via the line 13A,
The 256-bit data D0 to D7 specified by the load address are read from the DRAM 15. The instruction decoder 14 sends an arbitration circuit 133 in the bus selector 13 to
Extended operation unit 1 from DRAM 15 via line 14C
2 to generate a control signal indicating the data transfer to DR2.
The 256-bit data D0 to D7 read from the AM 15 are taken into the DRAM I / O circuit 140, output to the expansion data bus B12 through the expansion data buses B36 and B37, the read / write buffer 137, and further expanded. Is forwarded to In the embodiment where the aligner 139 is used, the extended data bus B
After the necessary data portion of the 256-bit data on the C.36 is selected and positioned by the aligner 139, the read / write buffer 137 and the extended data bus B
The data is transferred to the extended operation unit 12 via the control unit 12.

Bus control circuit 1 in extended operation unit 12
A circuit 22 operates in the same manner as the bus control circuit (not shown) in the load / store circuit 112 in the data processing unit 11 and transfers this data to the internal data bus 127. This data is transferred via the internal data bus 127 to one register designated by the above instruction in the register group 114 and stored therein. Similarly, using the load address 008, another 256-bit data D8
To D15 are the register group 12 in the extended arithmetic unit 12.
4 are loaded into the other registers.

An operation instruction requesting an operation by the second operation unit 123 holds two data to be operated.
The first and second registers in the register group 124 are designated. When the instruction decoder 14 decodes the operation instruction, the bus control circuit 122 has 256 bits read from the first and second registers designated by the operation instruction in the register group 124, respectively. First and second data (in this case, D0 to D7 and D8 to D1
5) to the internal data buses 125 and 126. The arithmetic unit 123 performs an operation (addition in this example) on these data. Specifically, the arithmetic unit 123 uses these 256 arithmetic units to provide these 256
16 pairs of 3 corresponding to each other among two data of bits
2-bit data is added (4-byte unit addition). The bus control circuit 122 causes the 256-bit operation result data output from the arithmetic unit 123 to be transmitted to the internal data bus 127. This data is stored in the first register in the register group 114 via the internal data bus 127.

The data in the register group 124 is stored in the DRAM 1
The instruction to store the data to be stored in the register group 114 of the data processing unit 11 is the first register that holds the address of the data to be stored, and the data to be stored in the register group 124 of the extended operation unit 12 is Second
And registers. When this instruction is decoded by the instruction decoder 14, the instruction stored in the load / store circuit 112 in the data processing unit 11 is the same as the instruction for storing the data in the register group 114 described above. A memory including a memory address (040 in this example) read from the first register designated by the load instruction in the register group 114 by a bus control circuit (not shown) and a memory access request circuit (not shown). The bus request is sent to the bus selector 13 via the access request and the line 112A, and the bus control circuit 122 in the extended operation unit 12 reads out from the second register in the register group 124 specified by the store instruction.
6-bit store data D0 + D8, D1 + D9,.
Is sent to the internal data bus 125, and this data is sent to the extended data bus B12. For the current order,
The bus selector 13 sends a control signal corresponding to a memory access request on the line 112A and store data on the local data bus B11 to the DRAM via the line 13A and the DRAM bus B15, respectively, and stores them therein. Thus, the execution of the store instruction is completed.

In the above description, the case where the access to the DRAM 15 is performed in units of 32 bytes and the data to be accessed is a long word (32 bits) has been described. The address used to access the DRAM 15 is, for example, N
+32 will be taken. Data processing unit 11
Therefore, when accessing data from the address N + 4, the DRAM 15 is controlled to access the data at the address N as the address, and the bus selector 13 converts the 4-byte data from the addresses N + 4 to N + 7 to the local data. The data is transferred to the bus B11. However, N + 4
Word read / write such as access in word (16 bits) to address or N + 6, N + 4, N
Binary read / write such as access to +5, N + 6 or N + 7 in byte units can also be performed. In this case, the DRAM 15 is accessed at address N, and the necessary data portion may be cut out by the bus selector 13. In the case of the above word read / write, 16 bits starting from address N + 4 or 16 bits starting from address N + 6
Bits may be cut out, and in the case of the binary read / write, 1-byte data at N + 4, N + 5, N + 6 or N + 7 may be cut out.

In this embodiment, the extended data bus B12 having a bus width wider than the local data bus B11 for the data processing unit 11 and the data width wider than the data width that can be processed by the data processing unit 11 are processed. DRAM bus B
The data operation can be executed by effectively utilizing the 15 wide bus widths. Further, since the operation to be executed by the extended operation unit 12 can be specified by an instruction, various operations can be executed on a wide range of data.

<Modification of First Embodiment of the Invention> As described above, the data width of data that can be processed by the extended arithmetic unit 12 is smaller than that of the DRAM bus B15, but the data processing unit 11 It can be wider than the data width of the data that can be processed. At this time, the data width of each register in the register group 124 in the extended operation unit 12, the data width of the internal data bus, etc.,
23, the data width of the data to be processed, the extended data bus B1
The data width of No. 2 may be adjusted to the new data width.
Further, at this time, the aligner 139 shown in FIG. 2 is required. For example, when the extension data bus B12 is set to 128
When the bit is bitted, the aligner 139 may be configured to cut out the first 128 bits or the last 128 bits of the 256 bits read from the DRAM 15 and transfer the cut data to the extended data bus B12.

<Embodiment 2 of the Invention> As shown in FIG. 5, in the present embodiment, the data bus B17 is connected to one or a plurality of peripheral devices (not shown) provided outside the microprocessor 1. Data bus that constitutes an external data bus (also called a system bust)
It consists of a part provided on the microprocessor 1 (on-chip part) and a part located outside the microprocessor 1 (off-chip part). Sometimes called a data bus. The data width of external data bus B17 is, for example, 16 bits as in the first embodiment. The bus interface circuit 17 is connected to the external data bus B17.
And an interface circuit for exchanging data with the peripheral device through the interface. Data processing unit 1
Local data bus B11 for internal data bus 115 of data processing unit 11 as in the first embodiment.
It has the same bit width as 117, for example, 32 bits. Unlike the first embodiment, in the present embodiment, the data processing unit 11 is connected to the bus interface circuit 17 via the local data bus B11.
The instruction decoder 14 and the cache 16 are connected to the local data bus B11.
Reference numeral 11 is connected to an external data bus B17 via a bus interface circuit 17. Furthermore, DRAM1
5 is connected to the external data bus B1 via the bus selector 13.
7 and the extended operation unit 12 is also connected to the external data bus B17 and the extended data bus B1.
2 is connected to the bus selector 13. The bit width of the extended data bus B12 is 256 as in the first embodiment.
Assume a bit. The bus selector 13 is a DRAM bus B
15 is used to switch and connect to one of the external data bus B17 and the extended data bus B12. It is assumed that the bit width of DRAM bus B15 is 256 bits as in the first embodiment. As described above, the bus selector 13 is located between the bus interface circuit 17 and the DRAM 15, and is controlled by the data processing unit 11 via the external data bus B17 in the same manner as an external device. The extended operation unit 12 is also connected to the external data bus B17, so that the data processing unit 11 controls the same as an external device. The same applies to the DRAM 15.

The data processing unit 11 includes a local data bus B11, a bus interface circuit 17, an external data bus B22, a bus selector 13, and a DRAM bus B15.
The DRAM 15 is accessed via the. In the first embodiment, a control signal for accessing the DRAM 15 is provided by an address decoder 13 provided in the bus selector 13.
1, generated by the DRAM address control circuit 134 and the DRAM timing control circuit 135. Since the DRAM 5 is connected to the DRAM bus B15 different from the external data bus, by making these circuits high-speed, the access to the DRAM 15 can be performed in the conventional case where the DRAM 15 is connected to the external data bus. (For example, FIG.
) Can be executed faster. However, for this purpose, as described above, it is necessary to increase the speed of the circuit used for the access (the circuit in the bus selector 13). However, in the present embodiment, the DRAM 15
It is controlled in the same manner as an external device, but has a feature that it enables transfer of wide data between the extended operation unit 12 and the DRAM 15. That is, the DRAM 1
5 is connected to the external data bus B17, so that a circuit for accessing the DRAM 15 provided in the bus
May be operated at the same speed as that provided outside (for example, in the case of FIG. 8). Therefore, in the present embodiment, the data processing unit 1
Although the access from 1 is slow unlike Embodiment 1,
Wide data transfer between the extended operation unit 12 and the DRAM 15 can be realized.

The data processing unit 11 accesses the cache 16 via the local data bus B11.
Further, the extended operation unit 12 and an external device (not shown) can be accessed via the local data bus B11, the bus interface circuit 17, and the external data bus B17.

The data processing unit 11 reads an instruction from the cache 16 or the DRAM 15 into the instruction decoder 22 using the local data bus B11, and the instruction decoder 22 generates a control signal for the data processing unit 11. The data processing unit 11 controls the cache 16 and the bus interface circuit 1 according to the control signal.
7 to access the data for processing.

As in the first embodiment, the DRAM 15
Are arranged on the same LSI as the data processing unit 11, the width of the DRAM bus B15 can be widened. However, since the external data bus B17 is used for connection with an external device and for data access to the extended operation unit 12, the external data bus B17 cannot be as wide as the DRAM bus B15. In this embodiment, a portion for connecting the extended data bus B12 and the DRAM bus B15 is provided in the bus selector 13, and the extended operation unit 12 is also connected to the data external data bus B17. With this configuration, data can be transmitted over a wide bus width using the extended data bus B12.
Data can be directly transferred between the RAM 15 and the extended operation unit 12. The external data bus B17 and the extended data bus B
12 can be used independently, so DR
When data is transferred between the AM 15 and the extended arithmetic unit 12, data transfer is executed in parallel with the transfer using an instruction that does not access the DRAM 15, for example, an external device using the external data bus B17. The instructions can be executed by the data processing unit 11.

Furthermore, in the first embodiment, special operation instructions, load instructions,
Although the store instruction is used, in this embodiment, a specific instruction for the extended operation unit 12 is not used, and an instruction executable by the data processing unit 11 is used. Therefore, this embodiment can operate with the conventional instruction architecture. That is, data and control signals required for the operation of the extended operation unit 12 are written into a plurality of registers provided in the extended operation unit 12 using a memory write instruction by a so-called memory-mapped I / O operation. That is, when the data processing unit 11 executes a store instruction to write to any of the registers in the extended operation unit 12, data or control signals specified by the instruction are transmitted from the data processing unit 11 to the bus interface circuit 17, the external data bus B17. To the extended operation unit 12 via As in the first embodiment, the bus selector 13 does not select a bus in response to an instruction for the data processing unit 11 or an instruction for the extended operation unit 12, but a memory for the DRAM 15 as described later. Depending on whether the access instruction is given from the external data bus B17 or the extended operation unit 12,
The DRAM bus B15 is connected to the external data bus B17 or the extended data bus B12.

As in the first embodiment, the DRAM 15
It is accessed with an address having a 2-byte address boundary and can read and write 256-bit data.
However, in the present embodiment, data transfer between the DRAM 15 and the data processing unit 11 is performed by the external data bus B.
The external data bus B17 has a bit width smaller than that of the local data bus B11, for example, 1 bit.
It has 6 bits. Conditions for other data buses are the same as in the first embodiment. Therefore, between the bus interface circuit 17 and the DRAM 15, basically 16
It is executed in units of bit data. That is, in the case of the long-word read / write in which 32-bit data is read-write described in the first embodiment, the bus interface circuit 17 issues the access request to the DRAM 15 twice in the present embodiment. For example, the bus interface circuit 17 sends a long word read request from the data processing unit 11 to the local data bus B1.
1 if received through the first half of this longword
Two memory read requests requesting reading of 6-bit data and reading of the latter 16 bits are performed by the bus selector 1.
3 via the bus B17. The bus interface circuit 17 stores the first 16 bits and the second 1 bits read from the DRAM 15 in response to each memory read request.
When 6 bits are received, these data are combined and transferred as 32-bit data to the data processing unit 11 via the local data bus B11. When receiving a long word store request from the data processing unit 11, the bus interface circuit 17 similarly divides the store data specified by the request into first half data and second half data, and issues a memory write request for each data. I do.

As shown in FIG. 6, bus selector 13 has the same structure as bus selector 13 used in the first embodiment shown in FIG. However, unlike the bus selector 13 of the first embodiment, in the bus selector 13 of FIG. 2, one end of the read / write buffer 136 is connected to a 16-bit external data bus B17. 16-bit local data bus B38
It is connected to the. In addition, aligner 138 has 256
It is provided between a bit extension data bus B36 and a 16-bit local data bus B38. Further, in the embodiment, the signal 14C for controlling the arbitration circuit 133 is given from the instruction decoder 14 (FIG. 1). However, in the bus selector 13 in FIG. The second address decoder 1 decodes a memory address given to the line 17A from the processing unit 11 and decodes a memory address newly supplied to the line 12A from the extended operation unit 12.
32, and the arbitration circuit 133 outputs the external data bus B1 by the outputs of the two address decoders 131 and 132.
7 or the extended data bus B12
Connect to 15. The operation of the arbitration circuit 133 will be described later in the case of data transfer between the extended operation unit 12 and the DRAM 15. The operation of the arbitration circuit 133 in the case of transferring data to and from the DRAM 15 is apparent from the description of the first embodiment, and thus the description thereof is omitted. Note that the aligner 139 shown by a dotted line in FIG.
Are not used in the present embodiment, and the extended data bus B
In the first embodiment, a bit width of 12 is used in a modified example smaller than a bit width of DRAM bus B15.
Is the same as

Referring back to FIG. 5, the extended operation unit 12 is shown in FIG.
3 shows a schematic block diagram of an arithmetic circuit in the DRAM 15 for converting image data composed of luminance (Y) data, color (Cb) data, and color (Cr) data into RGB data. Here, the image data of each pixel (ie,
The luminance (Y) data, the color (Cb) data, and the color (Cr) data) consist of 8 bits,
In a 6-bit area, 8 pixels for 32 pixels each are used.
Bit of the same type of image data (ie, luminance (Y)
It is assumed that data, color (Cb) data, and color (Cr) data) are stored. As described below, the extended operation unit 12 can access three to three DRAMs in one access.
The same type of image data (that is, luminance (Y) data, color (Cb) data, and color (Cr) data) of a total of 256 bits for two pixels is read out, and the image data of each pixel is converted to corresponding RGB image data. Is configured to be converted in parallel.

More specifically, the extended operation unit 12
Are registers 261, 262, and 263 for receiving image data having a data width extended via the extended data bus B12 from the DRAM 15 via the bus selector 13.
R, G, B corresponding to the image data in these registers
An RGB conversion circuit 264 for generating data; an output buffer 267 for outputting the generated RGB data to the second external data bus B22;
2, an operation control register group 265 for controlling the operation of DR2.
An address generator 266 for generating an address of image data to be read from the AM 15 is provided.

FIG. 7 shows a more detailed block of the extended arithmetic unit 12. The operation of the extended operation unit 12 is controlled by the data processing unit 11
It is realized by writing necessary data to the operation control register group 265 in the inside. Writing to these registers is realized by the data processing unit 11 executing a so-called memory write command. When executing a memory write instruction for any of the registers, the data processing unit 11 writes data specified by the instruction to a register to which the memory address is assigned in accordance with the memory address specified by the instruction. That is, when a memory write instruction for one of the registers is decoded by the instruction decoder 14, a bus control circuit (not shown) in the load / store circuit 112 of the data processing unit 11 causes the register group 11
4, the storage data and the memory address are transmitted from the first and second registers to the internal data buses 115 and 116, and the storage data is transmitted to the local data bus B11. Further, a memory access request circuit (not shown) in the load / store circuit 112 sends the memory address and the write request to the line 112A. The store data and the write request are transmitted to a pair of the local data bus B11 and the line 112A, the bus interface circuit 17,
The data is sent to the extended operation unit 12 through the pair of the external data bus B17 and the line 17A, and the stored data is written to the operation control register to which the memory address is assigned.

More specifically, as shown in FIG. 7, the operation control register group 265 includes a head memory address of the luminance data group, a head memory address of the color (Cb) data group, and a color (Cr) data group. Registers 2652, 2653, 26 for holding the head memory addresses of
54 and an operation start designation register 2655. The extended operation unit 12
Is provided with an address decoder 2651 for controlling the operation of. When the extended operation unit 12 is operated, the data processing unit 11 specifies a memory address for designating a head address of 32 luminance data consisting of a total of 256 bits for 32 consecutive pixels in the DRAM 15, A memory address specifying the head of 32 color (Cb) data for a pixel and a memory address specifying the head of 32 color (Cr) data for the 32 pixels are stored in a register 265.
2, 2653, 2654 are sequentially executed, and a memory write instruction for writing an operation start bit into the register 2655 is further executed. As a result, on line 17A, registers 2652,
The memory addresses assigned to the memory addresses 2653 and 2654 are sequentially supplied as store addresses from the data processing unit 11 via the bus interface circuit 17. On the external data bus B17, the three memory addresses and the operation start bits are stored as store data. The data is sequentially supplied from the data processing unit 11 via the bus interface circuit 17. Address decoder 2651 is connected to line 17
One of the strike addresses supplied to A is decoded, and the store data on the external data bus B17 is written to the register to which the store address is assigned.

When the operation start bit is written into the register 2655 by executing these memory write instructions,
The extended operation unit 12 starts operation. First, the address generator 266 reads a memory address for the luminance data group from the register 2652, and transmits this memory address and a memory read request to the bus selector 1 via the line 12A.
3 In the bus selector 13, the address decoder 252 receives the read request, and sends to the arbitration circuit 253 information indicating that a DRAM read access from the extended arithmetic unit 12 has been entered and its memory address. Arbitration circuit 2
The arbitration unit 53 performs arbitration so that read access from the extended operation unit 12 to the DRAM 15 is performed. That is, the read / write buffers 136 and 137 are controlled so that the data read from the DRAM 15 is transferred to the extended data bus B12, and the memory address and the read request are output to the DRAM address control circuit 134.
The DRAM address control circuit 134 converts the memory address into an address (DRAM address) in the DRAM 15 and sends the DR address to the DRAM timing control circuit 133.
AM signal and control signal, and
In the embodiment where 39 is used, the aligner 139 is instructed to cut out data. The DRAM timing control circuit 133 generates a control signal for accessing the DRAM 15, and outputs a control signal based on the DRAM address.
Access M15.

A group of 256-bit luminance data is read from the DRAM 15. The read data is DRA
When the M / O circuit 140 and the aligner 139 are provided, they are output to the extended data bus B12 through the aligner 139 and the read / write buffer 137. This data (luminance data (Y)) is stored in the register 261 in the extended operation unit 12. The address generator 266 then sequentially reads out color (Cb) data and color (Cr) data from the DRAM 15 in the same manner. Registers 2611 and 261,
62 and 263 are connected so as to constitute a shift register, and each time data newly read from the DRAM 15 is supplied to the extended operation unit 12, the register 2
The data read to the register 261 is moved in the order of 61 → 262 → 263. When the three pieces of image data (luminance, color Cb, and color Cr) are read in this way, the register 26
3 stores luminance (Y) data, the register 262 stores color (Cb) data, and the register 261 stores color data (Cr).

The extended operation unit 12 converts the image data recorded in these three registers into an RGB conversion unit 264.
And the RGB conversion unit 264 performs the RGB conversion on the image data of each of the 32 pixels in parallel.
That is, the RGB conversion unit 264 performs three 8-bit image data (ie, luminance data (Y) and color (Cb)) for the same pixel in the 256-bit image data.
Data and color (Cr) data) as shown in the figure, there are 32 arithmetic units for executing multiplication and addition with coefficients α, β, and γ, and each arithmetic unit has 8-bit R, G, Generate B data. The 8-bit R, G, and B data obtained for each of the 32 pixels are combined into one 256-bit R, G, and B data, and output to the buffer 267. The above operations are data operations in the width of the DRAM bus B15 (for example, 256 bits). The output from the output buffer 267 to the outside is converted into 256-bit data in 8-pixel units in order to output the data in units of pixels. R, G,
The B data is output from the output buffer 267 to the external data bus B22 in parallel. Therefore, in the present example, the external data bus B22 only needs to be 24 bits.

As described above, in the present embodiment, the extended operation unit 12 can transfer image data for a plurality of pixels at a time using the extended data bus B12. As a result, the extended operation unit 12
As a result, the time during which the data processing unit 11 can access the DRAM 15 for other processing becomes longer than before, and the processing capability of the data processing unit 11 improves.

<Modifications of Second Embodiment of the Invention> Various modifications described for the second embodiment are also applicable to the second embodiment.

For example, as in the first embodiment of the invention,
The data width of the data that can be processed by the extended operation unit 12 is narrower than the DRAM bus B15, but may be wider than the data width of the data that the data processing unit 11 can process. At this time, the data width of each register in the register group 124 in the extended arithmetic unit 12, the data width of the internal data bus, the data width of the data processed by the arithmetic unit 123, and the data width of the extended data bus B12 are also new. What is necessary is just to match the data width. Further, at this time, the aligner 139 shown in FIG. 6 is required. For example, when the extended data bus B12 has 128 bits, the aligner 139 may be configured to cut out the first 128 bits or the last 128 bits of the 256 bits read from the DRAM 15 and transfer the extracted data to the extended data bus B12. This is the same as in the first embodiment.

The arithmetic unit constituting the extended arithmetic unit 12 may have various structures as exemplified in the first embodiment.

Further, although a DRAM suitable for a large-capacity memory is used as the on-chip memory in the above description, another memory can be used instead.

[0067]

According to the present invention, a microprocessor capable of efficiently processing data in a memory arranged on the same LSI as a data processing unit (processor) can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a microprocessor according to the present invention.

FIG. 2 is a schematic block diagram of a bus selector used in the apparatus of FIG.

FIG. 3 is a view for explaining execution of an operation by a data processing unit in the apparatus of FIG. 1;

FIG. 4 is a view for explaining execution of an operation by an extended operation unit in the apparatus of FIG. 1;

FIG. 5 is a diagram showing a second embodiment of a microprocessor according to the present invention.

FIG. 6 is a schematic block diagram of a bus selector used in the device of FIG.

FIG. 7 is a schematic block diagram of an extended operation unit used in the device of FIG. 5;

FIG. 8 is a schematic block diagram of a conventional microprocessor.

FIG. 9 is a schematic block diagram of another conventional microprocessor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Microprocessor, 11 ... Data processing unit,
12: Extended operation unit, 136, 137: Read / write buffer.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification FI FI Theme Court ゛ (Reference) G06F 15/78 510 G06F 15/78 510A (72) Inventor Junko Nakase 5-chome, Kamisumihonmachi, Kodaira-shi, Tokyo No. 1 Hitachi, Ltd. System LSI Development Center (72) Inventor Takashi Nakamoto 5-2-1 Kamisumihonmachi, Kodaira-shi, Tokyo F-term, Hitachi System LSI Development Center (Reference) 5B033 AA03 AA14 DB04 DB09 DC04 DD09 5B060 MB03 5B061 FF02 GG02 5B062 AA03 CC01 DD10

Claims (20)

[Claims] 1. A data processing unit for executing a process specified by an instruction on data having a data width equal to or less than a first data width; An extended operation unit capable of executing an operation on data of a width, and a dynamic random access memory (D
RAM), a first data bus connected to the data processing unit and having the first data width for exchanging data with the data processing unit, and connected to the extended arithmetic unit. A second data bus having the second data width for exchanging data with the extended operation unit, and a second data bus connected to the DRAM for exchanging data to be read / written with the DRAM. A single semiconductor integrated circuit comprising: a third data bus having a third data width; and a bus selection circuit for switching one of the first and second data buses and connecting to the third data bus. A microprocessor on a chip. 2. The bus selection circuit is capable of bidirectional data transfer between the data processing unit and the DRAM, and bidirectional data transfer between the extended operation unit and the DRAM. The microprocessor according to claim 1, wherein 3. The first bus selection circuit requests a data transfer between the data processing unit and the DRAM.
In response to a second type instruction that requests data transfer between the extended operation unit and the DRAM,
3. The microprocessor according to claim 1, further comprising a circuit that connects the first data bus or the second data bus to the third data bus. 4. The data bus connected to the second data bus,
A cache for holding data or instructions read from the RAM, an instruction decoder connected to the second data bus for decoding instructions read from the DRAM, and a second data bus And a bus interface circuit for transferring data between the microprocessor and a device connected to the microprocessor via a data bus external to the microprocessor. A microprocessor according to any one of the preceding claims. 5. The data processing unit according to claim 1, wherein said data processing unit is a first type instruction for requesting data transfer between said data processing unit and said DRAM or said extended operation unit and said D / A processing unit.
The data processing unit and the DRA are respectively responsive to a second type of instruction requesting data transfer to and from the RAM.
A first type of memory access request for requesting data transfer to / from the M or a second type of memory access request for requesting data transfer between the extended operation unit and the DRAM is supplied to the bus selection circuit. 5. The microprocessor according to claim 1, further comprising a memory access request circuit. 6. The extended operation unit, wherein the extended operation unit is capable of executing an operation on data having a data width equal to or less than the second data width, and each of the extended operation units is connected to the extended operation unit. A plurality of extension registers which hold data to be operated or operation result data by the extension operation unit, each having the second data width, and each of which can be designated by an instruction requesting processing by the extension operation unit; A control circuit connected to the plurality of extension registers, for controlling transfer of data of the second data width between the second data bus and any of the plurality of extension registers; The extended operation unit is capable of executing one operation specified by an instruction requesting an operation by the extended operation unit, out of a plurality of predetermined operations. A microprocessor according to any one of claims 1 to 5. 7. The extended computing unit according to claim 6, wherein said extended computing unit includes a plurality of computing units for executing the same operation in parallel on different portions of data having a data width smaller than said second data width. Microprocessor. 8. A data processing unit comprising: a basic operation unit capable of executing an operation on data having a data width equal to or smaller than the first data width; and a basic operation unit connected to each of the basic operation units. Holds data to be operated or operation result data by the basic operation unit, each having the first data width, and can be designated by an instruction requesting processing by the data processing unit or the extended operation unit, respectively. A plurality of basic registers, and a control circuit connected to the plurality of basic registers, for controlling transfer of data of the first data width between the first data bus and any of the plurality of basic registers. The basic arithmetic unit further comprises: an instruction requesting an operation by the data processing unit among a plurality of predetermined operations. The memory access request circuit is connected to the plurality of basic registers and requests a data transfer between any of the plurality of basic registers and the DRAM; Any of the plurality of extension registers and the DR
Between the data processing unit and the DRAM based on address data held in at least one of the plurality of basic registers specified by a second type instruction requesting data transfer to and from the AM. A first type of memory access request for requesting data transfer or a second type of request for data transfer between the extended operation unit and the DRAM
8. The microprocessor according to claim 6, further comprising a memory access request circuit for supplying a kind of memory access request to said bus selection circuit. 9. The microprocessor according to claim 1, wherein said second data width is equal to said third data width. 10. The microprocessor according to claim 9, wherein said first data width is 32 bits, and said second and third data widths are 256 bits. 11. A data processing unit for executing a process specified by an instruction on data having a data width equal to or smaller than a first data width, and data having a width larger than the first data width and equal to or smaller than a second data width. An extended operation unit capable of executing an operation on data having a width, and a dynamic random access memory (D) capable of reading and writing data having a third data width equal to or larger than the second data width.
RAM), a first data bus connected to the data processing unit and having the first data width for exchanging data with the data processing unit, and connected to the extended arithmetic unit. A second data bus having the second data width for exchanging data with the extended operation unit, and a second data bus connected to the DRAM for exchanging data to be read / written with the DRAM. A third data bus having a third data width, a fourth data width not greater than the first data width,
A fourth data bus for connecting to a device provided outside the microprocessor, a bus interface circuit for controlling data transfer between the first data bus and the fourth data bus, A microprocessor having, on a single semiconductor integrated circuit chip, a bus selection circuit for switching one of the second and fourth data buses to connect to the third data bus. 12. The bus selection circuit is capable of bidirectional data transfer between the data processing unit and the DRAM, and is capable of data transfer from the DRAM to the extended operation unit. Item 11. The microprocessor according to Item 10. 13. The bus selection circuit according to claim 1, further comprising: an instruction for requesting data transfer from said data processing unit via said bus interface circuit to said DRAM, or said DRA when supplied from said extended operation unit.
13. The circuit according to claim 11, further comprising a circuit for connecting the fourth data bus or the second data bus to the third data bus in response to an instruction requesting data transfer to and from the M bus. Microprocessor. 14. A cache connected to the first data bus for holding data or instructions read from the DRAM, and a cache connected to the first data bus and read from the DRAM. 4. The microprocessor according to claim 1, further comprising an instruction decoder for decoding an instruction. 15. A data transfer unit between said data processing unit and said DRAM in response to a first type command requesting data transfer between said data processing unit and said DRAM. Is supplied to the bus interface circuit, and requests the extended operation unit to write a plurality of memory addresses designating a plurality of data to be read from the DRAM to the extended operation unit. A memory access request circuit that supplies a plurality of second type memory write requests to the bus interface circuit in response to the plurality of second type instructions; the bus interface circuit includes the first type memory access Request and the plurality of second type memory access requests are respectively sent to the bus selection circuit and And a plurality of address registers connected to the fourth data bus for holding a memory address of a plurality of data to be read from the DRAM. A circuit connected to the fourth data bus and writing the plurality of memory addresses specified by the plurality of second type memory access instructions transferred from the bus interface circuit into a plurality of registers; And a circuit for supplying a plurality of memory access requests respectively designating the plurality of memory addresses to the bus selection circuit, wherein the bus selection circuit transfers the first type of memory transferred from the bus interface circuit. Connecting the third data bus and the fourth data bus in response to an access request; Claims 11 in response to each of the extended arithmetic unit supply the plurality of memory access requests for connecting the third data bus and the second data bus 1
5. The microprocessor according to any one of 4. 16. The extended operation unit, wherein the extended operation unit is capable of executing a predetermined operation on data having a data width equal to or less than the second data width, and is connected to the second data bus; 16. A plurality of extension registers, each holding a plurality of data to be subjected to an operation by the extension operation unit and read from the DRAM via the data bus, and each of the extension registers having the second data width. Microprocessor. 17. The extended arithmetic unit according to claim 16, wherein said extended arithmetic unit includes a plurality of arithmetic units for executing the same operation in parallel on different portions of data having a data width smaller than said second data width. Microprocessor. 18. A data processing unit comprising: a basic operation unit capable of executing an operation on data having a data width equal to or smaller than the first data width; A plurality of basic registers, each holding data to be subjected to an operation or operation result data by the basic operation unit, each having the first data width, and each of which can be specified by an instruction; A control circuit for controlling the transfer of the data having the first data width between the first data bus and any of the plurality of basic registers. 18. The microprocessor according to claim 16, wherein an operation specified by an instruction requesting an operation by said data processing unit is executable among a plurality of operations. Ssa. 19. The microprocessor according to claim 11, wherein said second data width is equal to said third data width. 20. The first data width is 32 bits, and the second and third data widths are 256 bits.
The microprocessor as described.