JP2000232619A - Dynamic picture recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To record a dynamic picture for a long time by using an SDRAM as a ring buffer. SOLUTION: When a shutter button 58 is depressed, compression processing by a JPEG CODEC 30 is applied to photographed still picture data of each frame. A synchronous(S) DRAM 28 acting like a ring buffer stores the generated compressed picture data. The SDRAM 28 reads the compressed picture data in parallel with the write processing above and a memory card 36d stores the read pictures data. As a result, the memory card 36 records moving pictures for a long time. Moreover, a read speed from the SDARM 28 is slower that its write speed. Thus, when the write position approaches the read position and the both have a prescribed relation, the write is stopped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving image recording apparatus, and more particularly to a moving image recording apparatus which is applied to, for example, a digital camera and records a plurality of frames of image data on a recording medium in response to a recording instruction.

[0002]

2. Description of the Related Art In a conventional digital camera, when a shutter button is pressed, compression processing of moving image data is started, and the generated compressed moving image data is temporarily stored in an internal memory. Thereafter, when the shutter button is turned off, the compression processing is stopped, and the compressed moving image data stored in the internal memory is collectively recorded on the recording medium.

[0003]

However, in such a conventional technique, since the compressed moving image data is recorded on a recording medium via an internal memory, the continuous recording time depends on the capacity of the internal memory. There was a problem that would.
Therefore, a main object of the present invention is to provide a moving image recording device capable of recording a long moving image regardless of the memory capacity.

[0004]

SUMMARY OF THE INVENTION The present invention relates to a moving image recording apparatus for recording a plurality of frames of image data on a recording medium in response to a recording instruction. Writing means, image reading means for cyclically reading out image data from the internal memory and recording it on a recording medium, and disabling the image writing means when the image writing position and the image reading position have a predetermined relationship. A moving image recording apparatus characterized by comprising means.

[0005]

The image writing means cyclically writes the image data to the internal memory, and the image reading means cyclically reads the image data from the internal memory and records it on the recording medium.
The writing means is disabled by the disablement means when the image writing position and the image reading position have a predetermined relationship.

In one aspect of the present invention, the internal memory has a plurality of image blocks, and each image block has a capacity corresponding to a predetermined number of frames of image data. In one embodiment of the present invention, the image writing means operates as follows. That is, the designating means designates each of the image blocks one by one and cyclically, and the image data writing means writes a predetermined number of frames of image data into the designated image block.

In another embodiment of the present invention, a plurality of block flags respectively correspond to a plurality of image blocks, and the state of each block flag indicates an access state to the corresponding image block. In the image writing means, each time writing to one image block is completed, the setting means sets a corresponding block flag. Further, each time reading from one image block is completed, the reset means resets the corresponding block flag. In the image reading means, the image data reading means reads image data by a predetermined number of bytes from one image block.
Further, the updating means updates the read address each time reading of a predetermined number of bytes is completed. The reset unit detects the read address, and determines completion of reading from the image block based on the detection result. The disabling means disables the image writing means according to the state of such a block flag.

[0008] In another aspect of the present invention, the compression means compresses image data of a plurality of frames. Therefore, the image writing unit writes the compressed image data compressed by the compression unit to the internal memory, and the image reading unit reads the compressed image data from the internal memory.

[0009]

According to the present invention, the image data is cyclically written to the internal memory, and thereafter, the image data is cyclically read from the internal memory and recorded on the recording medium. Therefore, the capacity of the internal memory is small. A long-time moving image can be recorded at any time. Further, since the image writing unit is disabled when the image writing position and the image reading position have a predetermined relationship, the image data that has not been read out is not overwritten by the subsequent image data.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a digital camera 10 of this embodiment includes a CCD imager 12. A color filter (not shown) is mounted on a front surface of the CCD imager 12, and a light image of a subject is irradiated on the CCD imager 12 through the color filter. When the mode changeover switch 60 is switched to the “camera” side, the system controller 5
4 sets the camera mode. The timing generator (TG) 14 generates a timing signal based on the vertical synchronizing signal and the horizontal synchronizing signal output from the signal generator (SG) 16, and drives the CCD imager 12 by a progressive scan method. As a result, the camera signal of each frame is output from the CCD imager 12 every 1/15 second. The output camera signal is CDS
The A / D converter 16 performs well-known noise removal and level adjustment, and then converts the digital data into camera data as a digital signal by the A / D converter 16. The signal processing circuit 22 performs YUV conversion on the camera data output from the A / D converter 16 to generate YUV data. CCD
Since the imager 12 outputs the camera signal of each frame every 1/15 second, the YUV data (still image data) of each frame is also output every 1/15 second. The signal processing circuit 22 outputs the still image data thus generated to the memory control circuit 26 together with the write request.

The memory control circuit 26 writes still image data to the SDRAM 28 in response to the write request. A display image area as shown in FIG. 3 is formed in the SDRAM 54, and the still image data is written here. The display image area has a capacity of only one frame, and the still image data of each frame is updated every 1/15 second. On the other hand, the video encoder 38 outputs a request signal every 1/15 second, and the memory control circuit 26 reads out still image data from the display image area every 1/15 second. The read still image data of each frame is supplied to the video encoder 38 via the bus 24a. Note that an interlaced scan method is used for reading out still image data.

The video encoder 38 generates an NTSC format composite image signal from the input still image data of each frame, and supplies the generated composite image signal to the monitor 40. As a result, a moving image of the subject image is displayed on the monitor 40 in real time. When the operator presses the shutter button 58, the system controller 54 instructs the CPU 32 to perform a moving image and audio recording process. Then, the CPU 32 generates an image compression command and a sound processing command every 1/15 seconds. The image compression instruction is given to the JPEG codec 30 and the audio processing instruction is given to the signal processing circuit 46.

The JPEG codec 30 outputs a read request to the memory control circuit 26 in response to the image compression command. Therefore, the still image data stored in the display image area of the SDRAM 28 is read out by the memory control circuit 26 every 1/15 second. The read still image data is transmitted to the JPEG codec 3 via the bus 24a.
0 and JPEG compressed. The JPEG codec 30 requests the memory control circuit 26 to write such compressed image data every time one frame of compressed image data is obtained. In response, the memory control circuit 26 writes the compressed image data of each frame into the compressed image area shown in FIG. In the compressed image area,
A plurality of image blocks capable of storing 15 frames of compressed image data are formed, and the compressed image data is written into each compressed image block by 15 frames.

On the other hand, the signal processing circuit 46 fetches audio data from the A / D converter 44 in response to the audio processing command. That is, the audio data captured by the microphone 42 and subjected to A / D conversion is captured. Then, predetermined processing is performed on the fetched audio data, and the processed audio data is output to the memory control circuit 26 together with a write request. Since the audio processing command is given every 1/15 second, audio data of 1/15 second, that is, 524 bytes, is output to the memory control circuit 46. Memory control circuit 26
Responds to the write request with such a 524
The byte audio data is written in the audio area shown in FIG. In the audio area, an audio block capable of storing one second (7866 bytes) of audio data is formed, and the audio data is written to such an audio block one second at a time.

The CPU 32 also outputs 15 frames of compressed image data and 1 second of audio data to the SDRAM 28.
Each time it is written to the memory, image header data and audio header data are created, and the writing of these header data is requested to the memory control circuit 26. The memory control circuit 26 converts the image header data and the audio header data into
Write to the header block formed in the header area shown in FIG. Note that the image header data and the audio header data related to each other are written in the same header block. By executing the writing process in this manner, the compressed image data, audio data, and header data corresponding to each other are written into image blocks, audio blocks, and header blocks having the same coefficients.

The CPU 32 also requests the memory control circuit 26 to read data. In response to such a request, the memory control circuit 26 starts from the blocks having the same coefficient, the audio header, the audio, the image header,
Read data in the order of images. First, audio header data is read from the header block, and audio data for one second is read from the audio block. Next, image header data is read from the header block, and 15 frames of compressed image data are read from the image block. CP
U32 records the data thus read out on the memory card 36.

An AVI (Audio Video Interface) is stored in the memory card 36 in response to the first operation of the shutter button 58.
eave) File header is newly created and SDRAM
The data read from 28 is written after the file header. As a result, as shown in FIG. 2, audio chunks composed of audio data for one second and image chunks composed of compressed image data for 15 frames are alternately formed. The audio header data is provided at the head of the audio chunk, and the image header data is provided at the head of the image chunk. In this embodiment, a moving image for one second is composed of 15 frames, and one audio chunk and one subsequent image chunk correspond to each other.

When the shutter button 58 is turned off, CP
U32 stops outputting the audio processing command to the signal processing circuit 46 and outputting the image compression command to the JPEG codec 30. That is, the process of writing data to the SDRAM 28 is stopped. However, the recording process is SD
The process ends when all data in the RAM 28 has been recorded on the memory card 36.

Referring to FIG. 3, when writing to block (N-1) is completed by the writing process, the next write destination is block 0. When reading from the block (N-1) is completed by the recording process, the next read destination is the block (N-1). That is, SDR
The AM 28 operates as a ring buffer, and the write block and the read block are updated in a ring, that is, cyclically in each of the compressed image area, the audio area, and the header area. However, the speed of writing data to the SDARM 28 does not always match the speed of reading data from the SDRAM 28. Rather, the data write speed is faster than the data read speed. Therefore, when the write block catches up with the read block, the write mode is forcibly stopped even if the shutter button 58 is in the ON state. As a result, subsequent data is not overwritten on data that has not been read yet. The recording process is terminated when all data in the SDRAM 28 has been recorded on the memory card 36, as described above.

Note that the video encoder 38 issues a read request every 1/15 second even while the shutter button 58 is pressed, and the memory control circuit 28 reads out still image data of each frame from the display image area. Therefore, the same moving image as the moving image recorded on the memory card 36 is displayed on the monitor 40. When the write block catches up with the read block and the write mode is forcibly stopped, the still image at the time of the stop is continuously displayed on the monitor 40.

When the shutter button 58 is operated, C
The PU 32 executes a write mode process (write process) shown in FIGS. 5 to 7 and a BG mode process (recording process) shown in FIGS. That is, the CPU 32 is equipped with a multitask OS such as μiTRON, and these processes are executed in parallel. In the writing mode processing, a subroutine is processed as shown in FIGS. First, referring to FIG.
32 is a step S32 in response to the pressing of the shutter button 58;
Process 1. In step S1, FIG. 10 and FIG.
Various variables are initialized by the subroutine shown in FIG. Next, in step S3, the CPU 32 executes BG (Back Gro
und) mode is started, and a BG mode flag _fBG is set in step S5. When the BG mode is activated, FIG.
And the routine shown in FIG. 9 are processed in parallel.

In a step S7, it is determined whether or not the block flag fn is set. In the first step S7, the block flag f1 is to be determined. By the initialization processing in step S1, the block number n
Is set to “0”, and all the block flags f
Since 0 to f (N-1) are reset, the determination result at this time is YES. Note that the block flag fn is
It corresponds to image block n, audio block n, and header block n.

When proceeding to step S9, the CPU 32
2 and the subroutine shown in FIG. 13 to write compressed image data, audio data, and header data to the image block n, the audio block n, and the header block n, respectively. When the writing is completed, the block flag fn is set in step S11. Block flag fn
Is set in response to completion of writing to block n, and reset in response to completion of reading from block n. For this reason, the set state of the block flag fn means that the reading of data from the block n has not been completed yet.

In step S13, the subroutine shown in FIGS. 14 to 16 is processed to create an instruction list related to block n. The created instruction list is used for BG mode processing. The CPU 32 then proceeds to step S
At 15, the count value M is compared with "14" to determine whether all data corresponding to 15 frames has been written to the block n. This makes it possible to determine whether or not the shutter button 58 has been turned off during the writing to the block n. If the shutter button 58 is turned off halfway, YES is determined in the step S15, and the step S1 is performed.
Go to 7. In a step S17, the BG flag f _BG is reset, and in a succeeding step S19, it is determined whether or not the BG mode processing is completed. If YES is determined here,
The CPU 32 ends the write mode processing.

On the other hand, if the shutter button 58 is kept depressed, the CPU 32 proceeds to step S21 to acquire the address information of the file pointer FP. Then, in a step S23, it is determined whether or not the file pointer FP satisfies the condition shown in Expression 1.

[0027]

## EQU1 ## _VSA 0 ≦ FP < _VSA 1 _ASA 0 ≦ FP < _ASA 1 _HSA 0 ≦ FP < _HSA 1 _VSA n; head address of image block n _ASA n; head of audio block n Address H _SA n; head address of header block n If any one of these conditions is satisfied, the read process in the BG mode has been performed on block 0.
At this time, the CPU 32 executes the reset processing of the block flag f _N−1 in step S25, and then proceeds to step S41.
Proceed to. On the other hand, if neither condition is satisfied, the CPU
In step S27, the block number K is set to "1" in step S27, and in step S29, it is determined whether or not the file pointer FP satisfies the condition shown in Expression 2.

[0028]

## EQU2 ## V _SA K ≦ FP <V _SA (K + 1) _ASA K ≦ FP <A _SA (K + 1) H _SA K ≦ FP <H _SA (K + 1) Again, if any one of the conditions is satisfied, , It is determined that data has been read from the block K, the block flag fK _-1 is reset in step S31, and the process proceeds to step S41. If none of the conditions is satisfied, the CPU 32 increments the block number K in step S33, and increments the current block number K in step S35.
Is compared with "N-1". Unless K = N-1,
The CPU 32 returns to step S29, and as a result, the processing of steps S29 and S33 is repeated. K = N-
When it becomes 1, the CPU 32 proceeds to step S37, and determines whether or not the file pointer FP satisfies the condition shown in Expression 3.

[0029]

Equation 3] _{V SA (N-1) ≦} FP ≦ V EA A SA (N-1) ≦ FP ≦ A EA H SA (N-1) ≦ FP ≦ H EA V EA; end address of the compressed image area A _EA : End address of voice area H _EA ; End address of header area Also in this step, it is determined that YES if any of the conditions is satisfied, and NO if none of the conditions are satisfied. The determination of YES means that the data read operation is being performed on block (N-1),
32 resets the block flag fN _-2 in step S39, and then proceeds to step S41. If the determination is NO, the CPU 32 returns to step S17.

As described above, when all the data is read from the block n by the BG mode processing, the corresponding block flag n is reset. In step S41, the block number n is incremented.
In step 3, the current block number n is compared with "N-1". If NO, the process directly proceeds to step S47, and YE
If S, the block number n is reset in step S45, and then the process proceeds to step S47. In step S47, it is determined whether or not the shutter button 58 has been turned off. If NO, the process returns to step S7. If YES, the process proceeds to step S17. As can be seen from steps S41 to S45, the block number n is reset after being incremented to "N-1". For this reason, the image block, audio block and header block to be written are cyclically designated, and the compressed image data, audio data and header data are written in a ring.

Such a cyclic writing operation is stopped at the same time when the shutter button 58 is turned off. In other words, the shutter button 5 is pressed during writing to the block n or when writing to the block n is completed.
Even when 8 is turned off, the write mode processing is stopped in response to this off operation. The data held in the SDRAM 28 is transferred to the memory card 3 by the BG mode processing.
6 is recorded.

The writing mode process includes the shutter button 5
The process is stopped not only when 8 is turned off but also when NO is determined in step S7. Such a forced stop of the write operation is performed when the speed of reading data from the SDRAM 28 is lower than the speed of writing and data is to be written to a block for which data reading has not been completed. As a result, it is possible to prevent data that has not been read yet from being overwritten by subsequent data.

The BG mode processing will be described with reference to FIG. First, in step S51, the CPU 32 resets the mail write number W _N , the mail read number _RN, and the count value m. Next, steps S53 and S55
It is determined whether the count value m is greater than “0” and whether the BG flag f _BG has been reset. If m> 0, step S53 to step S5
7, if m ≦ 0 and the BG flag f _BG is set, the process proceeds to step S53, and if m ≦ 0 and BG
If the flag f _BG is in the reset state, the process ends.

The count value m is reset in step S51, but is incremented by the above-described write mode processing, specifically, the instruction list creation processing in step S13. As a result, m> 0, and step S53
Is determined as YES. Then, the CPU 32 sets the file pointer FP to the mail read number R in step S57.
Set to the read start address corresponding to _N, set the data size corresponding to the count value S to the mail read number R _N. In the above-described step S13, an instruction list 32a as shown in FIG. 4 is created. According to FIG. 4, the read start address and the data size represented by the number of bytes are associated with each mail number. In steps S57 and S59, the current mail read number R
_A mail number having the same value as _N is detected from the instruction list 32a, and a read start address and a data size corresponding to the detected mail number are read. Then, the read address data and size data are set in the file pointer FP and the count value S, respectively.

Next, the CPU 32 proceeds to step S61 where S
It is determined whether access to the DRAM 28 is possible. While the shutter button 58 is pressed, the memory control circuit 26 receives access requests not only from the CPU 32 but also from the signal processing circuits 22 and 46, the JPEG codec 30 and the video encoder 38, and arbitrates these requests while arbitrating these requests. Write / read with respect to. Therefore, in step S61, a request is output to the memory control circuit 26, and when a permission signal is returned from the memory control circuit 26, it is determined as YES. At the time of outputting the request in step S61,
The CPU 32 also outputs address information of the file pointer FP at the same time. The memory control circuit 26 reads one byte of data from the SDRAM 28 according to such address information. Therefore, the CPU 32 receives 1-byte data following the permission signal.

The CPU 32 records the input 1-byte data on the memory card 36 in step S63, and updates the file pointer FP and the count value S in steps S65 and S67. The address information of the file pointer FP is incremented, and the count value S is decremented. In step S69, the count value S
Is compared with “0”, and if S> 0, the process returns to the step S61. As a result, the processing of steps S61 to S69 is repeated until all data corresponding to the current mail read number RN is recorded on the memory card 36.

When the count value S becomes "0", the CPU 3
2 determines that the read process of the data corresponding to the current mail read number R _N has been completed, decrements the count value m in step S71. The count value m is incremented by the instruction list creation process, and is decremented in this step. Therefore, the count value m
Means the amount of data written to the SDRAM 28 and not yet read.

Thereafter, the CPU 32 proceeds to step S73 to send a message.
Reading number R_NIs incremented, and step S
The current mail read number R at 75_NTo "L-1"
You. As can be seen from FIG. 4, "L-1" is the mail number
This is the maximum value (for example, 1999). Therefore, R_N≤
If it is L-1, the process directly proceeds to step S79. _N
If> L-1, the mail reading number is set in step S75.
No.R_NIs reset, and the process proceeds to step S79. this
Result, mail read number R_NIs also updated cyclically.

In the step S79, the count value m is set to "L".
Normally, the count value m does not exceed "L-1", and the CPU 32 determines NO in this step and returns to step S53. As a result, the processing in steps S53 to S79 described above. Are repeated, and SDRAM2
8 is sequentially recorded on the memory card 36. On the other hand, when the count value m has exceeded “L−1”, YES is determined in the step S79, and the BG mode processing is ended through the error processing in the step S81. m> L−1 is when the decrement speed of the count value m is lower than the increment speed, that is, S
This occurs when the reading speed from the DRAM 28 is lower than the writing speed. In such a case, the BG mode processing is forcibly terminated.

With reference to FIG. 10 and FIG. 11, a specific process for initializing various variables will be described. CPU3
2. First, in step S101, the start address V _SA 0 of image block 0 is set to the start address V _S of the compressed image area, and the start address A _SA 0 of audio block 0 is set to the start address A _S of the audio area. Then, the head address H _SA 0 of the header block 0 is set to the head address H _S of the header area. Next, in step S103, the block flag f0 and the block number n are reset,
In step S105, the count value M is set to "14" and the block number j is set to "1".

The CPU 32 then proceeds to step S107, where the start address V of the image block j is calculated according to equation (4).
_SA j, calculates a head address H _SA j of the head address A _SA j and header block j of the sound block j.

[0042]

(Equation 4)_SAj = V_SA(J-1) + V_MAXSIZE× 15 A_SAj = A_SA(J-1) + A_SIZE H_SAj = H_SA(J-1) + H_AVSIZE V_MAXSIZEThe maximum size of one frame of compressed image data H_AVSIZEThe size of the audio header and the image header The size of the compressed image data differs depending on the subject image,
Maximum size V_MAXSIZEIs predetermined. others
"V_MAXSIZE× 15 ”is the start address V_SA(J-
1) is added to the start address V_SASeeking i. one
On the other hand, audio data is not compressed,
Is A_SIZEIs known from the beginning. Therefore, "A
_SIZE"To the start address A_SABy adding to (j-1)
Start address A _SAj is determined. About header data
However, since the size is already known from the beginning,
By the start address H_SAj is determined. Note that H
_AVSIZEIs one audio header and one image header
This is the total size.

In step S109, the block flag fj
Is reset, and in step S111, the block number j is incremented. Thereafter, in step S113, the current block number j is compared with "N-1", and if j≤N-1, the process returns to step S107. Therefore, step S1
07 to S111 are repeated, and the image blocks 1 to
The head addresses of (N-1), audio blocks 1 to (N-1) and header blocks 1 to (N-1) are calculated. Through the processing of steps S107 to S111 and the processing of the first step S101, N image blocks, N audio blocks, and N header blocks are formed in the SDRAM 28 as shown in FIG.

[0044] When YES is determined in step S113, CPU 32 proceeds to step S115, sets the image write address V _WA and image read address V _RA to the head address V _SA 0 of the image block 0, a sound write address A _WA The audio read address A _RA is set to the head address A _SA 0 of the audio block 0, and the header write address H _WA and the header read address H _RA are set to the head address H _SA 0 of the header block 0.

Subsequently, in step S117, the audio block
Size A of audio data to be written to 0 _SIZETo “0”,
In step S119, the frame number i is reset. S
In step S121, the compressed image data of the i-th frame is
Is V_SIZEi is set to “0”, and in the subsequent step S123
Increment the block number i. And step
In step S125, the block number i is counted by the count value M (= 14).
And steps S121 and S121 until i> M.
Step 123 is repeated. As a result,
Are set to "0". i> M
Then, the CPU 32 returns to the routine shown in FIG.

Referring to FIG. 12, the write processing for block n will be described. The CPU 32 first resets the frame number i in step S901, and clears the FIFO memory 46a provided in the signal processing circuit 46 in step S903. Subsequently, in step S905, the image write address V _WA is set to the head address V _SA n of the image block n, the audio write address A _WA is set to the head address A _SA n of the audio block n, and the header write address H _WA Is set to the head address H _SA n of the header block n. Thereafter, when a vertical synchronization signal is output from the SG 16, the CPU 32 proceeds to step S90.
7 is determined as YES, and an image compression instruction is output to the JPEG codec 30 in step S909. When outputting the image compression command, the CPU 32 also outputs the image write address _VWA to the JPEG codec 30.

The JPEG codec 30 requests the memory control circuit 26 to read out still image data in response to the image compression command. As a result, one frame of still image data stored in the display image area shown in FIG. 3 is read by the memory control circuit 26 and input to the JPEG codec 30 via the buses 24b and 24a.
The JPEG codec 30 performs JPEG compression on the input still image data to generate compressed image data. 1
When the frame compression processing is completed, the JPEG codec 30 requests the memory control circuit 26 to write such compressed image data. On request, JPEG
The codec 30 outputs the above-described image write address V _WA to the memory control circuit 26 in addition to the compressed image data and the request signal. In response, the memory control circuit 26 writes the given compressed image data to the image write address _{VWA and} thereafter.

After outputting the image compression command in step S909, the CPU 32 determines in step S911 whether the compression processing has been completed. Here, if it is determined that the compression process has been completed, the CPU 32 proceeds to step S913,
Data size V _SIZE i of the compressed image data generated this time
To get. The JPEG codec 30 outputs an end signal and a data size signal each time compression processing for one frame ends. Therefore, in step S911, the presence or absence of the end of the compression processing is determined based on such an end signal, and in step S913, the data size V _SIZE i is detected from the data size signal. In step S915, equation 5
And updates the image write address V _WA according to the data size V _SIZE i.

[0049]

V _WA = V _WA + V _SIZE i The CPU 32 then, in step S917, sends the audio processing instruction together with the audio write address A _WA to the signal processing circuit 46.
Give to. The audio signal captured by the microphone 42 is A / D
The data is converted by the converter 44 into audio data. Signal processing circuit 4
6 receives such audio data in response to the audio processing command, and writes the audio data into the FIFO memory 46a. The signal processing circuit 46 also reads out audio data of 1/15 second, that is, A _SIZE / 15 bytes, from the FIFO memory 46a,
The request signal and the audio write address _AWA are output to the memory control circuit 26. As a result, the audio data of A _SIZE / 15 bytes output from the signal processing circuit 46 is written by the memory control circuit 26 after the audio write address A _WA .

After outputting the voice processing command in step S917, the CPU 32 updates the voice write address A _{WA in} accordance with equation (6) in step S919. That is, 1/1
Because the size of the audio data for 5 seconds is known in advance,
The audio write address _AWA is updated without receiving the data size signal from the signal processing circuit 46.

[0051]

A _WA = A _WA + A _SIZE / 15 In step S921, it is determined whether or not the shutter button 58 has been turned off. If YES here, CPU 3
2 sets the current frame number number to the count value M in step S923, and proceeds to step S929. If the shutter button 58 is kept pressed, the CPU 32 increments the frame number i in step S925, and increments the current frame number i by the count value M (= 1 in step S927).
Compare with 4). Here, if i ≦ M, the CPU 32 returns to step S907 and repeats the above processing.
If it is M, the process proceeds to step S929.

In step S929, the audio data
Audio header data and compressed image data
Creates image header data corresponding to the
In 931, these header data are transmitted as a request signal and
Header write address H_WAWith memory control circuit 2
6 is output. The memory control circuit 26 receives the given voice.
Header data and image header data in this order
Write address H _WAWrite later. And
In step S923, the header write address H is calculated according to Equation 7.
_WAIs updated, and the routine returns to the routine shown in FIG.

[0053]

H _WA = H _WA + H _ASIZE + H _VSIZE H _ASIZE ; size of audio header data H _VSIZE ; size of image header data As a result of such writing processing, 15 frames (or less than 15 frames) are obtained. Compressed image data is stored in image block n, audio data for one second (or less than one second) is stored in audio block n, and corresponding header data is stored in header block n.

The instruction list creation processing in step S13 in FIG. 5 will be described in detail with reference to FIGS.
First, the CPU 32 resets the frame number i in step S1301. Next, in step S1303, the start address V _SA n of the image block n, the start address A _SA n of the audio block n, and the start address H _SA n of the header block n are set to the image read address V _RA , audio read address A _RA and header read. Each is set to the address H _RA .

Subsequently, the CPU 32 proceeds to step S1305, and writes the header read address H _RA and the audio header size H _ASIZE into the instruction list 32a shown in FIG. Specifically, a mail number having the same value as the current mail write number W _N is detected, and a header read address H _RA and a voice header size H _ASIZE are written at a position corresponding to the detected mail number. The mail write number W _N is shown in FIG.
Is reset in the step S51 shown in FIG. ₇ , the header read address H _RA and the audio header size H _ASIZE are written at the position corresponding to W _N = 0 in the first process of the step S1305. Thereafter, the CPU 32 increments the mail write number W _N and the count value m in step S1307, and compares the current mail write number W _N with “L−1” in step S1309. If W _N ≦ L−1, the process directly proceeds to step S1313. If W _N > L−1, the mail write number W _N is reset in step S1311 and then step S1
Proceed to 313.

In step S1313, the count value m is compared with "L-1". The count value m is usually m ≦ L
The condition of -1 is satisfied. For this reason, the CPU 32 determines in step S1317 the header read address H _RA according to equation 8.
Is updated, and thereafter, the process proceeds to step S1319.

[0057]

H _RA = H _RA + H _ASIZE Since the BG mode processing is abnormally slow, the count value m
Is larger than the decrement speed, and if m> L−1, step S1313
Is determined as YES. At this time, the CPU 32 performs error processing in step S1315, and forcibly ends the write mode processing.

[0058] In step S1319, writes to the instruction list 32a in association with each speech read address A _RA and sound size A _SIZE the current mail read number R _N. C
Subsequently, in steps S1312 to S1327, the PU 32 performs the same processing as in steps S1307 to S1313 described above. If YES in step S1313, the process proceeds to step S1315, and if NO, step S1
Proceed to 329. Note that the audio read address _ARA is no longer required, so that no update processing is performed.

[0059] In step S1329, writes the header read address H _RA and image header size H _VSIZE to the instruction list 32a in association with the current mail read number R _N. Then, in steps S1331 to S1337, the same processing as in steps S1307 to S1313 described above is performed. When NO is determined in step S1337, the process proceeds to step S1341.

[0060] CPU32 then proceeds to step S 1341, written in positions corresponding to the current mail read number R _N of the image read address V _RA and above image size V _SIZE i of the instruction list 32a acquired in step S913. Then, the same process as in step S1307~S1313 in step S1343～S1349, when it is judged NO in step S1349, updates the image read address V _RA according to Equation 9 in step S1351.

[0061]

V _RA = V _RA + V _SIZE i When the address data and the size data related to the i-th frame image are written in the instruction list 32a in this way, the CPU 32 increments the frame number i in step S1353. Then, step S13
In step 35, the current frame number i is compared with the count value M (= 14), and steps S1329 to S135 are performed until i> M.
Step 3 is repeated. As a result, address data and size data relating to the compressed image data for 15 frames written in the image block n are secured in the instruction list 32a. If i> M, the CPU 32 proceeds to step S
YES is determined in 1335, and the process returns to the routine shown in FIG.

According to this embodiment, when writing compressed image data, audio data and header data to the SDRAM, the compressed image area, audio area and header area are accessed cyclically. When these data are read, the compressed image area, audio area and header area are accessed cyclically. For this reason, even when the capacity of the SDRAM is small, a long-time moving image and sound can be recorded on the memory card. Further, since the writing speed to the SDRAM is faster than the reading speed, when the writing block catches up with the reading block, the writing mode is forcibly stopped. For this reason,
Data that has not yet been read can be prevented from being overwritten by subsequent data.

In this embodiment, JPEG-compressed image data is recorded on the memory card. However, the image data recorded on the memory card may be MPEG-compressed compressed data. May be image data not subjected to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an illustrative view showing an AVI file;

FIG. 3 is an illustrative view showing an SDRAM;

FIG. 4 is an illustrative view showing an instruction list;

FIG. 5 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 6 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

FIG. 7 is a flowchart showing a part of the operation of the embodiment in FIG. 1;

FIG. 8 is a flowchart showing yet another portion of the operation of the embodiment in FIG. 1;

FIG. 9 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

FIG. 10 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

FIG. 11 is a flowchart showing yet another portion of the operation of the embodiment in FIG. 1;

FIG. 12 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

FIG. 13 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

FIG. 14 is a flowchart showing yet another portion of the operation of the embodiment in FIG. 1;

FIG. 15 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

FIG. 16 is a flowchart showing another portion of the operation of the embodiment in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Digital camera 26 ... Memory control circuit 28 ... SDRAM 30 ... JPEG codec 32 ... CPU 36 ... Memory card 38 ... Video encoder 46 ... Signal processing circuit

[Procedure amendment]

[Submission Date] January 20, 2000 (2000.1.2
0)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claim 2

[Correction method] Change

[Correction contents]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] Claim 3

[Correction method] Change

[Correction contents]

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] Claim 8

[Correction method] Change

[Correction contents]

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] Claim 9

[Correction method] Change

[Correction contents]

Claims (10)

[Claims] 1. A moving image recording apparatus for recording a plurality of frames of image data on a recording medium in response to a recording instruction, comprising: an internal memory; an image writing unit for cyclically writing the image data to the internal memory; Read out from the internal memory and recorded on a recording medium, and disabling means disabling the image writing means when an image writing position and an image reading position have a predetermined relationship. A moving image recording apparatus, characterized in that: 2. The moving image recording apparatus according to claim 1, wherein said internal memory has a plurality of image blocks, and each image block has a capacity corresponding to a predetermined number of frames of image data. 3. The image writing means according to claim 1, wherein said image writing means designates each image block one at a time and cyclically, and image data for writing said predetermined number of frames of image data into said image block designated by said designation means. 3. The moving image recording apparatus according to claim 2, further comprising a writing unit. 4. The moving image recording apparatus according to claim 2, further comprising a plurality of block flags respectively corresponding to said plurality of image blocks and indicating an access state. 5. An image writing means for setting a corresponding block flag each time writing to one image block is completed, and a corresponding block flag each time reading from one image block is completed. 5. The moving image recording apparatus according to claim 4, further comprising a reset unit for resetting the image. 6. The image reading means includes: image data reading means for reading the image data by a predetermined number of bytes from one image block; and updating means for updating a read address each time the reading of the predetermined number of bytes is completed. 6. The moving image recording apparatus according to claim 5, wherein the reset unit includes: a detection unit that detects the read address; and a determination unit that determines completion of reading from the image block based on a detection result of the detection unit. apparatus. 7. The moving picture recording apparatus according to claim 4, wherein said disabling means disables said image writing means according to a state of said block flag. 8. The image processing apparatus according to claim 1, further comprising compression means for compressing the image data of the plurality of frames, wherein the image writing means writes the compressed image data compressed by the compression means to the internal memory, and wherein the image reading means comprises the compressed image data. The moving image recording device according to claim 1, wherein data is read from the internal memory. 9. A photographing means for photographing a subject image and generating image data of the plurality of frames.
9. The moving image recording apparatus according to any one of claims 8 to 8. 10. Audio writing means for writing audio data corresponding to said image data in said internal memory cyclically.
10. The moving image recording apparatus according to claim 1, further comprising an audio reading unit that reads the audio data cyclically from the internal memory and records the audio data on a recording medium.