JP2000228710A - Image sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the linearity of an automatic gain control(AGC) function with respect to time and a luminous quantity by resetting unnecessary storage charges of a luminous quantity monitor at an increased time from an unsaturated state of a floating diffusion amplifier FDA in the FDA, which uses a time for an integration time of charges for a photo sensor to detect the luminous quantity, that is, the time interval when the storage unnecessary charges of the floating diffusion amplifier FDA receiving a high level voltage to a reset gate RSG in advance are reset until the FDA stores charges through the reception of light with a mean luminous quantity, the monitor output decreases and a level at a point A of a comparator is lower than an AGC level. SOLUTION: A signal applied to a reset gate RSG of a luminous quantity monitor is used for an RSG control signal 53 generated by a D flip-flop 18 in place of a conventional ICG control signal 50 whose high level pulse width is 150 μs to reset the storage unnecessary charges of photo sensors 11-1n and the applied voltage to the reset gate RSG is set to a high level at all times except for the integration time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
It is arranged in a two-dimensional array, and accumulates (integrates) the amount of electric charge corresponding to the brightness of light (also referred to as illuminance or luminance, hereinafter, referred to as the amount of light) at each location. Charge is CCD (Charge Cou)
A plurality of photoelectric conversion elements (hereinafter, referred to as an optical sensor or simply a sensor or a pixel) including photodiodes and the like, which are read by a shift register-like reading means such as a pleated device (abbreviation of a charge coupled device), and a signal of the optical sensor As a solid-state imaging device used for, for example, a facsimile, a video camera, and the like, including a light amount monitor arranged to receive an average amount of light received by a plurality of optical sensors in order to control an integration time of electric charges. In particular, the present invention relates to an image sensor having a function of discharging unnecessary unnecessary charges before a monitor operation of a light amount monitor as much as possible to enhance the linearity of a light amount detection characteristic. In the drawings, the same reference numerals indicate the same or corresponding parts.

[0002]

2. Description of the Related Art In an image sensor of this kind, automatic gain control (AutoGain Cont.
The control circuit optimizes the output level of the optical sensor (pixel) even when the luminance difference of the subject is significant.

FIG. 4 shows a configuration example of a conventional automatic gain control circuit (hereinafter referred to as an AGC circuit) in a one-dimensional image sensor (hereinafter referred to as a line sensor) 01 comprising, for example, 256 light sensors arranged in a line and a light amount monitor. Indicates that
FIG. 6 shows an operation sequence of the main part of FIG.

In FIG. 4, 1 (1 ₁ , 1 ₂ ...)
1 _n ) are arranged in a horizontal line, each of which is an optical sensor as a plurality of pixels that accumulates (integrates) and outputs a charge corresponding to the amount of received light, and 11 denotes an average light amount of light applied to the plurality of pixels 1. In the light amount monitor for receiving light, a photodiode PD as a light receiving unit (monitor light receiving unit) of the light amount monitor 11 is arranged along a row of the optical sensors 1 and serves as a light receiving unit (pixel light receiving unit) of a plurality of optical sensors 1. It is arranged so as to correspond to the photodiode PD.

[0005] 2 is each optical sensor 1₁~ 1_nTransfer gate T
G is output from the optical sensor 1₁~ 1 _nFormed by tying
Signal transferred through a shift register CCD
An output unit for detecting a load.
Similar to the niter 11 side, a floating diffuser described later
Version amplifier (hereinafter referred to as floating diffusion amplifier) FDA
A source follower SF is provided.

Reference numeral 51 denotes a monitor output which indicates the potential of the accumulated charge of the floating diffusion amplifier FDA of the light amount monitor 11 which has been taken out through the source follower SF of the light amount monitor 11 with a low output impedance and a level shift. Is a comparator for comparing the monitor output 51 passed through the capacitor C with the AGC level Vr, 16 is a NOR gate which outputs an ICG control signal 50 and an output of the comparator 15 and outputs a level determination signal 52, and 21 is a level determination signal 52 and the BG control signal 54 from the ICG control signal 50
Is a D-type flip-flop (abbreviated as D-FF).

As shown in FIG. 6, when detecting an image of a subject, the ICG control signal 50 is supplied for a predetermined period of time (150 μs in this example) from an unshown means based on an integration start command issued first. , applied at Hi (5V) level to the reset gate RSG of accumulation clear gate ICG and intensity monitor 11 described later of the optical sensor ₁ 1 to 1 _n.

The level determination signal 52 is generated as Hi (5 V) during an integration time (time during which the optical sensor 1 accumulates a charge corresponding to the amount of received light) determined by a monitoring operation of the light amount monitor 11 described later. .

Further, the BG control signal 54 is a D-FF2
1 is output from the inverted output terminal QB of each optical sensor 1 from the output point of the integration start command to the end point of the integration time.
_The voltage is applied as Hi (1 V) to the barrier gates BG of ₁ to 1 _n to be described later.

In the D-FF 21, a signal obtained by inverting the ICG control signal 50 by the inverter 20 at its reset terminal RB, 5V (Hi level) at its data input terminal D, and level determination at its rising edge clock terminal. Signals obtained by inverting the signal 52 by the inverter 20 are input.

The AGC circuit shown in FIG. 4 automatically and variably controls the charge integration time for the optical sensor 1 to detect the amount of received light in accordance with the average amount of light monitored via the light amount monitor 11. Before discussing the details of the circuit,
The configuration of the optical sensor 1 and the light amount monitor 11 and the principle of operation will be described.

FIG. 8 is an explanatory view of the optical sensor (pixel) 1. FIG. 8A shows the configuration of the optical sensor 1 for one pixel as a semiconductor, and FIG. The distribution of the potential φ (here, indicating the quantum mechanical energy level of electrons) around the charge accumulation gate STG is shown.

In FIG. 8A, an optical sensor 1 is provided with an overflow drain OFD, an overflow gate OFG, a photodiode PD as a pixel light receiving section, a barrier gate BG, an integral clear gate ICG, and an integral clear drain ICD in order from the top. Charge storage gate STG,
A transfer gate TG and four charge-coupled device gates (also referred to as CCD gates) C connected in series in the left-right direction
It consists of CDG1 to CCDG4.

The charge coupled device gate CCDG1
Has its upper end coupled to the transfer gate TG of the photosensor 1 and, if the photosensor 1 is not located at the end on the pixel array, the charge coupled device gate CCDG
Reference numeral 1 denotes a charge-coupled device gate CCDG4 of the optical sensor 1 (not shown) adjacent to the left, and the charge-coupled device gate CCDG4 of the drawing is serially connected to a charge-coupled device gate CCDG1 of the optical sensor 1 (not shown) adjacent to the right. Are combined.

In this manner, the charge-coupled device gates CCDG1-CCDG4 for each pixel of the optical sensor 1 are provided.
But minute all the pixels 1 ₁ to 1 _n of the line sensor 01 constitutes the aforementioned shift register like CCD for charge transfer are coupled successively in series.

In this example, the overflow drain O
7V to FD, 0.5V to overflow gate OFG, 3V to charge storage gate STG, integral clear drain ICD
7V is applied to each.

The BG control signal 54 changing to 1V and 0V is applied to the barrier gate BG, and the ICG control signal 50 changing to 5V and 0V is applied to the integral clear gate ICG, respectively.

Each time a signal charge is transferred, a signal (not shown) which alternates between 5V and 0V is applied to the transfer gate TG and the charge-coupled device gates CCDG1 to CCDG4.

Next, referring to FIG.
The operation principle of will be described. A photodiode PD serving as a pixel light receiving unit receives light reflected from a subject and performs photoelectric conversion. When the integration start command is issued, after the unnecessary charge in the optical sensor 1 is discharged for a certain period of time, the signal charge photoelectrically converted by the photodiode PD is changed to the light amount monitor 1.
By the operation 1, the charge is accumulated in the charge accumulation gate STG during the integration time specified by the AGC circuit.

The accumulated signal charges are transferred to the charge-coupled device gate CCDG1 via the transfer gate TG, and further transferred to the output unit 2 in FIG. 4 in order from the pixel at the end of the line sensor by the above-mentioned CCD. The transferred signal charges are converted into voltage signals by the floating diffusion amplifier FDA provided in the output unit 2 and output as pixel signals 5 via the source follower SF.

The above-described integration operation of the optical sensor 1 and the operation of discharging unnecessary charges before the integration operation are controlled as follows by opening and closing the barrier gate BG and the integration clear gate ICG.

First, based on the integration start command, the BG control signal 54 of Hi (1 V) is applied to the barrier gate BG, and the ICG control signal 5 of Hi (5 V) is applied to the integration clear gate ICG.
When 0 is applied, the potential φ below the barrier gate BG and the potential below the integration clear gate ICG decreases, and signal charges flow from the photodiode PD to the charge storage gate STG and from the charge storage gate STG to the integration clear drain ICD. start.

Thereafter, the potential φ of the photodiode PD matches the potential under the barrier gate BG,
All unnecessary charges in the charge storage gate STG are discharged, and the reset before the integration operation is completed.

Next, the BG control signal 54 remains Hi,
When the ICG control signal 50 becomes Lo (0 V), the flow of charges from the charge storage gate STG to the integration clear drain ICD stops, and signal charges are stored in the charge storage gate STG.

When the integration time determined by the operation of the light amount monitor 11 elapses and the BG control signal 54 becomes Lo (0 V), the flow of charges from the photodiode PD to the charge storage gate STG stops, and the integration operation ends. The signal charges thus accumulated in the charge accumulation gate STG are transferred to the output unit 2 via the transfer gate TG and the CCD as described above.

7A and 7B are explanatory diagrams of the light amount monitor 11, wherein FIG. 7A shows the configuration of the light amount monitor as a semiconductor, and FIG. 7B shows the distribution of the potential φ in the light amount monitor.
7A, the light amount monitor 11 includes an overflow drain OFD, an overflow gate OFG,
Photodiode PD as monitor light receiving unit, output gate OG, floating diffusion amplifier FDA, reset gate RS
G, a reset drain RSD.

In this example, the overflow drain OFD and the reset drain R which are both ends of the light amount monitor 1 are provided.
7 V is applied to each end of the SD, 0.5 V is applied to the overflow gate OFG, and 1 V is applied to the output gate OG.

In the conventional case, the reset gate RSG is used for resetting the light amount monitor 11 by the above-described ICG.
A control signal 50 (change between 5V and 0V) is applied. Note that the potential of the floating diffusion amplifier FDA is equal to the source follower S
It is taken out as a monitor output 51 via F.

Next, the operation principle of the light amount monitor 11 will be described with reference to FIG. When 5 V is applied to the reset gate RSG via the ICG control signal 50, the potential under the reset gate RSG decreases, and unnecessary charges composed of electrons accumulated in the floating diffusion amplifier FDA are drawn to the reset drain RSD.

The unnecessary charges mainly consist of electrons which have flowed from the photodiode PD through the output gate OG into the floating diffusion amplifier FDA up to this time, but also slightly generated in the floating diffusion amplifier FDA itself. Also includes electrons.

The potential φ of the floating diffusion amplifier FDA matches the potential below the reset gate RSG (the FDA reset level in FIG. 7B, 5 V in this example), and the potential φ of the photodiode PD falls below the output gate OG. The reset of the floating diffusion amplifier FDA is completed according to the potential.

Next, when the voltage applied to the reset gate RSG is set to 0 V via the ICG control signal 50, the potential φ under the reset gate RSG rises, and the floating diffusion amplifier F
The discharge of the charge from DA to the reset drain RSD stops, and the charge starts to accumulate in the floating diffusion amplifier FDA.

This charge (electrons) is supplied to a floating diffusion amplifier FDA
Of the floating diffusion amplifier FDA is reduced (the potential is lowered), so that a change in the potential (ΔV) from the reset level (5 V) of the floating diffusion amplifier FDA becomes a monitor output 51 as a voltage output signal via the source follower SF.

The function of the AGC circuit shown in FIG. 4 is to start the charge integration of the optical sensor (pixel) 1 (1 ₁ to 1 _n ), and then add a signal corresponding to the potential change ΔV in FIG. The magnitude relationship with the set AGC level Vr is compared, and the charge integration operation of the optical sensors ₁₁ to 1 _n is controlled so that the charge integration is stopped at the moment when the magnitude relationship changes.

FIG. 5 shows a temporal transition of the potential at the point A of the (-) input terminal of the comparator 15 in FIG. Next, the operation of FIG. 4 will be described with reference to FIGS. At time t0, the integration start instruction is issued, during the optical sensor 1 ₁ to 1 _n integration operation before starting 150μs of accumulation clear time Tc, the above-mentioned ICG control signal applied to the integration clear gate ICG photosensor 50 becomes Hi (5 V), and at the same time, the ICG control signal 50 is applied to the reset gate RSG of the light amount monitor 11.

The Hi ICG control signal 50 is shown in FIG.
The D-FF 21 is reset via the inverter 20 of FIG.
_The BG control signal 54 output to the ₁ to 1 _n barrier gates BG also becomes Hi (1 V). Therefore, the integration clear time Tc
Between, as described above, accumulated unnecessary charge of the optical sensor 1 ₁ to 1 _n and the light quantity monitor 11 is to be discharged.

During the integration clear time Tc, the Hi-ICG control signal 5 is applied to the (−) input terminal of the comparator 15.
3V is applied via a switch S1 closed by 0. On the other hand, during this period, the potential of the amplifier FDA becomes the reset level (5 V) due to the discharge of unnecessary charges in the floating diffusion amplifier FDA of the light amount monitor 11, so that the capacitance C has the level of the monitor output 51 corresponding to the FDA reset level. (3.5V in this example) and a voltage of 0 V which is the difference between 3V and 3V.
5V is charged.

When the ICG control signal 50 becomes Lo (0 V, reset release) at time t1 after discharging the electric charge during the integration clear time Tc, the switch S1 of the (-) human input terminal of the comparator 15 is turned off, and at the same time, the light amount monitor 11 is turned off. The resetting of the floating diffusion amplifier FDA is also terminated, and electric charge starts to be accumulated in the floating diffusion amplifier FDA of the light amount monitor 11, and the potential of the floating diffusion amplifier FDA, that is, the monitor output 51 starts to decrease.

At time t1, the ICG control signal 5
When 0 becomes Lo, the clock input of the D-FF 21 becomes NO.
Falls through the R gate 16 and the inverter 19, but since this does not affect the output of the D-FF 21, BG control signal 54 remains Hi, optical sensor ₁ 1 to 1 _n is the integral of the signal charges ( Storage).

Returning to the light amount monitor 11 side, as the monitor output 51 starts to decrease as described above, the potential at the point A of the (-) input terminal of the comparator 15 starts to gradually decrease from 3 V, and the potential at the point A decreases. Time t2 when the AGC level falls below the AGC level Vr (2.5 V or 2.0 V in this example) previously applied to the 15 (+) input terminals.
Then, the output of the comparator 15 is inverted from Lo level to Hi level.

Thus, the NOR gate 16 and the invert
Inputting Hi (5 V) data through the
Since the clock input of -FF21 rises, D-FF
21, and the BG control signal 54 is L
o, optical sensor 1₁~ 1 _nSignal charge integration stops
Is done.

The monitor operation time Ti from the reset release time t1 to the inversion time t2 of the comparator output is Ti.
In FIG. 4, the level determination signal 52 which is the output of the NOR gate 16 in FIG. 4 becomes Hi, and this time Ti is simultaneously the integration time of the optical sensors ₁₁ to 1 _n .

Therefore, in order for the AGC function to operate normally, the potential of the point A, that is, the change of the monitor output 51 is not linear with respect to the time and the light quantity of the light received by the light quantity monitor 11. No. In other words, monitor output 5
1 changes in proportion to time under light reception of the same light amount (fall)
In addition, it must change (fall) in proportion to the amount of received light per unit time.

[0044]

FIG. 9 shows a linear AGC function when the unnecessary light discharge of the light amount monitor 11 is performed only during the integration clear time Tc of 150 μs before the integration operation of the optical sensor (pixel) 1. This figure shows the temporal transition of the potential from the reset level of the monitor output 51 using the received light amount (illuminance) of the light amount monitor portion as a parameter.

In this figure, since the output of the source follower SF at the subsequent stage of the floating diffusion amplifier FDA of the light amount monitor 11 is directly measured to be the monitor output 51, the reset level is approximately 3.5 V. The potential at the input point A of the comparator 15 is 3 V as described above.

The above-mentioned integration time (level determination time) Ti is the time required for the potential at the input point A of the comparator 15 to drop from 3 V to the AGC level Vr (2.5 V or 2.0 V), and this is shown in FIG. In terms of the monitor output 51, this is the time required for the monitor output 51 to drop from 3.5V to 3.0V or 2.5V. Actually, after the integration time Ti, a next integration start command is normally issued after about 4 ms, including the transfer time of the signal charges of the pixels by the CCD.

As can be seen from this figure, the amount of light is small (to about 2 lux) and the descending curve of the monitor output 51 changes until the next integration start command is issued.
If the floating output does not reach the saturation region of the floating diffusion amplifier FDA, the change of the monitor output 51 is linear, but the amount of light (3 lux or more) increases and the monitor output 51 is output before the next integration start command is issued. The descending curve of 51 is the light amount monitor 1
When it reaches the saturation region of the floating diffusion amplifier FDA of 1, the change of the monitor output 51 becomes non-linear with respect to time and light amount level even within the integration time Ti at the beginning of the curve descent ( No longer proportional).

This indicates that when the floating diffusion amplifier FDA of the light amount monitor 11 is saturated, the unnecessary charge of the floating diffusion amplifier FDA is not completely discharged in the integration clear time Tc of 150 μs. .

As described above, conventionally, even if the integration operation of the optical sensor 1 is completed, the floating diffusion amplifier FDA of the light amount monitor 11 is not reset unless the next integration start command is issued. Since the charge is accumulated as described above and the sampling time for the image sensor to periodically take in the image information is limited, the charge discharging operation is performed only for 150 μs before the pixel integrating operation. The charge was not completely discharged from the diffusion amplifier FDA, the linearity of the potential change of the monitor output 51 was deteriorated, and the AGC function did not operate normally.

Therefore, the present invention solves this problem, and makes the change in monitor output linear with respect to time and the amount of received light without changing the sampling time so that the AGC function can operate normally. The task is to provide

[0051]

In order to solve the above problems BRIEF SUMMARY OF THE INVENTION The image sensor of claim 1 includes a plurality of light sensors comprising a pixel, respectively (1 ₁ to 1 _n), the plurality of light sensors receiving Each light sensor has a light amount monitor (11) for receiving an average amount of light to be emitted, and based on a command (integration start command) to detect the light amount, each optical sensor performs a first period (integration clear time Tc). Unnecessary charges accumulated in the sensor are discharged (by applying the BG control signal 54 of Hi to the barrier gate BG and the ICG control signal 50 of Hi to the integration clear gate ICG). Subsequently, in the second period (pixel integration time Ti) in which the end point of the period is instructed (by setting the BG control signal 54 to Lo) when the control signal 50 becomes Lo, the electric power newly generated in the sensor by the light reception. Accumulated, the accumulation amount of the charge is detected as a light quantity of light received (as a pixel signal 5) the sensor, likewise on the basis of the instruction, the light quantity monitor, the first
After the unnecessary charge accumulated in the monitor is discharged (by applying the ICG control signal 50 of Hi or the like to the reset gate RSG) during the period of (3), the light is continuously received (the applied signal of the reset gate RSG is set to Lo). This causes the monitor to newly accumulate the electric charge generated in the monitor. The time when the accumulated amount of the electric charge (the potential at the input A point of the comparator 15 changed by the monitor output 51 representing the monitor output) reaches a predetermined value (AGC level Vr) is the above-mentioned value. An image sensor (line sensor 01) detected as the end of the second period
And the like (instead of the ICG control signal 50 to the reset gate RSG), the amount of light that discharges unnecessary charges of the light amount monitor (by applying the Hi RSG control signal 53) during periods other than the first and second periods. A monitor charge discharging means is provided.

According to a second aspect of the present invention, in the image sensor according to the first aspect, the discharge of the unnecessary charges by the light amount monitor charge discharging means is started simultaneously with the end of the second period.

According to a third aspect of the present invention, in the image sensor according to any one of the first and second aspects, the light quantity monitor charge discharging means always discharges unnecessary charges of the light quantity monitor except during the second period. To do it.

According to a fourth aspect of the present invention, in the image sensor of the second or third aspect, the light quantity monitor charge discharging means outputs an output value at a start time and an end time of the second period. A flip-flop (D-FF18) to be updated is provided.

According to a fifth aspect of the present invention, in the image sensor according to the fourth aspect, the light quantity monitor charge discharging means delays the start time of a second period and transmits the delayed time to the flip-flop. Inverter 17)
Be prepared to have.

That is, according to the present invention, unnecessary charges of the floating diffusion amplifier FDA of the light amount monitor are discharged without changing the sampling time (the discharge is started at the same time as the end of the integration operation). It prevents charges from accumulating in the floating diffusion amplifier FDA and saturating, allowing discharge even with a short discharge time. This allows
The potential change of the monitor output is made linear with respect to time and the amount of received light so that the AGC function operates normally.

[0057]

FIG. 1 shows the configuration of an AGC circuit according to an embodiment of the present invention. The circuit of FIG.
A delay inverter 17 and a D-FF 18 are inserted between the OR gate 16 and the inverter 19, and a signal to be applied to the reset gate RSG of the light amount monitor 11 is changed to an inverted output terminal of the D-FF 18 instead of the conventional ICG control signal 50. A signal (referred to as an RSG control signal) 53 output from the QB is used.

The RSG control signal 53 is always applied to the reset gate RSG by 5 V except during the integration operation of the optical sensor 1, that is, while the monitoring operation of the light amount monitor 11 is not necessary.
(Hi level) is continuously applied to discharge unnecessary charges in the floating diffusion amplifier FDA of the light amount monitor 11.

The D-FF 18 has a reset terminal RB provided with a level determination signal 52 output from the NOR gate 16, a data input terminal D provided with 5V (Hi level), and a rising edge clock terminal provided with ICG control. Signal 50
Are inverted by the delay inverter 17 to receive the inverted ICG control signal 50B.

FIG. 2 shows an operation sequence of a main part in the AGC circuit of FIG. Next, the operation of FIG. 1 will be described with reference to FIG. After the integration start command is output at time t0, a fixed integration clear time (in this case, 150 μs) Tc
During the period, the output of the Hi ICG control signal 50 is the same as that in the related art.

During the period of the integration clear time Tc, the level determination signal 52 is Lo, the D-FF 18 is reset, the RSG control signal 53 output from the inverted output terminal QB is Hi, and the light amount monitor 11 Unnecessary charges in the floating diffusion amplifier FDA are discharged.

When the integration clear time Tc is over and the ICG control signal
When the signal 50 becomes Lo, the ICG control signal 50 rises.
The falling signal passes through the delay inverter 17 (that is, the inverted I
Trigger D-FF 18 by the CG control signal 50B)
And the output of the inverted output terminal QB of the D-FF 18 is RS
The G control signal 53 is set to Lo (0 V), and the optical sensor 1 (1
₁~ 1_n) Of the integration operation start time t1 and the light amount monitor 11
The monitor operation start time t1 'is made substantially coincident.

However, the end time t1 of the integration clear time Tc
When the ICG control signal 50 becomes Lo and the level determination signal 52 becomes Hi, the ICG control signal 50 falls before the reset of the D-FF 18 is completely released.
When the rising of the signal 50B obtained by inverting the signal comes to the D-FF 18, the RSG control signal 53 which is the QB output of the D-FF 18 does not become Lo, and the monitoring operation of the light amount monitor 11 does not start.

In order to ensure that the rising of the inverted ICG control signal 50B comes at the time t1 'after the reset of the D-FF 18 is released, the delay inverter 17 is actually set to five.
They are arranged in stages in series. However, the delay inverter 17
Is very short, several ns, and the effect on the actual integration time (10 μs to 20 ms) can be neglected.

When the light amount monitor 11 stops operating and the level determination signal 52 becomes Lo, the level determination signal 52
Is used as a reset signal to reset the D-FF 18 and RS
The G control signal 53 is set to Hi, and the floating diffusion amplifier FD is again
The unnecessary charge of A is discharged. Since the ICG control signal 50 does not become Hi (and therefore does not fall) unless an integration start command is issued, the charge discharge is not interrupted.

Although the pulse width (integral clear time) Tc of the ICG control signal 50 is set to 150 μs in this embodiment, this time Tc becomes the unnecessary charge discharging time of the optical sensor (pixel) 1 and the light amount monitor 11 simultaneously. This is the shortest time for discharging unnecessary charges (for example, when a command for starting integration is input again at the same time as the end of the first integration as a special process, the discharging time for unnecessary charges becomes the pulse width of the ICG control signal 50).

The solid line curve in FIG. 3 is a characteristic diagram showing the linearity of the AGC function when the unnecessary charge discharging time of the floating diffusion amplifier FDA of the light amount monitor 11 is lengthened. This diagram shows the ICG control signal for convenience of measurement. An example is shown in which 50 is Hi and the integral clear time Tc is 4 ms.

In FIG. 3, similarly to FIG. 9, the reset level of the monitor output 51 is set to 3.5 V, and the time transition of the potential from this reset level is represented by the parameter of the received light amount (illuminance) of the light amount monitor portion. As shown.

From the solid curve shown in FIG. 3, even if the light amount increases (to 3 lux or more) and the floating diffusion amplifier FDA of the light amount monitor is saturated before the integration start command is issued, the integration clear is performed. If the time Tc is lengthened to about 4 ms normally existing from the end of the pixel integration time Ti to the issuance of the next integration start command, the change of the monitor output 51 becomes linear within the pixel integration time Ti. I understand.

The dashed line curve in FIG. 3 indicates that the Hi RSG control signal 53 is immediately monitored at the end of the pixel integration time Ti (at this time, the potential of the monitor output 51 is set to 2.5 V). 11 shows the temporal transition of the monitor output 51 when the signal is given to the monitor output 11. However, this one-dot chain line curve is added to the solid line curve based on a separate measurement result.

Thus, the floating diffusion amplifier FD of the light amount monitor
If the discharge of the unnecessary charges of the light amount monitor 11 is started in a state where A is not saturated, the floating diffusion amplifier FD in FIG.
As can be seen from the good linearity of the curve when A is unsaturated, even if the unnecessary charge discharging time of the floating diffusion amplifier FDA of the light amount monitor becomes only 150 μs, the temporal change of the monitor output 51 is obtained. Linearity can be maintained.

As described above, according to the present invention, the time for discharging the unnecessary charge of the light quantity monitor is usually set to be sufficient so that even if the floating diffusion amplifier FDA of the light quantity monitor is saturated before the unnecessary charge is discharged for some reason. By not saturating the floating diffusion amplifier FDA of the light amount monitor at all times, even if the floating diffusion amplifier FD of the light amount monitor
Even if the unnecessary charge discharging time of A becomes 150 μs,
In any case, unnecessary charges of the floating diffusion amplifier FDA of the light amount monitor can be completely discharged, and linearity of the change of the monitor output 51 with respect to time and light amount can be realized.

[0073]

According to the present invention, the floating diffusion amplifier FDA of the light amount monitor is always used except for the integration operation of the optical sensor (pixel).
Unnecessary charge is discharged, so that a sufficient time for discharging unnecessary charges is normally obtained. Even if the floating diffusion amplifier FDA is saturated before the unnecessary charges are discharged, the change in the monitor output does not affect the time. Good linearity is obtained with respect to the amount of light.

Since the unnecessary charge is discharged simultaneously with the stop of the integration operation, the floating diffusion amplifier FD of the light amount monitor is normally used.
A does not saturate, and even if the unnecessary charge discharging time can be as short as the integration clear time of 150 μs, unnecessary charges can be sufficiently discharged. In this way, the linearity of the monitor output with respect to time and light quantity is improved, and the AGC function can be perfectly and normally operated.

[Brief description of the drawings]

FIG. 1 shows an image sensor A according to an embodiment of the present invention.
Configuration diagram of GC circuit

FIG. 2 is a diagram showing an operation sequence of a main part of FIG. 1;

FIG. 3 is a characteristic diagram showing a time dependency of a monitor output for showing an effect of the present invention.

FIG. 4 is a configuration diagram of a conventional AGC circuit corresponding to FIG.

FIG. 5 is a diagram showing a relationship between a temporal transition of a monitor output and an integration time.

FIG. 6 is a diagram showing an operation sequence of a main part of FIG. 4;

FIG. 7 is a principle diagram of a light amount monitor.

FIG. 8 is a principle diagram of an optical sensor (pixel).

FIG. 9 is a characteristic diagram showing a time dependency of a conventional monitor output.

[Explanation of symbols]

01 Line sensor 1 (1 ₁ to 1 _n ) Optical sensor (pixel) 2 Output unit 5 Pixel signal 11 Light intensity monitor 15 Comparator 16 NOR gate 17 Delay inverter 18 D-type flip-flop (D-FF) 19, 20 Inverter 21 D Type flip-flop (D-FF) 50 ICG control signal 50B inverted ICG control signal 51 monitor output 52 level judgment signal 53 RSG control signal 54 BG control signal BG barrier gate C capacitor FDA floating diffusion amplifier (floating diffusion amplifier) ICG integration clear gate PD photodiode RSG reset gate S1 switch SF source follower TG transfer gate Vr AGC level

Continued on the front page F term (reference) 4M118 AA10 AB01 AB10 BA10 CA03 CA17 DB01 DD04 DD09 DD10 DD12 FA06 FA08 FA14 FA39 5C024 AA01 CA17 DA04 FA02 GA01 GA23 GA26 GA27 GA43 5C051 AA01 BA03 DA03 DB01 DB12 DB13 DB15 DE02 EA02 5C072A01 BA01 FB19 FB27

Claims (5)

[Claims] A plurality of light sensors each serving as a pixel; and a light amount monitor for receiving an average amount of light received by the plurality of light sensors. After the unnecessary charge accumulated in the sensor is discharged during the first period, each optical sensor successively generates a charge newly generated in the sensor by receiving light during the second period in which the end point of the period is indicated. The amount of accumulated charge is detected as the amount of light received by the sensor. Similarly, based on the command, the light amount monitor continuously discharges unnecessary charges accumulated in the monitor during the first period. An image sensor that accumulates charges newly generated in the monitor due to light reception and detects a point in time when the accumulated amount of the charges reaches a predetermined value as an end point of the second period. 1, the image sensor comprising the light amount monitoring charge discharging means for discharging unnecessary charges of the light amount monitor in addition to the second period. 2. The image sensor according to claim 1, wherein the discharge of the unnecessary charges by the light quantity monitor charge discharging means is started simultaneously with the end of the second period. 3. The image sensor according to claim 1, wherein said light quantity monitor charge discharging means comprises:
An image sensor which always discharges unnecessary charges of a light amount monitor except during the second period. 4. The image sensor according to claim 2, wherein said light quantity monitor charge discharging means comprises:
An image sensor, comprising: a flip-flop that updates an output value at a start time and an end time of the second period. 5. The image sensor according to claim 4, wherein said light quantity monitor charge discharging means includes means for delaying a start time of a second period and transmitting the delayed time to said flip-flop. Image sensor.