JP2000224592A - Decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable reducing a memory capacity even in the case of decoding a frame which is subjected to bi-directional predictive coding. SOLUTION: A frame kind detecting circuit 11 detects the frame kind of encoding data and a VBV buffer 12 holds encoding data at every frame kind based on the detection result. The VBV buffer outputs not only encoding data of the B frame but also encoding data of the I and P frames to be its reference picture during the decoding period of the B frame. At first, encoding data of the I and P frames to be an rear part reference picture are decoded and held in a movement correcting memory 19 and, then, encoding data of the B frame is decoded through the use of the front part and rear part reference pictures held by a frame memory 18 and the movement correcting memory 19. It is enough that the memory 19 holds only the restored picture of a movement compensating range so that the memory capacity is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding device suitable for decoding coded data including a bidirectionally predicted coded frame.

[0002]

2. Description of the Related Art In recent years, digital signal processing technology for video and audio has been remarkably advanced, and with the progress of digital broadcasting and integration of broadcasting and communication, systems have been actively developed around the world. It has become One of the most important digital signal processing techniques is a video and audio compression technique.

[0003] The compression technology is based on ISO / IEC13818-
1 (MPEG: Moving Picture Coding Experts Group
) (ISO / IEC JTC1 / SC29 / WG1)
The method proposed in 1) has been established as a global standard method in the fields of broadcasting, communication and storage media.

[0004] The method specified by ISO / IEC13818-1 is a technique for encoding a video signal by using a combination of DCT transform, inter-frame prediction encoding, run-length encoding, and entropy encoding.

FIG. 7 is a block diagram showing a general model encoder of ISO / IEC13818-1.

An input terminal 1 receives an MPGE elementary stream. The VBV buffer 2 holds the input elementary stream, and outputs data to the VLD decoder 3 under the control of a timing control circuit (not shown). The VLD decoder 3 decodes the input variable length data according to a table and converts the data into fixed length data.

[0007] The variable-length decoded data is inversely quantized by an inverse quantization circuit 4, and is inversely quantized by an inverse DCT circuit 5.
The signal is subjected to CT processing and supplied to the addition circuit 6. If the input elementary stream is a frame (I frame) that has been intra-coded, the output of the inverse DCT circuit 5 is a restored image. This restored image is supplied to the frame memory 8 as a reference image of the P and B frames that have been predictively encoded.

[0008] The frame memory 8 holds the restored reference image and outputs it to the motion correction circuit 9. Motion compensation circuit 9
Outputs a motion-corrected reference image to the switch 10.
The switch 10 sets the restored image of the P and B frames to the inverse DCT.
Motion correction circuit 9 when supplied from circuit 5 to adder 6
Is output to the adder 6.
The adder 6 restores the original image by adding the motion-compensated reference image to the restored images of the P and B frames.

The restored image of the P frame from the adder 6 is B
The frame image is supplied to the frame memory 8 as a reference image of the frame image. The restored image of the B frame from the adder 6 is output as it is via the switch 7. On the other hand, the restored images of the I and P frames stored in the frame memory 8 are also output via the switch 7.

The output order of the I, P and B frames is determined according to the display. FIG. 8 is an explanatory diagram for explaining the signal flow of I, P, and B frames. FIG. 8A shows the transmission format of the input elementary stream, FIG. 8B shows the decoding timing, and FIG.
8C shows the contents of the frame memory 8, and FIG. 8D shows the display timing. In FIG. 8, the subscripts indicate the original frame numbers in the display order, and I, P, and B indicate that they are I frames, P frames, or B frames, respectively.

At the time of encoding, since motion compensation prediction encoding is adopted, each frame is encoded and transmitted in an order different from the actual frame order. Now, a series of frames 0,
.. Shall be encoded. FIG. 8A shows, for example, a B frame (B0, B1 frame) in which frames 0 and 1 are encoded using frames (-1) and 2 as reference images.
, Frame 2 is an intra-coded I frame (I 2 frame), and frames 3 and 4 are B frames (B 2,
B5 frame), and frame 5 is a P frame (P5 frame) encoded using frame 2 as a reference image. In this case, since the reference image needs to be decoded first, transmission is performed in the order shown in FIG.

The input encoded frames are sequentially decoded in the order shown in FIG. As described above, the restored images of the I and P frames are stored as reference images in the frame memory 8 of FIG. For example, as shown in FIG. 8C, the restored image of the I2 frame is
Since the frames 0, B1, P5, B3, and B4 are used as reference images, they are held in the frame memory 8 until these frames are restored. Similarly, since the restored image of the P5 frame is used as a reference image of the B3 and B4 frames to be decoded later, it is held in the frame memory 8 until these frames are restored.

Since the restored image of the B frame is not used as a reference image, it is output as it is after decoding, as shown in FIG. As a result, as shown in FIG. 8D, the I and P frames are output with a delay of three frames from the decoding, and the B frames are output immediately after the decoding. Therefore, the apparatus of FIG. 7 needs to be able to hold two frames of restored images at the same time as a reference image.

As described above, when decoding coded data that has been bidirectionally predicted coded, two frames of memory are required to hold the restored images of I and P frames as reference images. Extremely large capacity.

[0015]

As described above, conventionally, when coded data that has been bidirectionally predicted coded is decoded, there is a problem that the required memory capacity is extremely large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a decoding apparatus capable of reducing a required memory capacity even when decoding coded data which has been bidirectionally coded. With the goal.

[0017]

A decoding apparatus according to the present invention receives coded data including a frame which has been bidirectionally coded by using motion compensated prediction coding, and receives the coded data of the input coded data. Frame type detecting means for detecting a frame type; and, based on a detection result of the frame type detecting means, holding and outputting the input coded data up to a decoding period of each frame for each of the frame types. During the decoding period of the coded data of the bidirectionally predicted coded frame of the coded data, the coded data of the intra-coded frame or the coded data of the unidirectionally predicted coded frame is backward or forward. Buffer means for outputting for a forward reference image,
Decoding means for decoding the encoded data output from the buffer means to obtain a restored image, and decoding the decoded image from the decoding means for a forward or backward reference image for decoding processing of the predictively encoded frame. A first storage unit for storing, and for decoding a predictively encoded frame, a decoded image decoded for a backward or forward reference image during a decoding period of encoded data of a bidirectionally predicted encoded frame. And a second storage means for holding the data.

In the present invention, the input coded data is supplied to and held in the buffer means after the frame type is detected by the frame type detection means. The coded data of the intra-coded frame and the coded data of the unidirectionally predicted coded frame are read from the buffer means and supplied to the decoding means for decoding. The restored images of these intra-frame encoded frames and unidirectional predictive encoded frames are held in the first storage unit as forward or backward reference images. During the decoding period of the coded data of the bidirectionally coded frame, in order to obtain the backward or forward reference image, the buffer means firstly sets the coded data of the intra-coded frame or the unidirectionally predicted coded data. The encoded data of the decoded frame is provided to the decoding means. The restored image obtained by the decoding means is given to and held in the second storage means. The encoded data of the frame subjected to bidirectional prediction encoding is supplied to a decoding unit, and is decoded using the reference image held in the first and second storage units.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of a decoding device according to the present invention.
In FIG. 1, the same components as those in FIG. 7 are denoted by the same reference numerals.

The input terminal 1 receives, for example, coded data that has been subjected to variable length coding according to the coding method of the MPEG standard. The encoded data includes an I frame that has been intra-coded and P and B frames that have been predictively encoded. The encoded data is supplied to the frame type detection circuit 11.
The frame type detection circuit 11 detects whether the input coded data is I, P, or B,
Output to the VBV buffer 12. VBV buffer 12
Outputs the held encoded data of each frame to the VLD decoder 13 in synchronization with the decoding timing.

In the VBV buffer 2 according to the prior art shown in FIG. 7, the order of the input encoded frames matches the order of the encoded frames to be decoded. On the other hand, in the present embodiment, the order of the input encoded frames and the order of the encoded frames decoded by the VLD decoder 13 are different.

That is, based on the detection result of the frame type detection circuit 11, the VBV buffer 2 converts the encoded frame of the frame type corresponding to the decoding order into the VLD decoder 1
Output to 3. In the present embodiment, during the decoding period of a B frame, I and P frames serving as reference images thereof are decoded in addition to the B frame to be decoded.

In the conventional VBV buffer 2, encoded frames are output in the order of input frames, and the encoded frames stored after decoding are completed are unnecessary. That is, the occupancy of the VBV buffer 2 is controlled by the encoder, and does not overflow or underflow. On the other hand, in the present embodiment, a decoding process is performed a plurality of times for an encoded frame serving as a reference image. Therefore, V
The capacity of the BV buffer 12 must be larger than that of the conventional VBV buffer.

Further, since the input frame order is different from the frame order output for decoding, the VBV buffer 12 records the head address of each frame signal and the head address of data of each macroblock. It has become.

The VLD decoder 13 includes a VBV buffer 1
2 is decoded and output to the inverse quantization circuit 14. The inverse quantization circuit 14 performs an inverse quantization process on the output of the VLD decoder 13 and outputs the result to the inverse DCT circuit 15. The inverse DCT circuit 15 performs an inverse DCT process on the inversely quantized output from the inverse quantization circuit 14 and outputs the result to the adder 16.

The adder 16 is provided with motion compensation circuits 20, 21 or "0" from a MIX circuit 22, which will be described later.
For the decoded data of the P and B frames, the output of the MIX circuit 22, that is, the reference image is added to the output of the inverse DCT circuit 15 to restore the original image. The adder 16 outputs the restored image of the I and P frames to the frame memory 18 or the motion correction memory 19 as a reference image. Also,
The adder 16 outputs the restored image of the B frame and the restored image of the I or P frame to the switch 7 for display as they are.

The frame memory 18 holds the input restored image of the I and P frames as a reference image and outputs it to the motion compensation circuit 20, and outputs the restored image of the P or I frame to the switch 7 for display. I do. The motion compensation circuit 20 performs motion compensation on the input reference image and performs MIX.
Output to the circuit 22.

The motion compensation memory 19 holds the restored image of the motion compensation range including at least the macroblock being decoded, and outputs the restored image to the motion compensation circuit 21. For example,
The memory 19 for motion compensation is set to a capacity capable of storing pixel data of the number of vertical pixels × the number of horizontal pixels in the motion compensation range.

The motion compensation circuit 21 performs motion compensation on the input reference image and outputs the result to the MIX circuit 22. The MIX circuit 22 selects “0” at the time of decoding an I frame and supplies it to the adder 16, and at the time of predictive coding, the motion compensating circuit 20,
The outputs of 21 are mixed and given to the adder 16.

In this embodiment, for example, the frame memory 18 is used for a forward reference image, and the motion correction memory 19 is used for a backward reference image.

Next, the operation of the embodiment configured as described above will be described with reference to FIGS. 2A and 2B are explanatory diagrams for explaining a decoding operation in the present embodiment. FIG. 2A shows a transmission format of input encoded data, and FIG. 2B shows a decoding timing. 2 (c) shows the contents of the frame memory 18, and FIG. 2 (d) shows the display timing. In FIG. 2, the subscripts indicate the original frame numbers in the display order,
I, P, and B indicate an I frame, a P frame, or a B frame, respectively. FIG. 3 is an explanatory diagram showing a storage range of the motion correction memory 19 and a motion correction range. FIG. 4 shows B
FIG. 5 is an explanatory diagram showing macroblocks required for decoding a frame, and FIG. 5 is an explanatory diagram for explaining movement of a motion correction range.

The input terminal 1 receives, for example, encoded data in the transmission format shown in FIG. The encoded data input via the input terminal 1 is input to the frame type detection circuit 1
1 and the frame type is detected. The VBV buffer 12 stores the input encoded data for each frame based on the detection result of the frame type. In this case, the VBV buffer 12 records the start address of each frame signal and the start address of data of each macro block.

Now, the encoded data of frame 2, I
It is assumed that the decoding timing of two frames (FIG. 2B) is reached. The encoded data of the I2 frame is read from the VBV buffer 12 and supplied to the VLD decoder 13. The VLD decoder 13 performs variable length decoding on the input coded frame and supplies the decoded frame to the inverse quantization circuit 14, and the inverse quantization circuit 14 performs an inverse quantization process on the input data to perform an inverse DCT.
It is given to the circuit 15. The inverse DCT circuit 15 performs an inverse DCT process on the inversely quantized output to restore the original image. This restored image is supplied to the frame memory 18 via the adder 16 as a reference image. As shown in FIGS. 2C and 2D, the restored image of the I2 frame is stored in the frame memory 1.
8 and output via switch 7 for display at the same time.

On the other hand, during the decoding period of the I2 frame, the VBV buffer 12 stores the P5 frame. VBV during the period following the decoding period of the I2 frame
The encoded data of the B3 frame held in the buffer 12 is decoded. In the present embodiment,
During the decoding period of the B3 frame, macroblocks in the motion compensation range of the B3 frame in the restored image of the P5 frame serving as a reference image are decoded prior to the decoding of the B3 frame.

FIG. 3 is for explaining the motion compensation range. In the MPEG encoder, DCT processing is performed in a predetermined block unit, for example, a block unit of 8 pixels × 8 pixels. The size of the luminance block differs from that of the color difference block due to the difference between the sampling clocks of the luminance signal and the color difference signal. In this case, macroblocks of the same size composed of different numbers of luminance blocks and chrominance blocks are used as units for encoding. Motion compensation is also performed on a macroblock basis.

In the motion detection, a predetermined motion compensation range is set around a block of a reference frame having the same relative positional relationship with a target block (macroblock) to be coded in the current frame. I do. And
By the matching calculation, a block having a pattern most similar to the pattern of the target block in the current frame is searched within the motion compensation range. In other words, matching is performed by sequentially setting blocks while moving them in 0.5-pixel units within the motion compensation range, and accumulating the absolute value of the difference between each corresponding pixel between the target block and the block set in the motion compensation range. Calculation is performed, and the block having the smallest cumulative value is set as a reference image block. The positional relationship between the reference image block and the block of interest is transmitted as a motion vector.

FIG. 3 shows the motion compensation range for the A macroblock by hatching. Assuming that the macroblock to be decoded is the A macroblock shown in FIG.
The decoding of the A macroblock requires a reference image in the motion compensation range indicated by oblique lines. Here, assuming that the motion correction memory 19 that holds the backward reference image holds the restored image of the area of the vertical pixels of the motion compensation range × the horizontal pixels of the screen, the figure of the motion compensation range of the A macro block The region excluding the C macroblock shown in FIG. 4 is already held in the motion compensation memory 19 when the macroblock immediately before the A macroblock is decoded. Therefore, in this case, when decoding each macroblock of the B3 frame, the macroblock of the P5 frame corresponding to the C macroblock may be decoded first.

That is, during the decoding period of the B3 frame,
First, a macroblock corresponding to the C macroblock in FIG. 4 of the P5 frame is read from the VBV buffer 12 and supplied to the VLD decoder 13. This macro block is composed of a VLD decoder 13, an inverse quantization circuit 14, and an inverse DCT.
The signal is supplied to the adder 16 via the circuit 15.

The processing in units of macro blocks is performed in VB
This is performed based on the head address recorded in the V buffer 12. The VBV buffer 12 has a DTS (decoding tim)
e stamp) is used to determine the timing of outputting the encoded data to the VLD decoder 13.

The reference image necessary for decoding the P5 frame is a restored image of the I2 frame already stored in the frame memory 18 (see FIG. 2C). After that, MI
The signal is supplied to the adder 16 via the X circuit 22. Adder 1
6 adds the output of the MIX circuit 22 to the output of the inverse DCT circuit 15 to obtain a restored image of the P5 frame. This restored image is supplied to the motion correction memory 19. Thus, the restored image of the motion compensation range of the P5 frame for decoding the macroblock of the B3 frame is stored in the motion compensation memory 19.

Next, when the macroblock of the B3 frame is V
The data is read from the BV buffer 12 and supplied to the VLD decoder 13. This macro block is a VLD decoder 1
3. The signal is supplied to the adder 16 via the inverse quantization circuit 14 and the inverse DCT circuit 15. Assuming that the macroblock to be decoded is the macroblock A in FIG. 3, the motion compensation circuits 20 and 21 convert the restored images in the motion compensation ranges shown by the hatched lines in FIG. To perform motion compensation based on the motion vector.

The MIX circuit 22 mixes the outputs of the motion compensation circuits 20 and 21 according to the prediction direction and supplies the mixed output to the adder 16. The adder 16 adds the two inputs, and the adder 16 outputs A
A macroblock restored image is output. This restored image is output via the switch 7 for display.

The same decoding is performed for the next B4 frame. At the time of decoding the next P5 frame, decoding is performed using the restored image of the I2 frame stored in the frame memory 18. As shown in FIG. 2D, the restored image of the P5 frame is
B, which is output through
6 and B7 are stored in the frame memory 18 as forward prediction reference images (FIG. 2C). Thereafter, the same operation is repeated to perform decoding.

When the macroblock line is switched at the time of decoding the B frame, the motion compensation memory 19
Also changes in the macro block line stored in. FIG. 5 shows an example in this case. When decoding the A1 macroblock in FIG. 5, the motion compensation range H1 indicated by oblique lines is used.
When decoding the A2 macroblock, a restored image in the motion compensation range H2 indicated by oblique lines is required. That is, when decoding the A2 macroblock, the restored image of the area A stored in the motion compensation memory 19 becomes unnecessary, and the restored image of the C area is required. Therefore, also in this case, the motion compensation memory 1
9 only needs to have a capacity to store the restored images of the areas A and B.

When the macroblock to be decoded in the B frame is the first macroblock to be decoded in the frame, the restored image of the motion correction range is not stored in the motion correction memory 19, so that the B frame is decoded. The number of macroblocks for backward prediction reference pictures to be decoded before decoding increases.

The VBV buffer 12 stores I, P
As shown in FIG. 2B, the encoded data of the frame is read out and output three times.
Therefore, the VBV buffer 12 needs to hold these encoded data for three frame periods longer than the conventional example.

The capacity required for the VBV buffer 12 is as follows:
MPEG (ISO / IEC13818-2) MP @ HL
9.7812 as the original VBV buffer
Assuming that the sampling rate is 48 Mbits and the sampling frequency ratio of Y: Cr: Cb is 4: 2: 0, 1920 (pixels) × 256 (lines) ×
8 (bits) × 1.5 (Y / C) = 5.9 M bits, which requires a total of about 15.7 M bits.

On the other hand, the capacity of the frame memory defined by the MPEG is 1920 (pixels) × 1152 (lines) × 8 (bits) × 1.5 (Y / C) = 26.5 Mbits. Therefore, in the present embodiment, it is possible to reduce 10.8 Mbits by combining the frame memory and the VBV buffer.

As described above, in the present embodiment, V
By controlling the reading of the encoded data from the BV buffer, only the necessary part of the backward prediction reference image in the motion correction range is decoded and held in the memory during the decoding period of the B frame. No memory is needed to hold the entire predicted reference image. What is necessary is just to hold the encoded data before decoding in the VBV buffer,
The overall memory capacity can be significantly reduced.

In the above-described embodiment, the description has been given of the case where video is output in units of frames on the assumption that signal processing is performed in units of frames. it is obvious.
In this case, after decoding the B frame, a second frame memory for the B frame having half the capacity of the frame memory is required. This is the same in the conventional example.

By the way, in the above embodiment, the motion compensation memory 19 stores the vertical pixels of the motion compensation range.
The description has been given assuming that the restored image of the horizontal pixel area of the screen is held. As described above, by using a memory having a sufficient capacity as the motion correction memory 19, it is possible to narrow the range of the macroblock to be decoded for the backward reference image during the decoding period of the B frame as shown in FIG. Thus, the decoding speed for obtaining the backward reference image can be made relatively low.

Conversely, if the decoding speed for obtaining the backward reference image is high, the capacity of the motion compensation memory 19 can be reduced. That is, at the time of decoding the macroblock of the B frame, if all the macroblocks in the motion compensation range of the I and P frames can be decoded, the backward reference image of the motion compensation range is used as the motion compensation memory 19. What is necessary is just to have the capacity to hold.

Further, as the memory 19 for motion compensation, a memory for holding a restored image of a region of horizontal pixels in the motion compensation range × vertical pixels of the screen may be employed.

FIG. 6 is a block diagram showing another embodiment of the present invention. In FIG. 1, the same components are denoted by the same reference numerals, and description thereof will be omitted. In the present embodiment, a decoding circuit system for obtaining a reference image is additionally provided, so that a circuit having a decoding speed similar to that of the conventional example is used.

In FIG. 6, a VLD decoder 3, an inverse quantization circuit 4, an inverse DCT circuit 5, and an adder 6 have the same configurations as those of the conventional example of FIG. 7, respectively, and the VLD decoder 13 and the inverse quantization circuit 14 of FIG. , And operates at half the operating frequency of the inverse DCT circuit 15 and the adder 16. The VLD decoder 3 ', the inverse quantization circuit 4', the inverse DCT circuit 5 'and the adder 6' shown in FIG.
It has the same configuration as the CT circuit 5 and the adder 6.

In the present embodiment, the VBV buffer 12 supplies the stored encoded data to the VLD decoder 3 and encodes the I and P frames in order to create a reference image during the decoding period of the B frame. VL data
It is given to the D decoder 3 '. The VLD decoder 3 performs variable-length decoding on the input encoded data to perform inverse quantization
4 ′, and the inverse quantization circuits 4 and 4 ′ dequantize the input coded data and supply the resulting data to the inverse DCT circuits 5 and 5 ′. The inverse DCT circuits 5 and 5 ′ perform inverse DCT processing on the input inversely quantized outputs and provide the resultant to the adders 6 and 6 ′.

The adder 6 supplies the output of the inverse DCT circuit 6 with the MI
The output of the X circuit 22 is added to obtain the original restored image, which is output to the switch 7 and the frame memory 18. The adder 6 'is supplied with a reference image from the frame memory 18 via the switch 25. The switch 25 is turned on during the decoding period of the B frame. The adder 6 'adds the output of the frame memory 18 to the output of the inverse DCT circuit 5' to obtain a restored image in the motion compensation range, and outputs the restored image to the motion compensation memory 19 as a reference image.

In the embodiment configured as described above, the same operation as in the embodiment of FIG. 1 is performed. In the embodiment of FIG. 1, during the decoding period of a B frame, V
LD decoder 13, inverse quantization circuit 14, inverse DCT circuit 1
5 and the adder 16 were used in a time-division manner. First, the backward reference image was decoded, and then the encoded data of the B frame was decoded. On the other hand, in the present embodiment, decoding of a B frame and decoding of a reference image necessary for decoding the B frame are performed in parallel.

In this embodiment, the decoding process is performed at the timing shown in FIG. 2, for example. That is, in the embodiment of FIG. 1, the decoding shown in FIG. 2B is performed in a time division manner, but in the present embodiment, the decoding processing of the B frame in the decoding processing shown in FIG. Decoder 3, inverse quantization circuit 4, inverse DCT circuit 5, and adder 6
The decoding of the I and P frames is performed by the VLD decoder 3 ', the inverse quantization circuit 4', the inverse DCT circuit 5 'and the adder 6'.

Accordingly, the decoding processing in the present embodiment is performed by the VLD decoders 3 and 3 ', the inverse quantization circuit 4,
4 ', the inverse DCT circuits 5, 5' and the adders 6, 6 '
The operation may be performed at half the operation speed of the VLD decoder 13, the inverse quantization circuit 14, the inverse DCT circuit 15, and the adder 16.

Other operations are the same as those of the embodiment shown in FIG.

As described above, also in this embodiment, FIG.
The same effect as that of the embodiment can be obtained. This embodiment has an effect that the memory capacity can be reduced without increasing the operation speed of the circuit.

It is apparent that the present embodiment is also applicable to a device that outputs video in units of fields.

[0064]

As described above, according to the present invention, there is an effect that the required memory capacity can be reduced even when decoding the coded data which has been bidirectionally coded.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a decoding device according to the present invention.

FIG. 2 is an explanatory diagram for explaining operation of the embodiment;

FIG. 3 is an explanatory diagram for explaining operation of the embodiment;

FIG. 4 is an explanatory diagram for explaining operation of the embodiment;

FIG. 5 is an explanatory diagram for explaining operation of the embodiment;

FIG. 6 is a block diagram showing another embodiment of the present invention.

FIG. 7 is a block diagram showing a conventional decoding device.

FIG. 8 is an explanatory diagram for explaining the operation of the conventional example.

[Explanation of symbols]

11 ... frame type detection circuit, 12 ... VBV buffer,
13 VLD decoder, 14 inverse quantization circuit, 15 inverse DCT circuit, 16 adder, 18 frame memory, 1
9: memory for motion compensation, 20, 21: motion compensation circuit, 2
2. MIX circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C059 KK08 LA09 MC11 ME01 NN03 NN11 NN28 PP05 PP06 PP07 PP14 PP16 TA03 TA12 TA45 TA63 TC12 TC39 TD17 UA05 UA34 5J064 AA04 BA08 BB03 BC01 BC08 BD02 BD03

Claims (6)

[Claims] 1. Frame type detection means for receiving coded data including a frame which has been bidirectionally predicted coded by employing motion compensated prediction coding, and detecting a frame type of the input coded data, Based on the detection result of the frame type detection means, the input coded data is held and output until the decoding period of each frame for each frame type, and the bidirectional predictive coding of the held coded data is performed. During the decoding period of the coded data of the frame, buffer means for outputting the coded data of the intra-frame coded frame or the coded data of the unidirectionally predicted coded frame as a backward or forward reference image, Decoding means for decoding the coded data output from the buffer means to obtain a restored image; First decoding means for holding a restored image from the decoding means for use as a forward or backward reference image for decoding a frame, and bidirectional predictive coding for decoding a predictively coded frame. A second storage unit for holding a restored image decoded for a backward or forward reference image during a decoding period of encoded data of a frame. 2. The decoding device according to claim 1, wherein the second storage unit holds a restored image in a region of a motion compensation range of the motion compensation prediction coding. 3. The image processing apparatus according to claim 1, wherein the second storage unit stores a restored image of a whole area in a horizontal direction in a motion compensation range of the motion compensated prediction coding in a vertical direction.
3. The decoding device according to item 1. 4. The apparatus according to claim 1, wherein said decoding means decodes only the area held by said second storage means for the encoded data output from said buffer means for a backward or forward reference image. Item 4. The decoding device according to item 2 or 3. 5. The buffer means holds a start address for each frame type, holds a start address for each coding unit, and determines the order of encoded data to be output based on the held start address. The decoding device according to claim 1, wherein: 6. Frame type detection means for receiving coded data including a frame which has been bidirectionally predicted coded by using motion compensated prediction coding, and detecting a frame type of the input coded data, Based on the detection result of the frame type detection means, the input coded data is held and output until the decoding period of each frame for each frame type, and the bidirectional predictive coding of the held coded data is performed. During the decoding period of the coded data of the frame, buffer means for outputting the coded data of the intra-frame coded frame or the coded data of the unidirectionally predicted coded frame as a backward or forward reference image, First decoding means for decoding the encoded data output from the buffer means to obtain a restored image; and the buffer means A second decoding means for decoding the encoded data output for the backward or forward reference image from the first decoding means to obtain a restored image, and a decoding means for decoding the predictively encoded frame from the first decoding means. First storage means for holding a restored image for use as a forward or backward reference image; and decoding the restored image from the second decode means for use as a backward or forward reference image for decoding of a predictively encoded frame. A decoding device, comprising: a second storage unit for holding.