JP2000222891A - Method and unit for rewriting memory of microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prolong the rewriting lifetime of memory while sustaining the general purpose performance of program without burdening a program being installed in a microcomputer. SOLUTION: A memory control circuit 8 controls data writing and erasure of an EEPROM 6 in a microcomputer. An address control circuit 10 rewrites the data held in the EEPROM 6 under control of the memory control circuit 8 and a counter 30 constituting the address control circuit 10 counts up the number of times when the memory control circuit 8 flash writes a data into the EEPROM 6 and holds the count nonvolatilisably. An address conversion circuit 32 delivers an address data to the EEPROM 6 while converting into an address data for accessing a different memory area thereof depending on the count held in the counter 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flash EEP.
This function functions in an apparatus and a method for rewriting the stored contents of a flash EEPROM in a microcomputer having a built-in ROM.

[0002]

2. Description of the Related Art A microcomputer (also called a flash microcomputer) having a built-in flash EEPROM capable of electrically writing or erasing data collectively.
Is widely used in various fields because various functions can be flexibly realized by rewriting program data and the like held in the EEPROM as needed. Incidentally, in this type of EEPROM, the number of rewritable times is generally limited due to deterioration of memory cells due to repetition of erasing and writing. Various attempts have been made to eliminate or alleviate such restrictions in terms of manufacturing methods and the like, but they have not yet reached a level that sufficiently satisfies the requirements.

Therefore, it is conceivable to increase the number of rewritable times by devising a method of using the flash EEPROM. For example, Japanese Patent Application Laid-Open No. 2-66696 discloses a method in which a nonvolatile memory is provided with a plurality of memory blocks (memory banks) and it is determined whether each memory block is usable. When this method is applied to a flash microcomputer, the configuration becomes, for example, a block diagram shown in FIG. The flash microcomputer 102 includes a CPU 104, a flash EEPROM 1
06, and the CPU 104 controls the address / data bus 10
The address data (also simply referred to as an address) output through the address latch 8 is stored in an address latch 110 and the EEPRO
M106, and writes data to the EEPROM 106 under the control of the memory control circuit 112.
Alternatively, data is read from the EEPROM 106. At this time, the data output from the CPU 104 is transferred to the EEPROM 106 through the write buffer 114.
The data read from the EEPROM 106 is output to an address / data bus 108 through a read buffer 116.

[0004] In this example, the EEPROM 106 is 4
Three first to fourth memory blocks 118, 120,
It is divided into 122 and 124, and a count area 126 is provided for each block. This count area 126
Indicates the number of times data has been written in the corresponding memory block, and whether or not data can be written in the same memory block is determined based on the value. With such a configuration, data writing can be performed by EEPROM.
Since the operation can be performed in a distributed manner over the entire M106, the life of the flash EEPROM 106 can be extended.

[0005]

However, in this method, the CPU 104 needs to supply different addresses to the EEPROM 106 depending on which memory block is used. Address control for that purpose is performed by a program, and a program incorporated in the flash microcomputer 102 must necessarily have such a function, which is strongly restricted. Further, since such a memory management function changes depending on the configuration of the memory block, etc., a program having the memory management function loses versatility, and if the flash microcomputer 102 changes,
The program must also be changed. Furthermore, when the above-described conventional technology is applied to the flash microcomputer 102, the count area 126 functions differently from the original intention of the above-described conventional technology. It becomes more complicated. The present invention has been made to solve such a problem, and its object is to extend the life of rewriting memory data without placing a burden on an embedded program and maintaining the versatility of the program. And a memory rewriting device for a microcomputer.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a flash EEPROM and the EEPROM.
A microcomputer having a memory control circuit for controlling writing and erasing of data to and from the OM;
An apparatus for rewriting data held in an EEPROM under the control of a memory control circuit, wherein the memory control circuit counts the number of times of batch writing of data to the EEPROM, and holds the count value in a nonvolatile manner. A counter and address data supplied to the EEPROM,
The EEP according to the count value held by the counter
An address conversion circuit that converts the data into address data in different storage areas of the ROM and supplies the data to the EEPROM, wherein the memory control circuit stores the data in each storage area of the EEPROM when the count value of the counter reaches a specified value. Data that has been erased at once.

Further, the present invention relates to a flash EEPROM.
And a memory control circuit for controlling writing and erasing of data to and from the EEPROM, wherein the data stored in the EEPROM is rewritten by the microcomputer.
Counting the number of times of batch writing of data to the ROM, holding the count value in a nonvolatile manner, and changing the address data supplied to the EEPROM to address data in different storage areas of the EEPROM according to the held count value. And the data is supplied to the EEPROM, and when the count value reaches a specified value, data stored in each storage area of the EEPROM is collectively erased.

In the present invention, the EEP is controlled by the memory control circuit.
The number of times of batch writing of data to the ROM is counted, the count value is held in a nonvolatile manner, and the address data supplied to the EEPROM is changed according to the held count value.
The data is converted into address data in a different storage area of the PROM and supplied to the EEPROM. Therefore, the storage areas can be switched and used in order, and rewriting is not concentrated on a specific storage area, and the rewriting life of the EEPROM can be extended. Even when the storage areas are switched in this manner, no burden is imposed on the program for operating the CPU constituting the microcomputer in terms of memory management. Therefore, the program does not need to have a function related to memory management, and the versatility of the program does not decrease.

Further, according to the present invention, when the count value reaches a specified value, data stored in each storage area of the EEPROM is collectively erased, so that every time data is rewritten in each storage area, the data is erased. As compared with the case where the erase operation is performed, the number of times of erasing is reduced, which is also advantageous in that the stress on the memory cells of the EEPROM is reduced and the life is extended. Furthermore, in the case of flash microcomputers, even if some data has been rewritten, data has been rewritten in the entire memory area, including other data that does not need to be rewritten. As a result, data loading and data writing However, in the present invention, since data can be written in one storage area unit,
Work can be completed in a short time. Also, since the data in each storage area is erased collectively as described above,
The time spent for erasing is reduced, and work can be performed efficiently in this regard.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a flash microcomputer including an example of a memory rewriting device of a microcomputer according to the present invention. FIG. 2 is a block diagram showing an address control circuit constituting the flash microcomputer of FIG. 1 in detail. FIG. 4 is a circuit diagram showing in detail the address conversion circuit constituting the control circuit, and FIG. 4 is a flowchart showing the operation of the flash microcomputer of FIG.
Hereinafter, an example of a memory rewriting device for a microcomputer according to the present invention will be described with reference to these drawings, and at the same time, an embodiment of a memory rewriting method for a microcomputer according to the present invention will be described.

The flash microcomputer 2 shown in FIG. 1 is composed of a single semiconductor chip, includes a CPU 4, a flash EEPROM 6, a memory control circuit 8, an address control circuit 10, and the like, and stores a relatively small amount of data held by the EEPROM 6. The configuration is suitable for applications that frequently change over a long period of time.

Address data output by the CPU 4 through the address / data bus 12 (also referred to simply as an address)
Are held in the address latch 14 and are stored in the address control circuit 10
Supplied to the EEPROM 6 through the memory control circuit 8
Under this control, data writing to the EEPROM 6 or data reading from the EEPROM 6 is performed. At this time, the data output by the CPU 4 is supplied to the EEPROM 6 through the write buffer 16, while the data read from the EEPROM 6 is output to the address / data bus 12 through the read buffer 18.

The storage area of the EEPROM 6 includes a memory block 20 and first to fourth memory blocks 22,
Data is rewritten in the first to fourth memory blocks 22, 24, 26, and 28. The address control circuit 10 includes a counter 30, an address conversion circuit 32, and an address decoder 34, as shown in FIG. The counter 30 counts the number of times the memory control circuit 8 performs batch writing of data to the EEPROM 6 and holds the count value in a nonvolatile manner even when the power of the flash microcomputer 2 is off. The address conversion circuit 32 converts the address data supplied to the EEPROM 6 into address data for accessing the first to fourth memory blocks 22, 24, 26, 28 of the EEPROM 6 according to the count value held by the counter 30. The data is supplied to the EEPROM 6. Specifically, the address conversion circuit 32, as shown in FIG.
It is a kind of addition circuit composed of multiple logic circuits,
In the present embodiment, the count value of the counter 30 is added to the upper bits of the address data.

The counter 30 is a 2-bit counter in the present embodiment, and its maximum value is three. When the fourth writing is performed on the EEPROM 6, the counter value becomes zero. . At this time, the memory control circuit 8
Erases data stored in the first to fourth memory blocks 22, 24, 26, and 28 of the EEPROM 6 collectively.

The address decoder 34 converts an address supplied from the CPU 4 into an address accessible by the actual EEPROM 6 as conventionally performed. The memory rewriting device of the present invention mainly includes an address control circuit 10, a memory control circuit 8, and an address latch 14 in this example.

Next, the operation of the flash microcomputer configured as described above will be described. Figure 5 shows an EEPROM
FIG. 6 is an explanatory diagram showing changes in memory blocks used for writing data in FIG. Hereinafter, this drawing and the flowchart of FIG. 4 will be referred to as appropriate. Here, the first to fourth memory blocks 22, 24, 2
Assume that the size of each of the memory blocks 6 and 28 is 400H bytes (H indicates a hexadecimal number), and as shown in the original memory map A of FIG. 22, 24, 26, and 28 are addresses F
000H to F3FFH, F400H to F7FFH, F8
The storage areas are 00H to BFFFH and FC00H to FFFFH. Note that the memory block 20 has 000
The range is from 0H to F000H.

In this embodiment, first, the data is first data.
Of the second memory block 24 when the first data rewriting is performed.
Data is written to Thereafter, in the second and third rewrites, the third and fourth memory blocks 26, 2
8 is written.

As shown in FIG. 4, when the count value of the counter 30 is 0, which is the initial value, the memory control circuit 8
When rewriting data in the EEPROM 6 under the control of the PU 4, the counter 30 adds 1 to the count value (step A1), and the count value becomes 1. At this time, the memory control circuit 8 checks whether or not the count value of the counter 30 is 0 (step A2). In this case, the memory control circuit 8 notifies the CPU 4 of the fact and does not control the data rewriting. Move on to

The CPU 4 first causes the address latch 14 to hold the write address (step A5), and supplies data to be written to the EEPROM 6 through the write buffer 16 (step A6). The address held by the address latch 14 is the address control circuit 10
Is supplied to the EEPROM 6, and in this state, the memory control circuit 8 instructs the EEPROM 6 to perform the writing (step A7). Thereafter, the memory control circuit 8 acquires the written data through the read buffer 18, and determines whether or not the writing has been normally performed (Step A8).

If the result of the determination is negative, the memory control circuit 8 returns to step A7 to perform rewriting, and proceeds to step A9 when the result of the determination in step A8 is YES. Here, it is determined whether or not writing of all data in one memory block has been completed. If the determination result is no, the process returns to step A5 to write the next data, and the determination result is YES in step A9. Until the writing operation is repeated.

Next, the operation of the address control circuit 10 particularly related to the present invention will be described in detail. EEPRO
The capacity of M6 is 64 KB in the present embodiment, and the address is 16 bits from bit 0 to bit 15 (00 bits).
00H to FFFFH). The address conversion circuit 32 calculates bit 10 and bit 11 of this address.
(Upper bits according to the present invention) include 2
The count value of the bit is added, and the result is set as the converted address. Then, this address is decoded by the address decoder 34 and then supplied to the EEPROM 6.

Table 1 shows the correspondence between the addresses before and after the conversion when the count value of the counter 30 is 1 (in the case of the first data rewrite).

[0023]

[Table 1] The four digits in the table are bit 1 of the address in order from the left.
1, 10, 9, and 8 are shown. As shown in the table, when these four bits are 0000 before conversion, the count value 1 is added, and after conversion, it becomes 0100. When the value before conversion is 0100, the value after conversion is 1000, and 1000 is 1
To 100, 1100 is converted to 1000.

In FIG. 5, a memory map A shows a memory map of the EEPROM 6 when the address conversion is not performed by the address conversion circuit 32. The first to fourth memory blocks 22, 24, 26, and 28 are described above. Are assigned to such addresses. On the other hand, when the conversion shown in [Table 1] is performed, if the four bits from bit 11 to bit 8 are 0000, for example, it becomes 0100 after the conversion, so that F000H to F3FFH output from CPU 4 The address in the range is F4
It is converted to an address in the range from 00H to F7FFH.
Since this is the address range of the second memory block 24, the CPU 4 changes bits 9 to 0 (lower-order bits according to the present invention) of the address to rewrite the data of the first memory block 22 to 0F000H.
When an address in the range from F3FFH to is output, data is written to the second memory block 24.

Therefore, it is not necessary for the memory control circuit 8 to erase the first memory block 22.
The program that causes U4 to perform such a write operation does not need to control the address so that data is written to the second memory block 24. FIG.
2 shows an equivalent memory map at the time of the first rewriting, and the second to fourth memory blocks 24, 26, and 28 each correspond to one memory block and are located at the lower side of the address. It is equivalently shifted.

Table 2 shows the correspondence between addresses before and after the conversion when the count value of the counter 30 is 2, that is, in the case of the second data rewriting.

[0027]

[Table 2] The four digits in the table are bit 1 of the address in order from the left.
1, 10, 9, and 8 are shown. As shown in the table, when these 4 bits are 0000 before conversion, the count value 2
Is converted to 1000 after conversion. Also, 0 before conversion
When it is 100, it becomes 1100 after conversion, and 1000 becomes 00
To 00, 1100 is converted to 0100.

When the conversion as shown in [Table 2] is performed, if the four bits from bit 11 to bit 8 are 0000, for example, it becomes 1000 after the conversion.
The addresses in the range from F000H to F3FFH output by PU4 are converted to addresses in the range from F800H to FBFFH. Since this is the address range of the third memory block 26 shown in the memory map A, the CPU 4
Outputs an address in the range from F000H to F3FFH in order to rewrite the data in the first memory block 22, the data is written to the third memory block 26. Therefore, the memory control circuit 8 does not need to erase the first and second memory blocks 24, and the program that causes the CPU 4 to perform such a write operation should write data to the third memory block 26. You don't need to control the address at all. The memory map C shown in FIG. 5 shows an equivalent memory map at the time of the second rewriting, and the third and fourth memory blocks 26 and 28 are each one more memory block and the lower side of the address. Is equivalently shifted to

Table 3 shows the correspondence between the addresses before and after the conversion when the count value of the counter 30 is 3, that is, in the case of the third data rewriting.

[0030]

[Table 3] The four digits in the table are bit 1 of the address in order from the left.
1, 10, 9, and 8 are shown. As shown in the table, when these 4 bits are 0000 before conversion, the count value 2
Is converted to 1100. Also, 0 before conversion
When it is 100, it becomes 0000 after conversion, and 1000 becomes 01
To 00, 1100 is converted to 1000.

When the conversion as shown in Table 3 is performed, if the four bits from bit 11 to bit 8 are 0000, for example, it becomes 1100 after the conversion.
Addresses in the range from F000H to F3FFH output by PU4 are converted to addresses in the range from FC00H to FFFFH. Since this is the address range of the fourth memory block 28 shown in the memory map A,
Outputs an address in the range from F000H to F3FFH in order to rewrite the data in the first memory block 22, the data is written to the fourth memory block.

Therefore, it is not necessary for the memory control circuit 8 to erase the first to third memory blocks 22, 24, and 26, and the program for causing the CPU 4 to perform such a write operation is stored in the fourth memory block. There is no need to control the address to write data to block 28. The memory map D shown in FIG. 5 shows an equivalent memory map at the time of the third rewriting, and the fourth memory block 28 is further equivalently shifted by one memory block to the lower side of the address. ing.

Table 4 shows the correspondence between the addresses before and after the conversion when the count value of the counter 30 is 0, that is, in the case of the fourth data rewriting.

[0034]

[Table 4] In this case, since the count value is 0, the address does not change between before and after the conversion. Therefore, the memory map in this case becomes the original memory map A, and the address output by the CPU 4 is output from the address conversion circuit 32 as it is.

In this case, since the determination result in step A2 of the flowchart of FIG. 4 is YES, the memory control circuit 8 sets the first to fourth memory blocks 22,
Erasing the whole of 24, 26 and 28 at once (step A
3) It is determined whether the data has been correctly erased (step A).
4) If the result is no, erase again (step A3),
If the result is positive, step A is performed to write data.
Go to 5. Then, the CPU 4 sets the first memory block 2
F000H to F3F
When an address in the range of FH is output, data is written to the corresponding first memory block 22.

As described above, in the present embodiment, since the memory block 20 is automatically switched according to the number of times of rewriting, the program for operating the CPU 4 does not have any burden in terms of memory management. . Therefore, the program does not need to have a function related to memory management, and the versatility of the program does not decrease. Since the four memory blocks 20 are switched and used in order, rewriting does not concentrate on a specific storage area, and the rewriting life of the EEPROM 6 can be extended. Further, in the present embodiment, 4
Since data is erased only when all the memory blocks 20 are used, the number of times of erasing is reduced, which also reduces stress on the memory cells of the EEPROM 6 and is advantageous in extending the life. Also, in the past, when rewriting a part of data, the flash microcomputer rewrites data in the entire memory area, including other data that does not need to be rewritten. As a result, data loading and data writing However, in this embodiment, since data is written in units of one memory block, the operation can be completed in a short time. In the present embodiment, one erasing operation is performed every four data rewrites, so that the time spent for erasing is reduced, and work can be performed efficiently in this respect as well.

In this embodiment, as described above, each time data is rewritten once, the memory block is equivalently shifted to the lower side of the address. It is also possible to adopt a configuration in which the memory banks are prepared as described above and the data are written by switching them in order. In this embodiment, four memory blocks are used, but the number of memory blocks may be any number as long as it is two or more, and the same effect can be obtained.

Next, a second embodiment will be described. The second embodiment has the same configuration as that of the flash microcomputer shown in FIG. 1, but the counter 30 (FIG. 2) constituting the address control circuit 10 The difference is that the value increases by two each time data is rewritten. Therefore, as shown in [Table 5], in the first rewriting, 2 is added to the bits 11 and 10 as the count value of the counter 30, and if the bits 11, 10, 9, and 8 before conversion are 0000, for example, the conversion is performed. After that, it becomes 1000, and before conversion 0100, 1000, 1
100 becomes 1100, 0000, and 0100, respectively.

[0039]

[Table 5] As a result, in the explanatory diagram of FIG. 6 corresponding to FIG.
Memory map E when rewriting has never been performed
And the third and fourth memory blocks 26 and 28 assigned to the addresses F800H to FFFFH.
Is equivalently shifted to the lower side of the address by two memory blocks as shown in the memory map E. Therefore, an address output by the CPU 4 to write data into the first and second memory blocks 22 and 24 is converted into an address for accessing the third and fourth memory blocks 26 and 28, supplied to the EEPROM 6, and Data is written to the third and fourth memory blocks 26, 28.

Also, in the second data rewriting, the count value of the counter returns to 0, so that the CPU
The address output to write data to the memory blocks 22 and 24 of the EEP is used as an address for accessing the first and second memory blocks 22 and 24 as it is.
It is supplied to the ROM 6 (see [Table 6]).

[0041]

[Table 6] However, in this case, since the count value of the counter is 0, as in the case of the above-described embodiment, the EEPROM is used.
6, the data is erased (step A in FIG. 4).
3). As a result, in the second embodiment, in addition to obtaining the same effect as the above-described embodiment, the count value of the counter increases by two, and therefore, unlike the above-described embodiment, Two memory blocks can be used in one rewrite, and it is possible to cope with a case where the rewrite data amount is larger.

[0042]

As described above, according to the present invention, the number of times data is written to the EEPROM at once by the memory control circuit is counted, and the count value is held in a nonvolatile manner.
The address data supplied to the EEPROM is converted into address data in a different storage area of the EEPROM in accordance with the held count value and supplied to the EEPROM. Therefore, the storage areas can be switched and used in order, and rewriting is not concentrated on a specific storage area, and the rewriting life of the EEPROM can be extended. Even when the storage areas are switched in this manner, no burden is imposed on the program for operating the CPU constituting the microcomputer in terms of memory management. Therefore, it is not necessary for the program to have a function related to memory management.
The versatility of the program does not decrease.

Further, according to the present invention, when the count value reaches the specified value, the data stored in each storage area of the EEPROM is collectively erased. As compared with the case where the erase operation is performed, the number of times of erasing is reduced, which is also advantageous in that the stress on the memory cells of the EEPROM is reduced and the life is extended. Furthermore, in the case of flash microcomputers, even if some data has been rewritten, data has been rewritten in the entire memory area, including other data that does not need to be rewritten. As a result, data loading and data writing However, in the present invention, since data can be written in one storage area unit,
Work can be completed in a short time. Also, since the data in each storage area is erased collectively as described above,
The time spent for erasing is reduced, and work can be performed efficiently in this regard.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a flash microcomputer including an example of a memory rewriting device for a microcomputer according to the present invention.

FIG. 2 is a block diagram showing an address control circuit constituting the flash microcomputer of FIG. 1 in detail;

FIG. 3 is a circuit diagram showing an address conversion circuit constituting the address control circuit of FIG. 2 in detail;

FIG. 4 is a flowchart showing an operation of the flash microcomputer of FIG. 1;

FIG. 5 is an explanatory diagram showing changes in memory blocks used for writing data in an EEPROM.

FIG. 6 is an explanatory diagram showing a change in a memory block used for writing data in an EEPROM in the second embodiment.

FIG. 7 is a block diagram illustrating an example of a flash microcomputer configured by applying the related art.

[Explanation of symbols]

2 ... Flash microcomputer, 4 ... CPU, 6 ... EE
PROM, 8 ... memory control circuit, 10 ... address control circuit, 12 ... address / data bus, 14 ... address latch, 16 ... write buffer, 18 ... read buffer, 20 ... memory block, 22 ... ... first memory block, 24 ... second memory block, 26 ...
... Third memory block, 28... Fourth memory block, 30... Counter, 32.
4 ... Address decoder, 102 ... Flash microcomputer, 104 ... CPU, 106 ... EEPROM, 10
8 ... address / data bus, 110 ... address latch, 112 ... memory control circuit, 114 ... write buffer, 116 ... read buffer, 118 ... first memory block, 120 ... second memory block , 12
2... Third memory block, 124... Fourth memory block, 126.

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] January 31, 2000 (200.1.3
1)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a flash EEPROM and the EEPROM.
A microcomputer having a memory control circuit for controlling writing and erasing of data to and from the OM;
An apparatus for rewriting data held in an EEPROM under the control of a memory control circuit, wherein the memory control circuit counts the number of times of batch writing of data to the EEPROM, and holds the count value in a nonvolatile manner. A counter and address data supplied to the EEPROM,
The EEP according to the count value held by the counter
An address conversion circuit that converts the data into address data in different storage areas of the ROM and supplies the data to the EEPROM, wherein the memory control circuit stores the data in each storage area of the EEPROM when the count value of the counter reaches a specified value. Data is erased at one time.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

Further, the present invention relates to a flash EEPROM.
And a memory control circuit for controlling writing and erasing of data to and from the EEPROM, wherein the data stored in the EEPROM is rewritten by the microcomputer.
Counting the number of times of batch writing of data to the ROM, holding the count value in a nonvolatile manner, and changing the address data supplied to the EEPROM to address data in different storage areas of the EEPROM according to the held count value. And the data is supplied to the EEPROM, and when the count value reaches a specified value, the data stored in each storage area of the EEPROM is collectively erased at a time.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction contents]

Further, according to the present invention, when the count value reaches a specified value, data stored in each storage area of the EEPROM is erased at once, so that each time data is rewritten in each storage area. The number of times that erasing is performed is smaller than in the case of
Stress on the memory cell is reduced, which is advantageous in extending the life. In addition, with flash microcomputers,
Even when rewriting part of the data, the data was rewritten in all memory areas, including other data that did not need to be rewritten.As a result, it took time to load and write the data. According to the present invention, since data can be written in units of one storage area, the work can be completed in a short time. In addition, since the data in each storage area is collectively erased at a time as described above, the time spent for erasing is reduced, and work can be performed efficiently in this respect as well.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction contents]

When the conversion as shown in [Table 2] is performed, if the four bits from bit 11 to bit 8 are 0000, for example, it becomes 1000 after the conversion.
The addresses in the range from F000H to F3FFH output by PU4 are converted to addresses in the range from F800H to FBFFH. Since this is the address range of the third memory block 26 shown in the memory map A, the CPU 4
Outputs an address in the range from F000H to F3FFH in order to rewrite the data in the first memory block 22, the data is written to the third memory block 26. Therefore, the memory control circuit 8 does not need to erase the first and second memory blocks 22 and 24, and the program that causes the CPU 4 to perform such a write operation stores data in the third memory block 26. There is no need to control the address to write. The memory map C shown in FIG. 5 shows an equivalent memory map at the time of the second rewriting, and the third and fourth memory blocks 26 and 28 are each one more memory block and the lower side of the address. Is equivalently shifted to

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction contents]

According to the present invention, when the count value reaches the specified value, the data stored in each storage area of the EEPROM is erased at once, so that each time the data is rewritten in each storage area. The number of times that erasing is performed is smaller than in the case of
Stress on the memory cell is reduced, which is advantageous in extending the life. In addition, with flash microcomputers,
Even when rewriting part of the data, the data was rewritten in all memory areas, including other data that did not need to be rewritten.As a result, it took time to load and write the data. According to the present invention, since data can be written in units of one storage area, the work can be completed in a short time. In addition, since the data in each storage area is collectively erased at a time as described above, the time spent for erasing is reduced, and work can be performed efficiently in this respect as well.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Takashi Kuwahara 1-403, Kosugicho, Nakahara-ku, Kawasaki-shi, Kanagawa 53 F-term within NEC Icy Microcomputer Systems Co., Ltd. 5B025 AA00 AB00 AC00 AD01 AD04 AD08 AE01 AE05 AE08 5B062 AA10 CC03 DD06 DD10 JJ10

Claims (6)

[Claims] A flash EEPROM; and said EEPROM.
An apparatus provided in a microcomputer having a memory control circuit for controlling writing and erasing of data in a ROM and rewriting data stored in the EEPROM under the control of a memory control circuit. Counts the number of times that batch writing of data to the EEPROM is performed, and a counter that holds the count value in a nonvolatile manner. The address data supplied to the EEPROM is stored in the EEPROM according to the count value held by the counter.
M to address data of different storage areas,
An address conversion circuit for supplying data to a PROM, wherein the memory control circuit erases data stored in each storage area of the EEPROM at a time when the count value of the counter reaches a specified value. Memory rewriting device for microcomputer. 2. The memory rewriting device according to claim 1, wherein the address conversion circuit changes upper bits of the address data based on the count value of the counter. 3. The memory rewriting device according to claim 2, wherein the address conversion circuit adds the count value of the counter to upper bits of the address data. 4. The microcomputer according to claim 2, wherein the memory control circuit performs batch writing of data to the EEPROM in an address range represented by lower bits than the upper bits of the address data. Memory rewriting device. 5. The memory rewriting device according to claim 1, wherein said microcomputer comprises a single semiconductor chip. 6. A flash EEPROM and said EEPROM.
A microcomputer having a memory control circuit for controlling writing and erasing of data to and from the ROM;
A method of rewriting data held in an EPROM, wherein the memory control circuit counts the number of times data is collectively written to the EEPROM, holds the count in a nonvolatile manner, and stores address data supplied to the EEPROM. Is converted into address data in a different storage area of the EEPROM in accordance with the held count value and supplied to the EEPROM. When the count value reaches a specified value, the EEPROM
A memory rewriting method for a microcomputer, wherein data stored in each storage area is erased collectively.