JP2000216747A - Cross polarized wave interference compensating system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimally set a cross polarized wave interference compensation device with only the operation at a receiver side. SOLUTION: This system is provided with a shift register circuit 27, that matches the delay time for a main signal path to pass from an antenna 20 up to an adder 26 through a demodulator 23 with a delay time in an interference compensation signal path from the antenna 20 up to the adder 26 through an interference compensation device and with a decoder 29 that decodes a demodulation signal whose cross polarization interference is compensated. The shift register circuit 27 consists of a means that controls number of stages of delay time adjustment means, a means that counts number of error pulses generated at decoding by a decoder 29, and a means that stores an error rate of each stage of the delay time adjustment means counted by the pulse count means. After sequentially changing the number of stages of the delay time adjustment means at initial setting and storing an error rate at each stage to a storage means respectively, number of the stages of the shift registers is selected as the number of stages, with which a uniformized delay with respect to increasing and decreasing delay time directions in a range stored in the storage means provides a best error rate and a maximum enhanced width.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cross polarization interference compensation system used in a digital microwave radio communication system, and more particularly to a system for adjusting a delay time difference due to a path difference between polarizations in a radio communication facility. .

[0002]

2. Description of the Related Art A digital microwave radio communication system using a cross polarization system is composed of two mutually orthogonal polarizations, for example, a vertical polarization (V polarization) and a horizontal polarization (H polarization), or a left-handed polarization. The effective use of frequency is achieved by transmitting different information for each of the circularly polarized wave and the right-handed circularly polarized wave. In this method, if a propagation obstruction such as rainfall is present, anisotropy of the medium occurs, and there is a possibility that interference occurs between cross polarizations.
In order to compensate for such cross-polarization interference, for example, a cross-polarization interference compensation system as described in Japanese Patent Application Laid-Open No. 5-260014 has been proposed.

When such cross-polarization interference compensation is performed, the path length from the transmitter on the different polarization side, which is the path of the interference path, to the demodulator on the own polarization side, and the interference compensation signal are used. The path length from a transmitter on a certain polarization side to a cross polarization compensator on the own polarization side must be equal. Therefore, in the wireless communication equipment, it is necessary to perform the following operation in order to adjust the delay time difference due to the path difference between the polarizations.

[0004] First, in order to know the delay time difference due to the path difference, the signal is output from one of the transmitters of the opposite station, received by the receiver of both polarizations on the receiving side, and the phase difference between the output signals of both receivers is obtained. Is measured. Next, the cable from the different polarization receiver to the cross polarization interference compensator is processed based on the delay time difference, and the length is adjusted to reduce the delay time difference. However, this work has a problem that the cable processing work in the office building is complicated and the control of the opposing transmitter is required. In order to solve the complexity of such cable processing work, Japanese Patent No. 2800774 proposes a method of adjusting a delay time difference due to a path difference between polarizations without performing a cable processing work in a station building. .

FIG. 5 is a block diagram showing a cross polarization interference compensation system proposed in the above-mentioned Japanese Patent No. 2800774. Hereinafter, a method of adjusting the delay time difference due to the path difference between the polarizations will be described with reference to FIG. First, the switch (SW) 14 is operated so that the V polarization transmitter 11 and the H polarization transmitter 12 output the same signal. S
W14 selects and outputs one of the two inputs. Here, the main signal is V-polarized, and the interference wave is H
A method of adjusting the delay time of two paths in the case of polarization will be described.

[0006] V · V output from the transmitting-side antenna 10
The RF frequency signal using the two polarization planes is received by the antenna 20 on the receiving side. The received signal is separated for each polarization, and is converted into an intermediate frequency signal by the V-polarization receiver 21 and the H-polarization receiver 22, respectively. Among the frequency-converted intermediate frequency signals, the output signal of the V-polarization receiver 21, which is an interference wave component leaking into the main signal, is demodulated into a baseband demodulated signal by a demodulator 23a and sent to a phase comparator 28a. Is output.

On the other hand, the output signal of the H-polarization receiver 22, which is a signal for removing the interference signal, is demodulated into a baseband demodulation signal inside the cross-polarization interference compensator 25a. As shown in FIG. 2, the cross polarization interference compensators 25a and 25b include a demodulation circuit 41 and a transversal filter 4.
2 to generate an interference compensation signal. Since the generation of the interference compensation signal is a known technique, a detailed description is omitted here.

In the cross polarization interference compensator 25a, the demodulation unit 4
In 1, the intermediate frequency signal on the H polarization side is demodulated using the carrier clock signal synchronized with the main signal output from the V polarization demodulator 23a. The demodulated signal is weighted by the transversal filter 42 at the time of normal interference compensation, and is output as an interference compensation component. However, when adjusting the delay time difference due to the path difference between the polarizations, the demodulated signal is output to the shift register 24a without any processing. Therefore, only the coefficient of the tap Co of the transversal filter 42 is set to 1, and all other tap coefficients are set to 0.

The interference compensation signal is supplied to a shift register 24
The bit is delayed by a and output to the phase comparator 28a together with the adder 26a. Here, the shift register 24a
Sets the initial value to the center of the total number of stages that can be delayed. The phase comparator 28a can be constituted by an exclusive OR circuit. For example, if two signals to be compared are the same, "1"
If "0" is output if they are different, the value is counted by the internal circuit, and if "1" is output continuously for more than a specified bit, it is determined that the phases are the same. Otherwise, it is determined that the phases are different, and control is performed to change the number of stages of the shift register 24a.

Under the control of the phase comparator 28a, the number of stages of the shift register 24a is varied in a certain direction, but if it does not match even if it is varied to the last stage, it returns to the initial value and varies the number of stages in the opposite direction. By doing so, the phase comparator 28a compares the signal output from the demodulator 23a with the signal output from the shift register 24a, and can control the value of the shift register 24a to be equal. When the two signals are controlled to be equal, the shift register 24a
The number of stages is fixed.

[0011]

The above-mentioned Patent No. 28007
According to the cross polarization interference compensation method proposed in No. 74, the same signal is transmitted from the V-polarization transmitter and the H-polarization transmitter on the opposite transmitting station side during the adjustment work, and this signal is transmitted. By adjusting the number of stages of the shift registers 24a and 24b provided on the respective paths on the receiving station side, the path lengths of both polarizations can be adjusted to be equal. Work can be simplified.

[0012] However, the above-mentioned Japanese Patent No. 2800774 is disclosed.
In the method proposed in the above publication, it is necessary to switch the switch 15 on the opposite station side during the adjustment work, and the transmission output control on the opposite station side must be performed, which causes a problem that the control becomes complicated.

An object of the present invention is to make it possible to adjust a delay time difference due to a path length difference between polarized waves by an operation only within the own station, thereby further simplifying the adjustment work.

[0014]

According to the present invention, there is provided a cross-polarization interference compensation system comprising: a receiving side for transmitting a delay time from an antenna, which is a main signal path, through a self-polarization demodulator to an adder; A shift register circuit for matching the delay time difference between the signal path antenna and the self-polarized wave through the cross polarization interference compensator to the adder; and a cross polarization interference compensated demodulation output from the adder. A decoder for decoding the signal;

The shift register circuit includes delay time adjustment control means for controlling the number of stages of delay time adjustment means, counting means for counting error pulses generated at the time of decoding by the decoder, and delay time counted by the coefficient means. The time adjustment means comprises a storage means for holding the error rate characteristic at each stage number, and the number of stages of the delay time adjustment means is changed by control from the delay time adjustment control means at the time of installation of the apparatus, that is, at the time of initial setting. Is stored in the storage means. And
The number of stages of the shift register is set to the number of stages which is equal to the delay time delay and the leading direction within the range where the error rate is the best among the values held in the storage circuit and gives the maximum improvement width.

Thus, it is necessary to operate the opposite station to transmit the pilot signal for measuring the delay time, or to perform a complicated operation of adjusting the waveguide length and the cable length in the station to make the delay time equal. Instead, the cross polarization interference compensator can be optimally set only by the operation within the own station.

[0017]

FIG. 1 is a block diagram showing an embodiment of the present invention. The cross-polarization interference compensation system according to the present invention includes an antenna 20 for receiving mutually orthogonal V-polarized and H-polarized RF frequency signals transmitted from the opposite station;
V-polarized wave receiver 2 which converts a received RF frequency signal into an intermediate frequency signal, and keeps its output at a constant level and outputs it.
1. A receiver 22 for H polarization and a demodulator 23 for demodulating and identifying the intermediate frequency signal and outputting a baseband demodulated signal.
a, 23b and an intermediate frequency signal on the different polarization side as input, a cross polarization interference component is reproduced with a carrier and a clock signal output from the demodulator on the own polarization side to generate an interference compensation signal. Interference compensators 25a and 25b and shift register circuit 27 capable of bit-delaying the interference compensation signal
a, 27b, an interference compensation signal output from the shift register circuits 27a, 27b, and a baseband demodulated signal output from the demodulators 23a, 23b, and a baseband demodulated signal from which cross-polarization interference components have been removed. , And decoders 29a and 29b that decode the baseband demodulated signal from which cross-polarization interference has been removed and correct the error.

As shown in FIG. 2A, the cross polarization interference compensators 25a and 25b are composed of a demodulation circuit 41 and a transversal filter 42. The transversal filter 42 has a (2n + 1) tap configuration as shown in FIG. 2B, and generates an interference compensation signal by performing weighting. Further, as shown in FIG. 3, the shift register circuits 27a and 27b
A shift register 31 for delaying the interference compensation signal by a predetermined time slot, and a counting circuit 34 for counting error pulses generated at the time of error correction in the decoders 29a and 29b.
And a storage circuit 33 for storing the counted result, and a shift register control circuit 32 for changing the number of stages of the shift register.
It is composed of

Next, the operation of the present embodiment will be described with reference to the drawings. In FIG. 1, when performing cross-polarization interference compensation, the path length from the receiving station antenna to the self-polarization demodulator, which is the path of the interference wave, and the cross-polarization interference of the self-polarization, which is the interference compensation signal, Unless the path lengths to the compensator are equal, optimal interference compensation cannot be performed.

For example, if the main signal is H-polarized and the interference wave is V-polarized, the antenna 2
0 to V polarization receiver 21 to demodulator 23a to adder 26a
And the path length from the antenna 20 to the H-polarization receiver 22 to the cross-polarization interference compensator 25a to the shift register 27a to the adder 26a, which is a path for generating a signal for removing the signal, is equidistant. That is, the delay time of each path must be equal.

Similarly, when the main signal is H-polarized, a path from the antenna 20 to the H-polarized wave receiver 22 to the demodulator 23b to the adder 26b and a path for generating a signal for removing the same are provided. The path lengths from the antenna 20 to the V polarization receiver 21 to the cross polarization interference compensator 25b to the shift register 27b to the adder 26b must be equal, that is, the delay time of each path must be equal. Hereinafter, the method of adjusting the delay time of the two paths according to the present invention will be described with the main signal being V polarization and the interference wave being H polarization.

An RF frequency signal using two V · H polarization planes output from the opposite station is received by an antenna 20 on the receiving side. The received signal is separated for each polarization, and a V-polarization receiver 21 and an H-polarization receiver 22 are respectively provided.
Is converted to an intermediate frequency signal. Of the frequency-converted intermediate frequency signals, the output signal of the V-polarization receiver 21, which is the main signal path, is demodulated into a baseband demodulated signal by the demodulator 23a, and on the other hand, becomes a path for interference compensation. Is generated as an interference compensation signal inside the cross polarization interference compensator 25a and output to the shift register circuit 27a.

The interference compensation signal delayed by a predetermined time slot in the shift register circuit 27a is added to the adder 26a
The demodulated baseband signal is added to remove the interference component. The baseband demodulated signal from which the interference component has been removed is
After being input to the decoder 29a and error-corrected and decoded, it is output from the device. Also, the decoder 29a outputs 1 at the time of error correction.
Each time a bit is corrected, one bit of an error pulse is output.

Here, the operation of the cross polarization interference compensators 25a and 25b will be described with reference to FIG. The demodulation circuit 41 demodulates the intermediate frequency signal on the different polarization side using the carrier signal and the clock signal synchronized with the main signal output from the demodulator on the own polarization side. The demodulated signal passes through the transversal filter 42, and the interference compensation signal is output to the shift register circuits 27a and 27b by weighting Cn.

Next, referring to FIG.
The method of setting a and 27b will be described. The interference compensation signal output from the cross polarization interference compensator 25 is output through the shift registers 31 of the number of stages determined by the shift register control circuit 32. At this time, the counting circuit 34 receives the error pulse determined by the decoder as input, counts the number of error pulses per unit time set in the shift register, and outputs the result to the storage circuit 33.

The storage circuit 33 stores the number of error pulses per unit time, that is, the error rate, for each number of stages of the shift register 31. In the shift register control circuit 32, the number of stages of the shift register 31 can be changed by the control signal. At the time of initial setting of the receiving device, the following operation is performed to set the number of stages of the shift register 31.

First, the number of stages of the shift register 31 is set to a minimum, and the error rate at that time is measured by the counting circuit 34.
After the value is stored in the storage circuit 33, the number of stages of the shift register 31 is increased by one according to a control signal from the shift register control circuit 32, and the error rate at the number of stages is measured again by the counting circuit. The value is stored in the storage circuit 33. Each shift register 31 that can be set in the same manner as described below
The error rate at the number of stages is measured by the counting circuit 34 and the storage circuit 3
3 is stored.

FIG. 4 (a) shows a main signal path from the antenna 20 through the self-polarized wave demodulator 23a and the adder 26a.
, The path length from the antenna 20, which is the path of the interference compensation signal, to the adder 26a through the self-polarized cross polarization interference compensator 25a, and the cross polarization. The relationship between the amounts of interference compensation is shown in the graph. FIG. 4B shows the relationship between the error rate at that time, that is, the amount of error pulses generated and the delay time.

Generally, the cross polarization interference compensators 25a, 25
b, the compensating ability for the delay time difference is determined by the number of taps of the internal transversal filter 42 (in this case, 2n
+1) and its sampling time T. If the error rate at that time is measured while varying the number of stages of the shift register 31, when the shift register 31 is set in a place where there is no compensation capability, a large amount of errors occur and the error rate becomes high, but the compensation capability becomes high. If it is set in a certain place, almost no errors occur.

Therefore, the delay time is set to be equal to the delay time delay and the leading direction within the range where the error rate is the best among the values held in the storage circuit and to provide the maximum improvement width, so that the delay time is set. It is possible to set a value having an optimal amount of interference compensation in the plus direction and the minus direction. Normally, the antenna 20 is installed so as to minimize the cross polarization interference. However, at the time of initial setting, that is, in adjusting the delay time, the polarization plane of the antenna 20 is rotated by an appropriate angle to intentionally reduce the cross polarization interference. In this case, the number of stages of the shift register can be set efficiently.

[0031]

According to the present invention, at the time of initial setting of the apparatus, the delay time from the antenna which is the main signal path to the adder through the self-polarized wave demodulator and the antenna which is the path of the interference compensation signal. The number of stages of the shift register for sequentially matching the delay time difference through the self-polarized cross polarization interference compensator to the adder is sequentially changed, and the bit error rate is coefficient-stored in the storage circuit. The number of stages of the shift register is set so as to be equal to the delay time delay and the leading direction within the range where the error rate is the best among the set values, and to provide the maximum improvement width. It does not require a complicated operation to operate and transmit a pilot signal or adjust the waveguide length and cable length in the station to make the delay time equal length. Wave interference償器 it is possible to optimally set up.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing details of a cross polarization interference compensator.

FIG. 3 is a block diagram showing a shift register circuit used in the present invention.

FIG. 4 is a diagram for explaining a path length adjustment principle according to the present invention.

FIG. 5 is a block diagram showing a conventional example.

[Explanation of symbols]

 10, 20 Antenna 11 Transmitter for V polarization 12 Transmitter for H polarization 13a, 13b Modulator 15 Switch 21 Receiver for V polarization 22 Receiver for H polarization 23a, 23b Demodulator 24a, 24b Shift register 25a , 25b Cross polarization interference compensator 26a, 26b Adder 27a, 27b Shift register circuit 28a, 28b Phase comparator 29a, 29b Decoder 31 Shift register 32 Shift register control circuit 33 Storage circuit 34 Counting circuit 41 Demodulation circuit 42 Transversal filter

Claims (4)

[Claims] 1. A cross-polarized signal of a signal on a self-polarization side is received by receiving cross-polarized signals whose polarization planes intersect each other sent from a transmission side and obtaining a cross-polarization interference component from a signal on a different polarization side. In a cross polarization interference compensation system adapted to compensate for interference, a decoder for decoding a demodulated signal subjected to cross polarization interference compensation,
Means for counting error pulses generated each time the decoder performs error correction upon decoding, and compensating for a delay time difference between the signal on the own polarization side and the signal on the different polarization side based on the result of counting the error pulses. A cross-polarization interference compensation method, comprising: 2. The apparatus according to claim 1, wherein said means for compensating for the delay time difference comprises variable delay means for varying a delay amount of a signal on a different polarization side based on a result of counting the error pulses. 2. The cross polarization interference compensation system according to 1. 3. The variable delay means includes: a shift register having a variable number of delay stages; a delay time switching control means for sequentially controlling the number of delay stages of the shift register when performing compensation control of the delay time difference; Counting means for counting the number of error pulses generated each time the decoder performs error correction during decoding for each number of delay stages of the shift register, and counting the number of error pulses counted by the coefficient means for each number of delay stages of the shift register. Storage means for storing as an error rate characteristic, and delay time setting control means for setting the number of stages of the shift register to the number of stages having the best error rate among the values held in the storage circuit. Claim 2
The described cross-polarization interference compensation method. 4. The delay time setting control means includes means for setting a range in which the error rate is the best among the values stored in the storage means, and a delay in the range in which the error rate is the best. 4. The cross polarization interference compensation system according to claim 3, further comprising means for setting and controlling the number of stages of said shift register so as to be at an even position with respect to time delay and advance direction.