JP2000216644A - Buffer circuit and image display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a buffer circuit that can handle a high amplitude and broadband input signal and realize reduction in a current at no signal and a broad band characteristic and to provide an image display device using the buffer circuit. SOLUTION: An emitter follower circuit is configured with transistors(TRs) Q4, Q5 that are connected in series between a supply line for a power supply voltage VCC and the ground potential GND, an input signal IN is given to the base of the TRQ4, and a control voltage resulting from adding a voltage in response to a high frequency component of an inverted signal INV extracted by a high pass filter consisting of a capacitor C1 and an input impedance when viewed from a node ND 2 to a constant voltage VA generated by diode- connected TRs Q1, Q2 and a resistive element R1 connected in series to them is fed to a base of the TRQ5 so as to control the supply current I2 to the TRQ5 in response to the high frequency component of the input signal. Thus, the operating current of the emitter follower circuit can be controlled in response to the frequency of the input signal so as to reduced the current at no signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a CRT (Cathode-
The present invention relates to a buffer circuit provided before a driving circuit for driving a ray tube and supplying a wide-band, large-amplitude signal to the driving circuit, and an image display device using the buffer circuit.

[0002]

2. Description of the Related Art CRTs are widely used as one of image display means in computers, television receivers and the like. Driving a CRT requires a wide-band and large-amplitude drive signal. In order to output such a drive signal, a buffer circuit including a bipolar transistor and an amplifier circuit for further amplifying an output signal of the buffer circuit are provided.

FIG. 5 shows an example of a buffer circuit generally used conventionally. As shown, this buffer circuit is configured by an emitter follower circuit including an npn transistor N1 and a current source IS1. The input signal IN is applied to the base of the transistor N1, and an output signal OUT corresponding to the input signal IN is output from the emitter of the transistor N1.

The operating frequency of a buffer circuit used as a preamplifier for a drive circuit of a display device such as a CRT differs depending on the application. For example, a CRT used for a television receiver requires a bandwidth of 10 MHz. In the case of a computer display or the like, a wider bandwidth, for example, a bandwidth of about 150 MHz may be required. Therefore, when the buffer circuit shown in FIG. 5 is used, the driving current I _e required in the high frequency band is required.
Must always be supplied by the current source IS1.
In the no-signal state, that is, in the idling state, wasteful power is consumed.

[0005] In order to solve the above-mentioned problem, a buffer circuit constituted by a push-pull circuit has been proposed.
FIG. 6 shows an example of a buffer circuit composed of a push-pull circuit. As shown, in this buffer circuit, npn transistors N1 and N2 and pnp transistors P1 and P2 are used, respectively. Connected in series between the transistors N1 and P1 is the power supply voltage V _CC ground potential GND, and the emitters of transistors N1 and P1 are connected in common, and the connection point is connected to the output terminal of the buffer circuit. The input signal IN is applied to the base of the transistor N1. A diode-connected transistor N2 is connected between the bases of the transistors N1 and P1.
And P2 are connected in series. Further, a current source IS2 is connected to the base of the transistor P1, and the current source I2
The S2, the current I _B supplied. A load circuit connected to the output terminal of the buffer circuit, for example, CR
The drive circuit of T has a predetermined input impedance and a load capacitance, and charges (discharges) or discharges (discharges) the load capacitance with a buffer circuit.

In the buffer circuit constituted by the push-pull circuit described above, for example, when the input signal IN is at a high level, a drive current is supplied to the output terminal side by the transistor N1, and the load capacitance is charged by the drive current. . On the other hand, when the input signal IN is at a low level, a current flows through the transistor P1, and the load capacitance is discharged by the current.

In the buffer circuit constituted by the push-pull circuit, almost no current flows through the transistors N1 and P1 at the time of idling, so that the power consumption when there is no signal can be greatly reduced.

[0008]

By the way, in the above-mentioned buffer circuit constituted by the conventional push-pull circuit, a pnp transistor and an np transistor having different channel conductivity types are used.
Since both n transistors are used, a pnp transistor and an npn transistor having substantially the same high-frequency characteristics are required. However, in the current bipolar transistor process, it is difficult to manufacture a pnp transistor having a high-frequency characteristic equivalent to that of an npn transistor. Therefore, the operable frequency band of a buffer circuit including a push-pull circuit is as follows: There is a disadvantage that it is almost restricted by the high frequency characteristics of the pnp transistor and cannot be used in a high frequency band.

The present invention has been made in view of the above circumstances, and an object of the present invention is to use a buffer circuit which can handle an input signal of a large amplitude and a wide band, and which can realize a reduction in idling current and a wide band characteristic. An image display device is provided.

[0010]

To achieve the above object, a buffer circuit according to the present invention comprises an input signal applied to a control terminal, a current source connected to an emitter, and a signal corresponding to the input signal from the emitter. And a control signal generating circuit that extracts a signal in a predetermined frequency band of the input signal and controls a supply current of the current source in accordance with the extracted signal.

An image display device according to the present invention is an image display device for amplifying an input image signal and displaying the amplified signal on a CRT.
A buffer circuit for amplifying the image signal to a predetermined amplitude,
An amplifier circuit for amplifying an output signal of the buffer circuit to a large amplitude signal necessary for display on the CRT and outputting the amplified signal to the CRT, wherein the buffer circuit receives the input image signal at a control terminal; A current source is connected to the emitter,
An output transistor from which a signal corresponding to the image signal is output from the emitter; and a control signal for extracting a signal of a predetermined frequency band of the image signal and controlling a supply current of the current source according to the extracted signal. A generation circuit.

In the present invention, preferably, the control signal generation circuit includes a voltage source for supplying a predetermined constant voltage, and a high-pass filter circuit for extracting a predetermined high frequency component of the image signal. And outputting the sum of the output signal of the filter circuit and the supply voltage of the voltage source as the control signal.

Further, in the present invention, preferably, the current source receives the control signal at a control terminal, and one terminal, for example, a collector is connected to an emitter of the output transistor, and the other terminal is For example, it is composed of a current output transistor whose emitter is connected to a common potential.

According to the present invention, the buffer circuit is constituted by the emitter follower circuit comprising the output transistor and the current source connected to the emitter. The current source includes a current output transistor having a base to which a control signal generated by a control signal generation circuit is applied, so that a supply current according to the control signal is output. The control signal generation circuit outputs, for example, a voltage signal obtained by adding a voltage corresponding to a predetermined frequency component of the input signal, for example, a high frequency component to a predetermined constant voltage, as a control signal. According to the control signal, the operating current of the emitter follower circuit is controlled to be large according to the high frequency component of the input signal.
Broadbanding of the buffer circuit is realized. In addition, when there is no signal, the base voltage of the current output transistor constituting the current source is set low, so that the idling current is reduced and power consumption is reduced.

[0015]

FIG. 1 is a block diagram showing the overall configuration of an image display device using a buffer circuit according to the present invention. As shown, the image display device includes a buffer circuit 10, an input switch 20, a drive circuit 30, an OSD controller 40, a horizontal / vertical synchronization signal processing circuit 50, a deflection correction processing circuit 60, and a microcomputer (microcomputer) 7.
0, a ROM 80 and a CRT 90.

The input switch 20 selects a plurality of input image signals and synchronization signals, and outputs the selected signals to the buffer circuit 10, the horizontal / vertical synchronization signal processing circuit 50, and the microcomputer 70, respectively. For example, a recent high-end is a BN having different specifications in an image display device.
It has two inputs, an S connector and a D-sub connector. The input switch 20 selects one of these inputs and supplies it to the internal circuit.

The buffer circuit 10 includes an input switch 20
A selected image signal, for example, an RGB signal is amplified in a predetermined manner.
And the amplified signal is input to the drive circuit 30.
You. For example, the buffer circuit 10
0.7V selected amplitude_ppAmplify the RGB signals of
3V width_PPIs output. Here, V _pp
Is the voltage difference between the maximum and minimum values of the signal.
Means the so-called Peak-to-peak value.

The driving circuit 30 further amplifies the image signal from the buffer circuit 20, generates a large amplitude image signal, and drives the CRT. For example, the drive circuit 30 amplifies the 3 V _pp RGB signal from the buffer circuit 10 to 60 V _pp and outputs the signal to the CRT. As described above, the drive circuit 30 is a main driver in the image display device,
The buffer circuit 10 is a preamplifier that supplies a signal to a main driver.

The horizontal / vertical synchronizing signal processing circuit receives the horizontal synchronizing signal and the vertical synchronizing signal selected by the input switch 20, and in accordance with these synchronizing signals, generates horizontal and vertical deflection signals necessary for displaying an image on a CRT. appear. The deflection correction processing circuit 60 performs deflection correction on the horizontal and vertical deflection signals input from the horizontal / vertical synchronization signal processing circuit, and converts the corrected horizontal and vertical deflection signals into CR signals.
Supply to T.

The microcomputer 70 receives the horizontal / vertical synchronization signals from the input switch 20 and generates various timing signals. Further, necessary data is read from the ROM 80, and a timing signal and a display signal are generated in accordance with the read data in accordance with the synchronization signal.

An OSD (On Screen Display) controller 40 generates information such as a display / non-display instruction on the screen and a display position on the screen when displaying in response to a timing signal and a display signal from the microcomputer 70. Then, an image signal corresponding to the information is output to the buffer circuit 10. The OSD is, for example, brightness / contrast /
When adjusting the screen size / screen position and the like, numbers, codes, and the like displayed on the display screen of the CRT are included.

In the image display device constituted by the respective partial circuits described above, the minute image signal selected by the input switch 20 has a large amplitude and a small amplitude by the driving circuit 30 connected to the buffer circuit 10 and its output side. The signal is amplified to a broadband signal, the CRT 90 is driven by the output signal of the drive circuit 30, and an image signal is displayed. Therefore, the buffer circuit 10 is required to be able to amplify a large-amplitude signal and a wide-band image signal and to have low power consumption. Hereinafter, embodiments of a buffer circuit according to the present invention will be described in detail with reference to circuit diagrams.

FIG. 2 is a circuit diagram showing the basic concept of the buffer circuit of the present invention. As shown, the buffer circuit 10 of the present invention includes an npn transistor N1 and a current source IS.
Emitter follower circuit and current source IS1
It comprises a control signal generating circuit for generating a control signal S _C for controlling a zero current. The control signal generation circuit includes a filter circuit 12, an addition circuit 14, and a voltage source VS10 that supplies a bias voltage.

An input signal IN is applied to the base of the transistor N1, for example, as shown. Transistor N
The output signal OUT is output from one of the emitters. The supply current of the current source IS10 is controlled in accordance with the input control signal S _C. The control signal S _C is _supplied to the filter circuit 1
2 is obtained by adding the bias voltage V ₀ supplied from the voltage source VS10 to the output signal S _F of No. 2.

The filter circuit 12 receives, for example, the input signal I
It comprises a high-pass filter (high-pass filter) that receives the inverted signal INV of N and extracts the high-frequency component of the inverted signal INV. The addition circuit 14 calculates the sum of the bias voltage V ₀ and the output signal S _F of the filter circuit 12, and outputs the sum to the current source IS10 as a control signal S _C.

The output current _{Ie of the} current source IS10 is controlled according to the control signal S _C. Therefore, when there is no signal,
That is, when the level of the input signal IN is 0 V _pp , the current source I
In S10, a predetermined constant current controlled by the bias voltage V ₀ is supplied. On the other hand, when the predetermined signal IN is input, the high frequency component S _F of the inverted signal INV of the input signal IN is output by the filter circuit 12, and according to the sum of the high frequency component S _F and the bias voltage V ₀ , Current source IS
The ten output currents _Ie are controlled. That is, the current source IS1
Reference numeral 0 denotes a signal component in a predetermined frequency band of the input signal IN, and in this embodiment, a current _Ie controlled according to a high-frequency component is supplied as an operating current of the emitter follower circuit.

Hereinafter, the load of the buffer circuit 10 and the current source I
The relationship with the output current in S10 will be described. FIG.
FIG. 4 is a diagram for explaining a relationship between a load of a buffer circuit 10 and an output current. As shown, a load capacitance C is connected to the output terminal of the buffer circuit. Buffer circuit 10
Is the input signal I input to the base of the transistor N1.
Depending on the N, and supplies the charging current I _C or discharge current I _D with respect to the load capacity. For example, when the input signal IN is at a high level, the transistor N1 is turned on, the buffer circuit 10 supplies a charge current I _C in capacitive load C through the transistor N1. Accordingly, the load capacitance C is charged, and the voltage of the output signal OUT of the buffer circuit 10 increases. Conversely, when the input signal IN is at a low level, the transistor N1 is turned off, and the buffer circuit 10
The supply current _{Ie of} 0 is supplied to the load capacity as the discharge current _ID . In response, the charge accumulated in the load capacitance C is discharged to the ground side via the current source IS10, and the buffer circuit 1
The voltage of the output signal OUT of 0 drops.

Here, the input signal IN and the output signal OU
Consider the fall of T. For example, as shown in FIG. 3, it is assumed that the input signal IN has changed by a voltage ΔV at time Δt. At this time, in order to change the output signal OUT at the same slew rate, the discharge current _ID required for the buffer circuit 10 is obtained by the following equation.

[0029]

I _D = CΔV / Δt (1)

From equation (1), it can be seen that the amount of current required to change by the same voltage increases as the fall time of the signal increases (that is, as the frequency of the signal increases). When the signal falls, the buffer circuit 10 is used to discharge the charge stored in the load capacitance C.
It is necessary to supply a current equal to or greater than the discharge current _ID shown in the equation (1) to the current source IS10. That is, the supply current I _e of the current source IS10, it is necessary to set the lower limit I _D shown in Equation (1). Note that the input signal IN and the output signal O
When the UT rises, the load capacitance C is charged through the transistor N1. At this time, the slew rate of the rise of the output signal OUT is substantially determined by the driving capability of the transistor N1, so that the size of the transistor N1 is reduced. By appropriately setting, the slew rate of the rising edge of the output signal OUT can satisfy a desired reference value. That is, the current supply current capability of the current source IS10 determines the slew rate of the fall of the output signal OUT. When the input signal IN and the output signal OUT rise, the supply current _Ie of the current source IS10 may be small.

FIG. 4 is a circuit diagram showing a specific configuration example of the buffer circuit in the present embodiment. As shown,
The buffer circuit 10a of the present example includes an npn transistor Q1
To Q5, resistance elements R1 to R4, and capacitor C1.

The transistors Q4 and Q5 are connected to the power supply voltage V _CC
Are connected in series between the supply line and the ground potential GND. The base of the transistor Q4 is connected to the input terminal T _IN of the input signal IN via the resistance element R4. The emitter of the transistor Q4 and the collector of the transistor Q5 are connected in common.
_Is connected to the output terminal T _OUT of. The resistance element R4 connected to the base of the transistor Q4 is provided for preventing oscillation. When there is no possibility of oscillation due to the characteristics of each element constituting the buffer circuit 10a, output load, and the like, The resistance element R4 can be omitted. The transistors Q4 and Q5 form an emitter follower circuit. The collector current I ₂ of transistor Q5 is the operating current of the emitter follower circuit. That is, the transistor Q5 corresponds to the current source IS10 in FIGS. The circuit connected to the base of the transistor Q5 is a control signal generation circuit for controlling the supply current of the current source IS10. Hereinafter, this portion will be described in detail with reference to FIG.

The resistance element R1 and the diode the connected transistors Q1, Q2 are connected in series between the supply line of the power supply voltage V _CC and the ground potential GND. Resistance element R
1 and the transistor Q1 are connected to the node ND1
Are formed. The capacitor C1 is connected to the inverted input signal IN
It is connected between the V input terminal T _INV and the node ND2. A resistance element R is connected between nodes ND1 and ND2.
2 are connected. The base of transistor Q3 is connected to the node ND2, the collector is connected to the supply line of the power supply voltage V _CC, and the emitter is grounded through a resistor R3. The base of the transistor Q5 is the transistor Q3
Connected to the emitter.

Here, assuming that the base-emitter voltages of the transistors Q1 and Q2 are both V _BE , the node ND1
The voltage V _A, the 2V _BE. That is, a constant voltage source that supplies a constant voltage is configured by the transistors Q1 and Q2 that are diode-connected to the resistance element R1. When the input signal IN is absent, that is, when the input signal IN and its inverted signal INV have no AC component and only a DC component, the input signal is cut off by the capacitor C1. In this case, since the base current of the transistor Q3 is very small, there is little current in the resistor element R2, the voltage V _B of the node ND2 is equal to the voltage V _A of approximately node ND1. That is, V _B = V _A = 2V _BE . Further, when the base-emitter voltage of transistors Q3 and Q5 is substantially equal to V _BE , the current flowing through transistors Q3 and Q5 is very small, and the power consumption of buffer circuit 10a when there is no signal can be reduced.

Here, assuming that the size of the transistor Q5 is m times the size of the transistors Q1 and Q2 (m ≧ 1, m is an integer), the emitter current I _{2 of the} transistor Q5
The current I ₁ flowing through the transistors Q1 and Q2 m
Double. That is, I ₂ = mI ₁ .

[0036] If the signal to the terminal T _INV is input, i.e., when the AC signal is input to the terminal T _INV, a predetermined frequency component of the input signal is extracted. Viewed from the input terminal T _INV of the inversion signal INV, the high-pass filter is configured. Here, the capacitance value of the capacitor C1 and C _1, and the node ND2 viewed from the input impedance R
Then, the high-pass filter constituted by these has a transfer function H (jω) represented by the following equation.

[0037]

(Equation 2)

That is, a high-pass filter having a primary characteristic equivalent to the inverted signal input terminal T _INV is connected. The high-pass filter allows the input inverted signal INV
Is extracted and applied to the base of the transistor Q3.

According to equation (2), the amplitude characteristic | H (jω) | of the transfer function of the high-pass filter is obtained by the following equation.

[0040]

(Equation 3)

[0041] For example, the inverting input terminal T _INV to the frequency f,
When the signal INV having the amplitude ΔV is input, the node ND2
The voltage _{V B, V B = 2πfRC 1} ΔV / (1 + 4π 2
the ^{_{f 2 R 2 C 1 2)}} 1/2. That is, the voltage V _B increases the frequency of the input signal IN generated in higher node ND2. Since the emitter voltage of variation only the transistor Q5 of the voltage V _B at the node ND2 is changed, the collector current I ₂ of the transistor Q5 in response to variation of the emitter voltage
Is controlled.

[0042] Incidentally, in the buffer circuit 10a shown in FIG. 4, first order high pass filter by inverting signal INV for controlling the supply current I ₂ of the transistor Q5 of the input signal IN has substantially the same function as the differential circuit. As shown in FIG. 2, in response to the rise of the input signal IN, a voltage signal lower than in the non-signal state is input to the base of the transistor Q5. Conversely, in response to the fall of the input signal IN, a higher voltage signal than when there is no signal is supplied to the base of the transistor Q5. This control, when the input signal IN is at a high level, i.e., when supplying the charging current I _C in the load capacitance by transistors Q4, by reducing the supply current of the transistors Q5, increase the charging speed of the load capacitance it can. Conversely, when the input signal IN is at low level, i.e., when discharging the load capacitor with a current I ₂ of the transistors Q5, by increasing the current I ₂ of the transistors Q5, it can increase the discharge speed of the load capacitance. By such control, the slew rate of both the rising and falling of the output signal OUT is increased.

In the buffer circuit 10a of this embodiment, the inverted signal INV of the input signal is output by the high-pass filter.
Is extracted, and the supply current of the transistor Q5, which is a current source, is controlled accordingly. Therefore, the higher the frequency of the input signal IN, the larger the operating current of the emitter follower circuit is controlled, and Can achieve a high slew rate required for the output signal OUT.

[0044] As described above, according to this embodiment constitutes an emitter follower circuit by the transistors Q4 and Q5 which are connected in series with the supply line of the power supply voltage V _CC and the ground potential GND, and the base of the transistor Q4 The input signal IN is input to the base of the transistor Q5, and the constant voltage V _A generated by the transistors Q1 and Q2 diode-connected to the resistor R1 connected in series.
A control voltage to which a voltage corresponding to a high-frequency component of the inverted signal INV extracted by a high-pass filter constituted by the capacitor C1 and the input impedance viewed from the node ND2 is applied is applied to the transistor Q5 according to the high-frequency component of the input signal. and controls the current I _2, the operating current of the emitter follower circuit higher the frequency of the input signal can greatly control can be set in accordance with the slew rate of the output signal to the high-frequency component of the input signal, improving wideband characteristics of the buffer circuit Power consumption can be reduced by reducing the operating current of the emitter follower circuit when there is no signal.

[0045]

As described above, according to the buffer circuit and the image display device of the present invention, the operating current of the buffer circuit when there is no signal can be reduced, and the operating current can be controlled according to the high frequency component of the input signal. The input / output characteristics of the buffer circuit in a large amplitude and high frequency band can be improved. Furthermore, there is an advantage that the power consumption and the performance of the entire image display device can be reduced and the performance can be improved by reducing the power consumption and the bandwidth of the buffer circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an image display device using a buffer circuit of the present invention.

FIG. 2 is a circuit diagram showing a basic configuration of a buffer circuit according to the present invention.

FIG. 3 is a circuit diagram illustrating the concept of a buffer circuit according to the present invention.

FIG. 4 is a circuit diagram showing a specific example of a buffer circuit according to the present invention.

FIG. 5 is a circuit diagram illustrating a configuration example of a conventional buffer circuit.

FIG. 6 is a circuit diagram showing another configuration example of a conventional buffer circuit.

[Explanation of symbols]

10, 10a buffer circuit, 12 high-pass filter, 14 addition circuit, VS10 voltage source, IS10 current source, Q1, Q2, Q3, Q4, Q5 npn transistor, R1, R2, R3, R4 resistive element , C1 ... capacitor, V _CC ... the power supply voltage, GND ... ground potential.

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 5J091 AA01 AA17 AA45 CA32 CA36 CA62 CA78 FA04 FA10 HA02 HA08 HA19 HA25 HA29 KA05 KA07 KA11 KA26 KA46 KA67 MA01 MA21 SA01 SA08 TA01 TA06 5J092 AA01 AA17 AA02 CA04 CA62 HA08 HA19 HA25 HA29 KA05 KA07 KA11 KA26 KA46 KA67 MA01 MA21 SA01 SA08 TA01 TA06

Claims (6)

[Claims] An input transistor is applied to a control terminal, a current source is connected to an emitter, and an output transistor from which a signal corresponding to the input signal is output from the emitter, an output transistor of a predetermined frequency band of the input signal. And a control signal generation circuit for extracting a signal and controlling a supply current of the current source according to the extracted signal. 2. The control signal generating circuit according to claim 1, further comprising: a voltage source for supplying a predetermined constant voltage; and a high-pass filter circuit for extracting a predetermined high-frequency component of the input signal. 2. The buffer circuit according to claim 1, wherein a sum of a signal and a supply voltage of the voltage source is output as the control signal. 3. The current source according to claim 1, wherein the control signal is input to a control terminal, one terminal is connected to an emitter of the output transistor, and the other terminal is connected to a common potential by a current output transistor. 2. The buffer circuit according to claim 1, wherein the buffer circuit is configured. 4. An image display device for amplifying an input image signal and displaying the amplified signal on a CRT, wherein the buffer circuit receives the input image signal and amplifies the image signal to a predetermined amplitude. An amplifier circuit for amplifying an output signal of the buffer circuit into a large-amplitude signal necessary for display on the CRT and outputting the amplified signal to the CRT, wherein the buffer circuit receives the input image signal at a control terminal. A current source is connected to the emitter, an output transistor from which a signal corresponding to the image signal is output from the emitter, and a signal in a predetermined frequency band of the image signal is extracted, and the current is determined according to the extracted signal. An image display device having a control signal generation circuit for controlling a supply current of a source. 5. The control signal generating circuit has a voltage source for supplying a predetermined constant voltage, and a high-pass filter circuit for extracting a predetermined high-frequency component of the image signal. The image display device according to claim 4, wherein a sum of a signal and a supply voltage of the voltage source is output as the control signal. 6. The current source according to claim 1, wherein the control signal is input to a control terminal, one terminal is connected to an emitter of the output transistor, and the other terminal is connected to a common potential by a current output transistor. The image display device according to claim 4, wherein the image display device is configured.