JP2000216267A - Semiconductor circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the occurrence of leakage currents in a semiconductor circuit device and to improve drivability of the device. SOLUTION: The gate electrode of a second P-channel MOSFET (MP2) for cutting stand-by leakage currents is formed of a non-doped silicon film (non-doped silicon gate), and the gate electrodes of a first P-channel MOSFET (MP1) and an N-channel MOSFET (MN1) constituting an input amplifier are formed of impurity-doped silicon films.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit device, and more particularly to a semiconductor circuit device in which a circuit block operating at a low power supply voltage of 1.5 V or less has a reduced leakage current during standby.

[0002]

2. Description of the Related Art With the spread of portable electronic devices, LS
The power supply voltage of I is being reduced from 3 V to 1.5 V or less in order to reduce current consumption. However, as the power supply voltage decreases, the threshold voltage of the MOSFET also needs to be set lower, which causes a problem of an increase in the leakage current of the LSI during standby.

FIG. 8 shows a PLL circuit for obtaining a signal phase-locked to the oscillation output of the crystal oscillator 1. The output of the crystal oscillator 1 is input to the phase comparator 3 through the input amplifier 2 and compared with the output of the VCO 4 (voltage-controlled oscillator). The output of the phase comparator 3 is smoothed by a low-pass filter 5 to control the oscillation frequency of the VCO 4. During standby of this circuit, the current consumption is reduced by turning off the leak current cutting MOSFET 6 of the input amplifier.

In the above circuit, the power supply voltage is, for example,
When lowering the voltage by 1.5 V, it is necessary to lower the threshold value of the MOSFET. In particular, when the frequency of the crystal oscillator is as high as 200 MHZ or more, the input amplifier 2 must set the threshold value of the MOSFET as low as about 0.3 V in order to improve the frequency characteristics.

[0005]

Therefore, it is conceivable to set the threshold value of the current cutting MOSFET 6 higher than 0.3 V to suppress the leak current. But,
If the threshold value is increased, the current during operation decreases, and the driving capability of the input amplifier 2 becomes insufficient. On the other hand, if the threshold value of the current cutting MOSFET 6 is lowered, the conventional P-channel MOSFET has a problem that the current consumption during standby cannot be sufficiently reduced due to a large leakage current at the time of OFF.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a gate electrode of a P-channel MOSFET for cutting a leakage current of a circuit block at the time of standby is provided with an impurity. It is characterized by being made of an undoped silicon film.

As a circuit block, the above-described PL
An input amplifier (inverter) used for the L circuit is suitable.

In a conventional semiconductor circuit device, a MOS
P-channel MOSFE as gate electrode of FET
For both T-channel and N-channel MOSFETs, a polysilicon film (doped polysilicon) doped with an N-type impurity such as phosphorus at a high concentration of about 1 × 10 20 ^-21 / cm ³ has been used. According to the present invention, the leakage current cut P-channel MOSFET of the circuit block is substantially intrinsic silicon because the gate electrode is not doped with impurities (non-doped).

Therefore, when viewed from the energy band, the energy level of the gate electrode is at the center of the band gap of silicon, and the work function of the gate electrode is different from that of the doped silicon gate by half the band gap voltage. Looking at this from the viewpoint of the threshold voltage of the MOSFET, for the same channel impurity concentration, the non-doped silicon gate MOSFET is about 0.5 V compared to the conventional MOSFET having a gate electrode made of doped polysilicon. Lower. For the same threshold value, the non-doped silicon gate MOSFET has a higher channel impurity concentration and a reduced leakage current.

For this reason, the use of a non-doped silicon gate P-channel MOSFET for cutting the leak current of the circuit block makes it possible to reduce the leak current for the same threshold voltage as compared with the conventional case.
On the other hand, if the leak current value is the same, the threshold value can be further reduced, so that the current driving capability during operation can be increased.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor circuit device according to one embodiment of the present invention will be described with reference to FIGS. This semiconductor circuit is an input amplifier that constitutes the PLL circuit shown in FIG. 8, and the specific configuration is shown in FIG.

The input amplifier is a first P-channel type MOS.
FET (MP1) and N-channel MOSFET (MN
1) is composed of inverters connected in series. The output of the crystal oscillator is applied to this input amplifier. 1st P
A second P-channel MOSFET (MP2) is connected between the channel MOSFET (MP1) and the power supply VCC to cut off a leakage current during standby. The standby signal Φ is applied to the gate of the MOSFET (MP2).
Is applied, the standby signal φ becomes high level at the time of standby, the MOSFET (MP2) is turned off, and the leak current is cut. On the other hand, during operation,
The standby signal Φ goes low and the MOSFET
(MP2) is turned on, and the input amplifier is powered by the power supply VC.
Connected to C. Then, the input amplifier amplifies the output of the crystal oscillator and transmits it to the phase comparator.

A feature of the present invention is that the gate electrode of the second P-channel MOSFET (MP2) is formed of a silicon film not doped with impurities (non-doped silicon gate), and the first P-channel MOSFET (MP2) MP
1) and the N-channel MOSFET (MN1) are formed of a silicon film doped with impurities. The silicon film may be a polysilicon film or an amorphous silicon film.

As will be described in detail below, a non-doped silicon gate P-channel MOSFET has a very small leak current, and therefore operates at a low voltage and a low threshold like the above-described input amplifier. This is effective in reducing the leakage current during standby. On the other hand, if the leak current value is the same, the threshold value can be further reduced, so that the current driving capability during operation can be increased. For example, according to the data of the off-leak current shown in FIG. 4, the threshold value of the non-doped silicon gate P-channel MOSFET can be lowered by about 0.1 V as compared with the conventional one for the same leak current value.

Further, since the input amplifier itself requires a high driving capability, it is preferable to use a doped silicon gate MOSFET having an excellent driving capability.

Next, a non-doped silicon gate P-channel type MOSF constituting the semiconductor circuit device of the present invention.
The transistor characteristics of the ET will be described.

FIG. 2 shows a P-channel type MOSFE having an LDD structure.
It is sectional drawing which shows T. A gate having a polycide structure of a polysilicon film 3 made of non-doped polysilicon and a tungsten silicide film 4 having a thickness of about 1010 mm on an n-type semiconductor substrate or n-well 1 via a gate insulating film 2 having a thickness of about 100 mm. An electrode 5 is formed. Source / drain regions 6 to which p-type impurities are added at about 1E20 cm ⁻³ are formed on the surface of the semiconductor substrate 1. A buried channel doped with a p-type impurity is formed in the channel region 7 between the source and drain regions 6.

FIG. 3 shows the gate length dependence of off-leak current Isd0p of this MOSFET and a doped silicon gate (N + Poly) MOSFET. The gate length refers to the distance between the source and drain regions 6 below the gate electrode,
In other words, it is the length of the channel region in the source / drain region direction. Note that the thickness of the polysilicon film is 1010 °. ○: MOSFET with doped silicon gate, △
And ▲ are MOSFE of non-doped silicon gate
The data of T is shown. Each threshold (MOS
The ON voltage of the FET) is 0.61 V for ○, 0.67 V for Δ, and 0 for ▲.
It is 49V. The threshold can be adjusted by changing the concentration of the buried channel. The phenomenon in which the off-leak current increases as the gate length becomes shorter is a phenomenon generally called a short channel effect. First, by comparing ○ and ▲, the M of the undoped silicon gate
The OSFET has substantially the same off-leakage current value despite the threshold value being about 0.1 V lower. Next, comparing O and Δ, the MOSFET of the present invention has an off-leak current value that is nearly two orders of magnitude smaller only by a threshold of about 0.06 V higher. Thus, a non-doped silicon gate MOSFET
With the same threshold value, the off-leak current can be suppressed smaller than in the conventional case.

Next, FIG. 4 shows the threshold value Vt of the off-leak current.
Indicates ep dependency. Setting a lower threshold increases the off-leakage current, but increases the MO of the undoped silicon gate.
The SFET has an off-leak current value one order of magnitude smaller than that of a conventional MOSFET.

FIG. 5 shows the dependence of the threshold value Vtep on the amount of implanted buried channel ions. The threshold value decreases as the concentration of the buried channel increases. However, for example, when the threshold value is 0.35 V, the implantation amount of the buried channel is 3.0 × 10 ¹² cm ⁻² , which is about 60% of the concentration required for the MOSFET of the doped silicon gate.
Non-doped silicon gate MOSFETs can be used with a doped silicon gate M
It can be set to a threshold value equivalent to that of the OSFET.
Also, for the same channel ion implantation amount, the threshold values of both differ by about 0.5V. Then, the threshold value of the undoped silicon gate MOSFET is set to 0.3V.
Is set to
The threshold value of T is 0.8V.

The relatively small off-leakage current of a non-doped silicon gate P-channel MOSFET is due to the fact that the concentration of the buried channel is low and the depth at which the buried channel is formed is small. It is believed that there is. Since the buried channel and the source and drain regions are regions to which impurities of the same conductivity type are added, the buried channel is basically conductive, and since the concentration of the buried channel is low, the electric resistance is only relatively high.

Therefore, as the concentration of the buried channel increases, the off-leak current increases. Also, as the concentration increases, the depth at which the buried channel is formed also increases, thereby lowering the electric resistance of the buried channel region. Therefore, as the concentration of the buried channel increases, the off-leak current increases. Since a non-doped silicon gate P-channel MOSFET can have the same threshold with a lower buried channel concentration than a doped silicon gate MOSFET,
With the same threshold value, the off-leak current can be suppressed to 1/10.

Next, the thickness of the non-doped polysilicon film 3 will be described. The thickness of the non-doped polysilicon film 3 was 1010 °, 285 °, and 247 °. In the following, samples 1 and 285 having a thickness of 1010 mm
The sample of {circle around (2)} is referred to as Sample 2, and the sample of {247} is referred to as Sample 3.

FIG. 6 shows the dependence of the channel current Ids0 on the gate voltage of a MOSFET of a doped silicon gate (hereinafter referred to as a conventional sample) in which the thickness of the polysilicon film 53 is set to 1010 ° as a comparison object. is there. The channel current of each of the samples 1 to 3 is smaller than the channel current of the conventional sample. Sample 1
The channel current values of Samples 2 and 3 are larger than those of Samples 2 and 3.
Can be said to be good.

FIG. 7 shows the characteristics of a conventional (doped silicon gate MOSFET) and non-doped silicon gate MOSFET when the threshold value (on voltage of the MOSFET) is about 0.65V. The first stage shows the characteristics of sample 1, the second stage shows sample 2, the third stage shows sample 3, and the fourth stage shows the characteristics of the conventional sample. The off-leakage current is 6.40 pA for the conventional MOSFET, which is 0.05 pA to 0.09 pA under each condition, which is about two orders of magnitude smaller, indicating that the off-leakage current is sufficiently suppressed. β is the slope of the channel current value with respect to the gate voltage, and is a value indicating the driving capability of the FET. β is sample 2,
3 shows almost the same value as the conventional one, but sample 1 is slightly lower. This is because the inside of the non-doped silicon gate is depleted, and the thicker the film thickness, the thicker the depletion region.

[0026]

As described above, according to the present invention,
Leakage current during standby of a semiconductor circuit device operating at a low power supply voltage can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor circuit according to an embodiment of the present invention.

FIG. 2 is a sectional view of a non-doped silicon gate MOSFET.

FIG. 3 is a diagram showing a gate length dependency of an off-leak current Isd0p of a MOSFET.

FIG. 4 is a diagram showing the threshold value dependence of off-leak current.

FIG. 5 is a diagram showing the dependence of a threshold value on a buried channel ion implantation dose.

FIG. 6 is a diagram showing a gate voltage dependency of a channel current Ids0.

FIG. 7 is a diagram showing characteristics of a MOSFET.

FIG. 8 is a diagram illustrating a circuit block configuration of a PLL circuit.

Continued on the front page F-term (reference) 4M104 BB01 BB28 BB40 CC05 FF14 GG10 HH20 5F040 DA02 DB03 EC01 EC07 EC13 EE04 EF02 5F048 AA00 AB04 AC03 BA01 BB05 BB06 BB08 BB12 BB15 BC06 BD05 5J056 AA00 BB10 BB18 BB10 BB10

Claims (4)

[Claims] 1. A P-channel MOSFE connected between a circuit block and a power supply connected between the circuit block and a power supply for cutting off a leakage current in a standby state of the circuit block.
T, the MOSFE
A semiconductor circuit device, wherein a gate electrode of T is made of a silicon film not doped with an impurity. 2. An inverter comprising a first P-channel MOSFET and an N-channel MOSFET connected in series, and a second P-channel MOSFET connected between the first P-channel MOSFET and a power supply. MOSFET and
In a semiconductor circuit device in which the second P-channel MOSFET is turned off during standby, the first P-channel MOSFET and the N-channel MOSFET may be turned off.
A semiconductor circuit device, wherein the gate electrode of the ET is made of a silicon film doped with an N-type impurity, and the gate electrode of the second P-channel MOSFET is made of a silicon film not doped with an impurity. 3. The semiconductor circuit device according to claim 2, wherein a threshold value of said second P-channel MOSFET is higher than a threshold value of said first P-channel MOSFET. 4. The semiconductor circuit device according to claim 2, wherein said silicon film is a polysilicon film or an amorphous silicon film.