JP2000209464A - Television receiver - Google Patents

Television receiver

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Publication number
JP2000209464A
JP2000209464A JP11004998A JP499899A JP2000209464A JP 2000209464 A JP2000209464 A JP 2000209464A JP 11004998 A JP11004998 A JP 11004998A JP 499899 A JP499899 A JP 499899A JP 2000209464 A JP2000209464 A JP 2000209464A
Authority
JP
Japan
Prior art keywords
circuit
noise
amount
image quality
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11004998A
Other languages
Japanese (ja)
Inventor
Yoshihiro Kitano
宣裕 北野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11004998A priority Critical patent/JP2000209464A/en
Publication of JP2000209464A publication Critical patent/JP2000209464A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To obtain optimum image quality in response to a noise quantity of a video signal by optimally controlling a gain and a coring amount of an image quality improvement circuit in response to the noise amount of a received video signal and providing a field cyclic type noise reduction circuit to a post- stage of the image quality improvement circuit so as to optimally control its cyclic coefficient depending on the noise amount. SOLUTION: Afield cyclic noise reduction circuit 101 detects a noise amount of a video signal from the A/D converted video signal and the detected noise amount is fed to a microcomputer 106 via an IIC bus 10. The field cyclic noise reduction circuit 101 uses a field memory 102 to detect a motion of each pixel of the video signal. The microcomputer 106 controls the cyclic coefficient of the noise reduction circuit in response to a degree of a motion of each pixel and the noise amount obtained through the IIC bus 10 to be an optimum noise reduction amount through the IIC bus. The video signal whose noise is optimally reduced is given to a plurality of circuits, where the image quality is improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はフィールド巡回型ノ
イズ低減回路の後段に配される画質改善回路として水平
輪郭補正回路,ピーキング回路,垂直輪郭補正回路,速
度変調信号発生回路を有するテレビジョン受像機におい
て入力された映像信号のノイズ量に応じて最適に画質改
善ブロックのゲイン及びコアリング量を制御を行ない,
ノイズ量に応じた最適な画質を提供するテレビジョン受
像機に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver having a horizontal contour correction circuit, a peaking circuit, a vertical contour correction circuit, and a speed modulation signal generation circuit as an image quality improvement circuit disposed downstream of a field cyclic noise reduction circuit. Optimally controls the gain and coring amount of the image quality improvement block according to the amount of noise of the video signal input in
The present invention relates to a television receiver that provides optimal image quality according to the amount of noise.

【0002】[0002]

【従来の技術】従来の技術としては,実開平5ー155
72号公報に記載のように,ノイズ低減回路を通過した
映像信号に対し,輪郭強調効果可変回路がノイズ低減回
路におけるノイズ低減効果とは逆行する輪郭強調効果を
もって輪郭強調効果を施すことにより,ノイズ低減回路
によるノイズ低減効果を大に設定したときは,輪郭強調
を抑制し,逆にノイズ低減回路によるノイズ低減効果を
小に設定したときは輪郭強調の程度を高めることで画質
改善効果を挙げ,ノイズ低減と輪郭強調の相乗効果によ
り適切な画質改善を図るようにしたものがある。
2. Description of the Related Art As a conventional technique, Japanese Utility Model Laid-Open No. 5-155 is used.
As described in Japanese Patent Application Publication No. 72-72, a contour enhancement effect variable circuit applies a contour enhancement effect to a video signal that has passed through a noise reduction circuit with a contour enhancement effect that is opposite to the noise reduction effect of the noise reduction circuit. When the noise reduction effect of the noise reduction circuit is set to a large value, the outline enhancement is suppressed. Conversely, when the noise reduction effect of the noise reduction circuit is set to a small value, the degree of the outline enhancement is increased to improve the image quality. There is an image processing apparatus in which an appropriate image quality is improved by a synergistic effect of noise reduction and edge enhancement.

【0003】また、特開平8ー98058号公報に記載
のように,映像信号中に周期的に配置されている同一の
信号波形間で減算処理を行い差分信号を得,本来値が零
となるべき信号期間に現われる伝送系の付加雑音成分を
測定する雑音測定回路と,雑音測定回路の出力に基づい
て,映像信号に対応する信号の輪郭強調の度合を調節す
る輪郭調整回路を有したものであった。
Further, as described in Japanese Patent Application Laid-Open No. 8-98058, a subtraction process is performed between the same signal waveforms periodically arranged in a video signal to obtain a difference signal, and the original value becomes zero. A noise measuring circuit for measuring an additional noise component of a transmission system appearing in a power signal period, and a contour adjusting circuit for adjusting a degree of contour emphasis of a signal corresponding to a video signal based on an output of the noise measuring circuit. there were.

【0004】[0004]

【発明が解決しようとする課題】しかしながら,前記の
従来の技術はノイズ低減処理を施した後の信号に対して
A/D変換を行ない,輪郭強調回路にて輪郭強調効果可変
回路からの情報により効果量を制御しているものである
が,輪郭強調回路としては垂直輪郭補正回路のみであ
り,水平輪郭補正回路,ピーキング回路,速度変調信号
発生回路に関してはノイズ低減量に応じた制御はなされ
ていなかった。さらに、画質改善回路の前段にフィール
ド巡回型のノイズ低減回路を配したものは無く,フィー
ルド巡回型のノイズ低減回路の巡回係数と画質改善回路
のゲイン及びコアリング量を連動させて総合的な画質改
善効果を得るものは存在しなかった。
However, the above-mentioned conventional technique does not apply to a signal after noise reduction processing.
A / D conversion is performed and the effect level is controlled by the information from the contour emphasis effect variable circuit by the contour emphasis circuit. However, only the vertical contour correction circuit is used as the contour emphasis circuit, and the horizontal contour correction circuit is used. The peaking circuit and the speed modulation signal generating circuit have not been controlled according to the amount of noise reduction. In addition, there is no field recursive noise reduction circuit in front of the image quality improvement circuit, and the overall image quality is linked by linking the cyclic coefficient of the field recursive noise reduction circuit with the gain and coring amount of the image quality improvement circuit. There was no one that improved.

【0005】[0005]

【課題を解決するための手段】本発明は前記課題を解決
するために,入力された映像信号のノイズ量に応じて垂
直輪郭補正回路のみならず水平輪郭補正回路,ピーキン
グ回路,速度変調信号発生回路のゲイン及びコアリング
量を最適に制御すると共に画質改善回路の後段に配され
るフィールド巡回型のノイズ低減回路を有し,その巡回
係数をノイズ量に応じて最適に制御を行なうことによ
り,映像信号のノイズ量に応じた最適な画質を提供でき
る。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides not only a vertical contour correction circuit but also a horizontal contour correction circuit, a peaking circuit, and a speed modulation signal generation circuit according to the amount of noise in an input video signal. By optimally controlling the gain and coring amount of the circuit, and having a field recursive noise reduction circuit arranged downstream of the image quality improving circuit, the cyclic coefficient is optimally controlled according to the noise amount. Optimal image quality can be provided according to the amount of noise in the video signal.

【0006】[0006]

【本発明の実施の形態】本発明における第1の発明は、
A/D変換された映像信号にノイズ低減処理を施した後
に水平輪郭補正回路,ピーキング回路,垂直輪郭補正回
路,速度変調信号発生回路を有するテレビジョン受像機
において,入力される映像信号のノイズ量に応じてこれ
らの回路のゲイン及びコアリング量を最適に制御を行な
うことにより,ノイズ低減と画質改善の両立を図ること
を特徴とするテレビジョン受像機としたもので、映像信
号のノイズ量に応じた最適な画質を提供できる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The first invention of the present invention is as follows.
Noise reduction of an input video signal in a television receiver having a horizontal contour correction circuit, a peaking circuit, a vertical contour correction circuit, and a speed modulation signal generation circuit after subjecting the A / D converted video signal to noise reduction processing A television receiver characterized by achieving both noise reduction and image quality improvement by optimally controlling the gain and coring amount of these circuits according to the Optimum image quality can be provided according to the situation.

【0007】さらに、第2の発明は、画質改善ブロック
の水平輪郭補正回路,ピーキング回路,垂直輪郭補正回
路,速度変調信号発生回路のゲイン及びコアリング量は
IICバスで制御可能であり,ノイズ検出回路により検出
されたノイズ量に応じてマイコンを介し,画質改善ブロ
ックのゲイン及びコアリング量に自動的に補正を加えII
Cバスを通じて最適に制御を行なうことを特徴とするテ
レビジョン受像機としたもので、映像信号のノイズ量に
応じた最適な画質を提供できる。以下,本発明の実施の
形態について,図1から図3を用いて説明する。
Further, according to a second aspect of the present invention, the gain and coring amount of the horizontal contour correction circuit, peaking circuit, vertical contour correction circuit, and velocity modulation signal generation circuit of the image quality improvement block are
It can be controlled by the IIC bus, and automatically corrects the gain and coring amount of the image quality improvement block via a microcomputer according to the amount of noise detected by the noise detection circuit.
This is a television receiver characterized by performing optimal control through the C bus, and can provide an optimal image quality according to the amount of noise of a video signal. Hereinafter, an embodiment of the present invention will be described with reference to FIGS.

【0008】(実施の形態1)図1は本発明の一実施例
におけるノイズ量に応じた画質改善手法のシステム構成
図である。図1において,符号101はフィールド巡回
型ノイズ低減回路,102はフィールド巡回型ノイズ低
減回路用のフィールドメモリー,103は画質改善回
路,104はRGB処理回路,105はCRT,106はマイ
コンを示す。以上のように構成されたノイズ量に応じた
画質改善手法について,以下にその動作を説明する。
(Embodiment 1) FIG. 1 is a system configuration diagram of an image quality improving method according to a noise amount in one embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a field recursive noise reduction circuit, 102 denotes a field memory for the field recursive noise reduction circuit, 103 denotes an image quality improvement circuit, 104 denotes an RGB processing circuit, 105 denotes a CRT, and 106 denotes a microcomputer. The operation of the image quality improving method according to the noise amount configured as described above will be described below.

【0009】図1において,A/D変換された映像信号は
フィールド巡回型ノイズ低減回路101にて映像信号の
ノイズ量の検出が行なわれる。検出されたノイズ量はII
Cバス10を通じてマイコン106に送信される。フィ
ールド巡回型ノイズ低減回路101はフィールドメモリ
ー102を用いて映像信号の各画素に対して動き検出を
行なう。マイコン106はIICバス10を通じて得られ
たノイズ量と各画素の動き度合に応じてノイズ低減回路
の巡回係数をIICバス11を通じて最適なノイズ低減量
となるように制御する。
In FIG. 1, an A / D-converted video signal is subjected to a field recursive noise reduction circuit 101 to detect the amount of noise in the video signal. The detected noise amount is II
It is transmitted to the microcomputer 106 through the C bus 10. The field recursive noise reduction circuit 101 uses the field memory 102 to perform motion detection on each pixel of the video signal. The microcomputer 106 controls the cyclic coefficient of the noise reduction circuit through the IIC bus 11 so that the optimal noise reduction amount is obtained according to the noise amount obtained through the IIC bus 10 and the degree of motion of each pixel.

【0010】最適にノイズ低減された映像信号は画質改
善回路103にて水平輪郭補正回路,ピーキング回路,
垂直輪郭補正回路,速度変調信号発生回路にて画質改善
処理が施される。さらに、映像信号の垂直ブランキング
期間のノイズ量の検出を行ない,検出されたノイズ量は
IICバス12を通じてマイコン106に送信される。マ
イコン106はIICバス12から送信されたノイズ量に
応じて内部でプログラムされた一定の計算式に従い,水
平輪郭補正回路,ピーキング回路,垂直輪郭補正回路,
速度変調信号発生回路の各ゲイン及びコアリング量を算
出する。
The video signal whose noise has been optimally reduced is subjected to a horizontal contour correction circuit, a peaking circuit,
Image quality improvement processing is performed by a vertical contour correction circuit and a speed modulation signal generation circuit. Further, the amount of noise during the vertical blanking period of the video signal is detected.
It is transmitted to the microcomputer 106 through the IIC bus 12. The microcomputer 106 calculates the horizontal contour correction circuit, the peaking circuit, the vertical contour correction circuit, and the like according to a constant calculation formula programmed internally according to the amount of noise transmitted from the IIC bus 12.
Each gain and coring amount of the speed modulation signal generation circuit are calculated.

【0011】算出された各回路のゲイン及びコアリング
量はIICバス13を通じて画質改善回路103に送信さ
れノイズ量に応じた最適な画質制御が施される。さら
に、映像信号は画質改善回路103でD/A変換される。
RGB処理回路104にてRGB原色信号に変換され,CRT1
05にてCRT上に表示される。速度変調信号発生回路に
より生成された速度変調信号は画質改善回路103にて
D/A変換され, CRT105の速度変調コイルに伝えられ
ノイズ量に応じた最適な速度変調効果が得られる。
The calculated gain and coring amount of each circuit are transmitted to the image quality improvement circuit 103 through the IIC bus 13 and are subjected to optimal image quality control according to the amount of noise. Further, the video signal is D / A converted by the image quality improvement circuit 103.
The signal is converted to an RGB primary color signal by the RGB
Displayed on the CRT at 05. The speed modulation signal generated by the speed modulation signal generation circuit is processed by the image quality improvement circuit 103.
The D / A conversion is performed and transmitted to the speed modulation coil of the CRT 105 to obtain an optimum speed modulation effect according to the noise amount.

【0012】(実施の形態2)本発明における画質改善
回路ブロックにおけるブロック構成及びその制御の流れ
についての一実施例について図2を用いて説明する。
(Embodiment 2) An embodiment of a block configuration and a control flow in an image quality improvement circuit block according to the present invention will be described with reference to FIG.

【0013】図2において画質改善回路は垂直輪郭補正
回路21,垂直輪郭補正信号を得るためのラインメモリ
ー201及び202,水平輪郭補正回路21,ピーキン
グ回路22,速度変調信号発生回路23, D/A変換器
213及び214,ノイズ検出回路24で構成されてい
る。
In FIG. 2, an image quality improving circuit includes a vertical contour correcting circuit 21, line memories 201 and 202 for obtaining a vertical contour correcting signal, a horizontal contour correcting circuit 21, a peaking circuit 22, a speed modulation signal generating circuit 23, and a D / A. It comprises converters 213 and 214 and a noise detection circuit 24.

【0014】画質改善回路に入力された映像信号は,ノ
イズ検出回路24にて映像信号の高周波成分だけをハイ
パスフィルタ218で取り出され,垂直ブランキング期
間ノイズ検出回路219でノイズ量が測定される。測定
されたノイズ量はIICバス25によりマイコンに送信さ
れる。これとは別に映像信号は,垂直輪郭補正回路20
にてラインメモリー201及び202を用い,各々のラ
インにローパスフィルター203,204,205を施
し,低周波成分だけを取り出し,さらに各々を加算して
コアリング処理206を施される。
From the video signal input to the image quality improving circuit, only the high frequency component of the video signal is extracted by the noise detection circuit 24 by the high-pass filter 218, and the noise amount is measured by the vertical blanking period noise detection circuit 219. The measured noise amount is transmitted to the microcomputer via the IIC bus 25. Separately, the video signal is supplied to a vertical contour correction circuit 20.
The line memories 201 and 202 are used to apply low-pass filters 203, 204, and 205 to each line, to extract only low-frequency components, and to add them to perform coring processing 206.

【0015】垂直輪郭補正回路を通過した映像信号は,
水平輪郭補正回路21にて一次微分回路207にて一次
微分され,コアリング回路208,ゲイン調整回路20
9の処理が施される。ピーキング回路22は二次微分回
路210で二次微分されコアリング回路211,ゲイン
調整回路212の処理が施され,両者が加算器にて加算
され,さらに映像信号に加算され輪郭強調された信号が
D/A変換器213にてアナログ信号に変換される。水平
輪郭補正回路及びピーキング回路を通過した信号は,速
度変調信号発生回路23にて,一次微分回路214にて
一次微分され,ゲイン調整回路215,コアリング回路
216でゲイン及びコアリング量が補正されD/A変換器
217にてアナログ信号に変換される。
The video signal that has passed through the vertical contour correction circuit is
First-order differentiation is performed by the first-order differentiating circuit 207 in the horizontal contour correction circuit 21, and the coring circuit 208 and the gain adjusting circuit 20 are used.
9 are performed. The peaking circuit 22 is secondarily differentiated by the second differentiating circuit 210, subjected to the processing of the coring circuit 211 and the gain adjusting circuit 212, added by the adder, and further added to the video signal to obtain a signal whose outline is emphasized.
The signal is converted into an analog signal by the D / A converter 213. The signal that has passed through the horizontal contour correction circuit and the peaking circuit is first-order differentiated by a first-order differentiation circuit 214 by a velocity modulation signal generation circuit 23, and gain and coring amount are corrected by a gain adjustment circuit 215 and a coring circuit 216. The signal is converted into an analog signal by the D / A converter 217.

【0016】垂直輪郭補正回路23のコアリング回路2
06及び水平輪郭補正回路21のコアリング回路20
8,ゲイン調整回路20及びピーキング回路22のコア
リング回路211,ゲイン調整回路212及び速度変調
信号発生回路のゲイン調整回路215,コアリング回路
216はIICバス26によりマイコンから制御される。
The coring circuit 2 of the vertical contour correction circuit 23
06 and coring circuit 20 of horizontal contour correction circuit 21
8, the coring circuit 211 of the gain adjustment circuit 20 and the peaking circuit 22, the gain adjustment circuit 212, the gain adjustment circuit 215 of the speed modulation signal generation circuit, and the coring circuit 216 are controlled by the microcomputer via the IIC bus 26.

【0017】(実施の形態3)本発明における画質改善
回路の各コアリング回路及びゲイン調整回路のノイズ量
に応じた制御方法についての一実施例について図3を用
いて説明する。図3においてNOIは画質改善回路のノイ
ズ検出回路よりIICバスにより送信されてきたノイズ量
のデータである。
(Embodiment 3) An embodiment of a control method according to the noise amount of each coring circuit and gain adjustment circuit of the image quality improvement circuit according to the present invention will be described with reference to FIG. In FIG. 3, NOI is data of the amount of noise transmitted from the noise detection circuit of the image quality improvement circuit via the IIC bus.

【0018】各回路のコアリング量の制御は図3に示す
通り,制御式Fkで算出される。制御式の中のパラメータ
A,B,Cは各回路に対して各々独立に設定可能となって
いる。入力信号のノイズレベルが極めて良い場合には,
NOIは零となるので計算式のCの値がコアリング量として
各回路に送信される。入力信号のノイズレベルが徐々に
悪くなってくるとNOIの値は大きくなり,NOIにB/Aを乗
じた値にCを加えた値がコアリング量として各回路に送
信される。こうすることにより入力信号のノイズ量に応
じてコアリング量を連続的に変化させることによりノイ
ズの強調を抑制することが可能となる。
The control of the coring amount of each circuit is calculated by a control formula Fk as shown in FIG. Parameters in control expressions
A, B, and C can be set independently for each circuit. If the noise level of the input signal is very good,
Since NOI becomes zero, the value of C in the calculation formula is transmitted to each circuit as a coring amount. When the noise level of the input signal gradually deteriorates, the value of NOI increases, and a value obtained by adding C to a value obtained by multiplying NO / B / A is transmitted to each circuit as a coring amount. This makes it possible to suppress noise enhancement by continuously changing the coring amount according to the noise amount of the input signal.

【0019】次に各回路のゲイン制御については図3に
示す通り,制御式Fgで算出される。制御式の中のパラメ
ータA,B,C,Dは各回路に対して各々独立に設定可能と
なっている。但し,NOIが零の時には制御式Fgの値が無
限大になってしまうため,この時にはNOIを1としてい
る。入力信号のノイズレベルが徐々に悪くなるにつれて
制御式Fgの分母の値が大きくなりゲイン量がノイズの増
加と共に連続的に減少していく。前記コアリング量とゲ
イン量が入力された映像信号のノイズ量に応じて連続的
に変化することによりノイズに対して常に最適な制御が
可能である。
Next, the gain control of each circuit is calculated by the control formula Fg as shown in FIG. Parameters A, B, C, and D in the control formula can be set independently for each circuit. However, when the NOI is zero, the value of the control formula Fg becomes infinite, so the NOI is set to 1 at this time. As the noise level of the input signal gradually deteriorates, the value of the denominator of the control formula Fg increases, and the gain amount continuously decreases as the noise increases. By continuously changing the coring amount and the gain amount according to the noise amount of the input video signal, it is possible to always optimally control the noise.

【0020】[0020]

【発明の効果】以上のように本発明のテレビジョン受像
機の画質改善手法によれば,入力された映像信号のノイ
ズ量に応じた最適な画質の提供が可能となる。
As described above, according to the image quality improving method of the television receiver of the present invention, it is possible to provide the optimum image quality according to the noise amount of the input video signal.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例におけるノイズ量に応じた画
質改善手法のシステム構成図
FIG. 1 is a system configuration diagram of an image quality improvement method according to a noise amount according to an embodiment of the present invention.

【図2】本発明の一実施例における画質改善回路ブロッ
クにおけるブロック構成図
FIG. 2 is a block diagram of an image quality improvement circuit block according to an embodiment of the present invention.

【図3】本発明における画質改善回路の各コアリング回
路及びゲイン調整回路のノイズ量に応じた制御方法の一
例の図
FIG. 3 is a diagram illustrating an example of a control method according to a noise amount of each coring circuit and a gain adjustment circuit of the image quality improvement circuit according to the present invention.

【符号の説明】[Explanation of symbols]

10,11,12,13 IICバス 101 フィールド巡回型ノイズ低減回路 102 フィールドメモリー 103 画質改善回路 104 RGB処理回路 105 CRT 106 マイコン 20 垂直輪郭補正回路 21 水平輪郭補正回路 22 ピーキング回路 23 速度変調信号発生回路 24 ノイズ検出回路 25,26 IICバス 201 ラインメモリー 202 ラインメモリー 203,204,205 ローパスフィルター 206 垂直輪郭補正回路のコアリング回路 207 水平輪郭補正回路の一次微分回路 208 水平輪郭補正回路のコアリング回路 209 水平輪郭補正回路のゲイン調整回路 210 ピーキング回路の二次微分回路 211 ピーキング回路のコアリング回路 212 ピーキング回路のゲイン調整回路 213 映像信号用D/A変換器 214 速度変調信号発生回路の一次微分回路 215 速度変調信号発生回路のゲイン調整回路 216 速度変調信号発生回路のコアリング回路 217 速度変調信号発生回路用D/A変換器 218 ノイズ検出回路のハイパスフィルター 219 ノイズ検出回路の垂直ブランキング期間ノイズ
検出回路
10, 11, 12, 13 IIC bus 101 Field cyclic noise reduction circuit 102 Field memory 103 Image quality improvement circuit 104 RGB processing circuit 105 CRT 106 Microcomputer 20 Vertical contour correction circuit 21 Horizontal contour correction circuit 22 Peaking circuit 23 Speed modulation signal generation circuit Reference Signs List 24 Noise detection circuit 25, 26 IIC bus 201 Line memory 202 Line memory 203, 204, 205 Low pass filter 206 Coring circuit of vertical contour correction circuit 207 First derivative circuit of horizontal contour correction circuit 208 Coring circuit of horizontal contour correction circuit 209 Gain adjustment circuit of horizontal contour correction circuit 210 Secondary differentiation circuit of peaking circuit 211 Coring circuit of peaking circuit 212 Gain adjustment circuit of peaking circuit 213 D / A converter for video signal 214 Speed change Primary differentiation circuit of signal generation circuit 215 Gain adjustment circuit of speed modulation signal generation circuit 216 Coring circuit of speed modulation signal generation circuit 217 D / A converter for speed modulation signal generation circuit 218 High-pass filter of noise detection circuit 219 Noise detection circuit Vertical blanking period noise detection circuit

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 ノイズ低減回路の後に画質改善回路を有
するテレビジョン受像機において,これらの回路のゲイ
ン及びコアリング量を最適に制御することを特徴とする
テレビジョン受像機。
1. A television receiver having an image quality improvement circuit after a noise reduction circuit, wherein the gain and coring amount of these circuits are optimally controlled.
【請求項2】 A/D変換された映像信号にノイズ低減
処理を施した後に水平輪郭補正回路,ピーキング回路,
垂直輪郭補正回路,速度変調信号発生回路を有するテレ
ビジョン受像機において,入力される映像信号のノイズ
量に応じてこれらの回路のゲイン及びコアリング量を最
適に制御を行なうことにより,ノイズ低減と画質改善の
両立を図ることを特徴とするテレビジョン受像機。
2. A horizontal contour correction circuit, a peaking circuit, after performing a noise reduction process on an A / D converted video signal.
In a television receiver having a vertical contour correction circuit and a velocity modulation signal generation circuit, noise reduction and noise reduction can be achieved by optimally controlling the gain and coring amount of these circuits in accordance with the amount of noise in the input video signal. A television receiver characterized by improving image quality.
【請求項3】 入力された映像信号の画質改善回路の前
段にフィールド巡回型ノイズ低減回路を有し,ノイズ量
に応じて最適に巡回係数の制御を行ない,最適なノイズ
低減を図ることを特徴とするテレビジョン受像機。
3. A noise reduction circuit having a field recursive noise reduction circuit preceding the image quality improvement circuit for an input video signal, wherein a recursive coefficient is optimally controlled according to the amount of noise to achieve optimal noise reduction. Television receiver.
【請求項4】 入力された映像信号の画質改善回路での
ノイズ量の検出手段として垂直ブランキング期間のノイ
ズ量を検出するノイズ検出回路を有し,そのノイズ量を
IICバスを通じてマイコンに入力する回路を有すること
を特徴とするテレビジョン受像機。
4. A noise detecting circuit for detecting an amount of noise in a vertical blanking period as means for detecting an amount of noise in an image quality improving circuit of an input video signal, wherein the amount of noise is detected.
A television receiver having a circuit for inputting data to a microcomputer through an IIC bus.
【請求項5】 画質改善ブロックの水平輪郭補正回路,
ピーキング回路,垂直輪郭補正回路,速度変調信号発生
回路のゲイン及びコアリング量はIICバスで制御可能で
あり,ノイズ検出回路により検出されたノイズ量に応じ
てマイコンを介し,画質改善ブロックのゲイン及びコア
リング量に自動的に補正を加えIICバスを通じて最適に
制御を行なうことを特徴とするテレビジョン受像機。
5. A horizontal contour correction circuit for an image quality improvement block,
The gain and coring amount of the peaking circuit, vertical contour correction circuit, and velocity modulation signal generation circuit can be controlled by the IIC bus. The gain and the quality of the image quality improvement block are controlled via the microcomputer according to the noise amount detected by the noise detection circuit. A television receiver characterized by automatically correcting the coring amount and performing optimal control over the IIC bus.
JP11004998A 1999-01-12 1999-01-12 Television receiver Pending JP2000209464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11004998A JP2000209464A (en) 1999-01-12 1999-01-12 Television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11004998A JP2000209464A (en) 1999-01-12 1999-01-12 Television receiver

Publications (1)

Publication Number Publication Date
JP2000209464A true JP2000209464A (en) 2000-07-28

Family

ID=11599271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11004998A Pending JP2000209464A (en) 1999-01-12 1999-01-12 Television receiver

Country Status (1)

Country Link
JP (1) JP2000209464A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100735918B1 (en) 2004-12-22 2007-07-06 삼성전자주식회사 Display apparatus and method of processing image thereof
KR100762148B1 (en) * 2006-06-01 2007-10-02 엘지전자 주식회사 Method and apparatus for adjusting detail and sharpness by motion measurement
JP2012010046A (en) * 2010-06-24 2012-01-12 Sharp Corp Image quality improving device and method thereof
JP2012244436A (en) * 2011-05-19 2012-12-10 Toshiba Corp Video processing device and edge enhancement method
CN108600606A (en) * 2017-03-01 2018-09-28 佳能株式会社 The control method of image processing equipment and image processing equipment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100735918B1 (en) 2004-12-22 2007-07-06 삼성전자주식회사 Display apparatus and method of processing image thereof
KR100762148B1 (en) * 2006-06-01 2007-10-02 엘지전자 주식회사 Method and apparatus for adjusting detail and sharpness by motion measurement
JP2012010046A (en) * 2010-06-24 2012-01-12 Sharp Corp Image quality improving device and method thereof
JP2012244436A (en) * 2011-05-19 2012-12-10 Toshiba Corp Video processing device and edge enhancement method
CN108600606A (en) * 2017-03-01 2018-09-28 佳能株式会社 The control method of image processing equipment and image processing equipment
CN108600606B (en) * 2017-03-01 2021-01-12 佳能株式会社 Image processing apparatus and control method of image processing apparatus

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