JP2000209459A - Television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize synchronization even when a general purpose video display circuit is used in a television receiver for being loaded on a mobile object. SOLUTION: A synchronization separator circuit 5 outputs composite synchronizing signals 6 by performing synchronizing separation from video signals 4. A synchronization stabilizing circuit 7 outputs synchronization stabilizing signals 22 for which the composite synchronizing signals 6 are corrected for generating disturbance at the time of mobile reception. A stabilized synchronization superimposing circuit 23 supplies stabilized synchronization superimposed video signals 24 for which the synchronization stabilizing signals are superimposed on the video signals 4 to a video display circuit 25. The synchronization stabilizing signals are reproduced by synchronization separating the stabilized synchronization superimposed video signals 24 in the video display circuit 25 and video images without synchronization disturbance are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver suitable for mounting on a moving body such as a vehicle.

[0002]

2. Description of the Related Art In recent years, small and light-weight, high-performance television receivers have been developed, and are increasingly used for mobile devices such as vehicles. However, when the television receiver is used in a mobile object, fading accompanying the movement occurs, and the image is severely disturbed. In order to reduce the image disturbance due to such fading, a spatial diversity device that utilizes the fact that a received wave close to uncorrelated is obtained by spatially separating a plurality of antennas sufficiently is used. Although the use of a space diversity device is effective in improving received video quality, depending on the area where the vehicle is traveling, the received waves from all diversity antennas may receive similarly degraded video. May not contribute to the improvement of the image quality.

[0003] Further, in the case where there is a reflecting object such as a building in the propagation path, the reflected wave causes reception of a radio wave in which waves having different propagation delay times are multiplexed. The ghost image becomes a multiple ghost image, and the propagation delay time fluctuates when moving. Therefore, a ghost flutter phenomenon in which the ghost image appears to be swung right and left occurs. Such a decrease in the electric field or the presence of the multiplex wave causes disturbance of video synchronization and further lowers the video quality.

As countermeasures against such disturbance of synchronization, those described in JP-A-5-115015 and JP-A-6-78230 are known. These are provided with a synchronization stabilization circuit for stabilizing vertical and horizontal synchronization signals synchronized and separated from the video signal, thereby stabilizing the synchronization of the received video.

FIG. 10 shows a mobile-equipped television receiver having a conventional synchronization stabilizing function.
The operation will be described with reference to FIG. Antenna 80 induces high frequency signal 81. The TV tuner 82 outputs the high-frequency signal 8
1. The high frequency signal of the TV channel to be received from 1 is selectively tuned and converted into an intermediate frequency signal. Then, the converted intermediate frequency signal is detected to extract a video signal 83. The synchronization separation circuit 84 separates a composite synchronization signal 85 including horizontal synchronization and vertical synchronization from the video signal 83. The synchronization stabilization circuit 86 supplies a synchronization stabilization signal 87 in which the disturbance of the composite synchronization signal 85 has been corrected to the video display circuit 88. The video display circuit 88 receives the video signal 83 and the synchronization stabilization signal 8
7 to reproduce and display the video. With the television receiver mounted on a mobile body configured as described above, it is possible to obtain an image without disturbance of the synchronization signal.

[0006]

However, in the above-mentioned conventional television receiver mounted on a mobile body, the video display circuit 8 is not provided.
8, it is necessary to input the synchronization stabilization signal 87 in a form separated from the video signal 83. Therefore, as a form of the mobile-equipped television receiver, a TV tuner 82,
In some cases, the housing of the video display circuit 88 is separated, and in such a case, it is necessary to increase the number of wires included in a cable connecting the respective housings. In addition, there is a problem that a general-purpose video display circuit that does not consider the mounting of a moving object cannot be used as the video display circuit.

[0007] The present invention solves the above-mentioned conventional problems, and is suitable for mounting on a moving body in which a general-purpose video display circuit can be used as it is in a form in which a TV tuner and a housing of a video display circuit are separated. It is an object of the present invention to provide a simple television receiver.

[0008]

SUMMARY OF THE INVENTION In order to solve this problem, the present invention provides a synchronous stabilizing signal superimposing circuit for superimposing a synchronous stabilizing signal in which a disturbance of a synchronous signal has been corrected in a synchronous stabilizing circuit into a video signal. Used. This eliminates the need to separate the synchronization stabilization signal from the video signal and supply it to the video display circuit. In this manner, in a form in which the tuner circuit and the casing of the video display circuit are separated,
A general-purpose video display circuit can be used as it is.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a TV tuner for outputting a video signal detected from a reception signal obtained by an antenna, and a vertical synchronization signal and a horizontal synchronization signal mixed from the video signal. A sync separation circuit for separating the composite sync signal, a sync stabilization circuit for correcting the disturbance of the sync signal, a stabilizing sync superimposing circuit for superimposing the output of the sync stabilizing circuit on the video signal, and a stabilizing sync superimposing. And a video display circuit that reproduces video based on the output of the circuit. A synchronization stabilization signal in which the disturbance has been corrected is generated. Further, even in a separate type television device in which the tuner housing and the housing of the video display circuit are separated from each other and connected by a cable or wirelessly, a synchronization signal superimposing circuit that superimposes a synchronization stabilization signal on a video signal is provided. There is no need to separate the stabilized synchronizing signal from the video signal and supply it to the video display circuit. As a result, even if a general-purpose video display circuit having no input of the synchronization stabilization synchronization signal is used, a stable image without disturbance of the synchronization signal can be obtained.

According to a second aspect of the present invention, in the television receiver according to the first aspect, a reference clock oscillator that oscillates at a frequency that is an integral multiple of the horizontal synchronization frequency and an output of the reference clock oscillator are divided. A frequency divider circuit for outputting a horizontal synchronization stabilization signal having a cycle substantially equal to the horizontal synchronization signal, detecting a phase shift direction of the horizontal synchronization signal with respect to the horizontal synchronization stabilization signal, and checking whether the phase shift is within a predetermined range. A phase difference detection circuit that detects whether or not the phase synchronization signal is detected and outputs the detected value as a phase coincidence detection signal, a phase control cycle counter that counts the vertical synchronization signal and outputs a counter value of a predetermined field cycle, and a phase shift detection result. A frequency division number control circuit for increasing or decreasing the frequency division number of the frequency division circuit; and a phase division detection signal and an output of the phase control cycle counter for a predetermined number of fields. And a reset control circuit that outputs a horizontal synchronization signal to the frequency dividing circuit as a reset signal when the coincidence is not detected, and makes the phase of the horizontal synchronization stabilization signal coincide with the horizontal synchronization signal. It has the function of generating a horizontal synchronization stabilizing signal in which the synchronization disturbance is corrected, even when the reception electric field condition is deteriorated during mobile reception and the horizontal synchronization signal is disturbed.

According to a third aspect of the present invention, in the television receiver according to the first aspect, a voltage-controlled oscillator capable of changing an oscillation frequency by a control voltage, and a frequency-divided output of the voltage-controlled oscillator for horizontal scanning. A frequency divider that outputs a horizontal synchronization stabilization signal having a cycle substantially equal to the synchronization signal, and a phase difference detection circuit that outputs a positive / negative voltage value according to the direction and amount of phase deviation of the horizontal synchronization signal with respect to the horizontal synchronization stabilization signal And a synchronizing and stabilizing circuit including an integrating circuit for averaging the output of the phase difference detecting circuit and using the output as a control voltage of the voltage-controlled oscillator. Even when the synchronizing signal is disturbed, there is an effect that a horizontal synchronizing stabilization signal in which the disturbed synchronizing signal is corrected is generated.

According to a fourth aspect of the present invention, there is provided the television receiver according to the first aspect, wherein the output of the reference clock oscillator is frequency-divided to thereby obtain a vertical synchronization stabilizing signal having a period substantially equal to the vertical synchronization signal. A vertical frequency divider that outputs
Detects phase coincidence with the supplied vertical synchronizing signal and the vertical synchronizing stabilization signal, and resets the vertical synchronizing signal to the vertical frequency dividing circuit when there is no continuous phase coincidence over a predetermined number of fields. It is characterized by having a synchronization stabilization circuit including a vertical synchronization control circuit that matches the phases of the vertical synchronization signal and the vertical synchronization stabilization signal by outputting the signal as a signal. Even if the vertical synchronizing signal is disturbed due to deterioration, a vertical synchronizing stabilizing signal in which the synchronizing disturbance is corrected is generated.

According to a fifth aspect of the present invention, in the television receiver according to the first aspect, the polarities of the video signal and the composite synchronization signal are matched, and the amplitude level of the composite synchronization signal is set to a predetermined level. A stabilizing synchronous superimposing circuit comprising: a synchronizing pulse adjusting circuit for adjusting the output of the synchronizing pulse adjusting circuit and the video signal; and an amplifier circuit for setting the amplitude level of the adding circuit to a predetermined level. The synchronization signal for superimposing the synchronization stabilization signal on the video signal even in the case of a separate type television device in which the tuner housing and the video display circuit housing are separated and connected by a cable or wirelessly. The superimposition circuit eliminates the need to separate the stabilized synchronizing signal from the video signal and supply it to the video display circuit. As a result, even if a general-purpose video display circuit having no input of the synchronization stabilization synchronization signal is used, a stable image without disturbance of the synchronization signal can be obtained.

According to a sixth aspect of the present invention, in the television receiver according to the first aspect, the polarities of the video signal and the composite synchronization signal are matched, and the amplitude level of the composite synchronization signal is set to a predetermined level. Synchronous pulse adjusting circuit, a synchronous pulse adjusting circuit for adjusting an output pulse of the synchronous pulse adjusting circuit, an adding circuit for adding the output of the synchronous pulse adjusting circuit and the video signal, and setting the amplitude level of the adding circuit to a predetermined level. It is characterized by having a stabilized synchronous superimposing circuit provided with an amplifier circuit, and a separate type television device in which a tuner housing and a video display circuit housing are separated and connected by a cable or wirelessly. Even if there is a synchronization signal superimposed on the video signal, the synchronization signal superimposition circuit separates the stabilized synchronization signal from the video signal and supplies it to the video display circuit. That it is no longer necessary. As a result, even if a general-purpose video display circuit having no input of the synchronization stabilization synchronization signal is used, a stable image without disturbance of the synchronization signal can be obtained.

According to a seventh aspect of the present invention, in the television receiver according to the sixth aspect, a cutting pulse is inserted before and after a synchronization pulse to perform pulse processing, and a video signal and a synchronization pulse signal are superimposed. At this time, the influence of the synchronization pulse in the video signal can be reduced, and the pulse of the stabilized synchronization signal can be emphasized, so that the synchronization pulse is reliably separated.

According to an eighth aspect of the present invention, a plurality of antennas, an antenna switching circuit for selecting one of the plurality of antennas, and detection from a received signal obtained by the antenna selected by the antenna switching circuit. A TV tuner for outputting a converted video signal, a synchronization separation circuit for separating a composite synchronization signal in which a vertical synchronization signal and a horizontal synchronization signal are mixed from the video signal, a synchronization stabilization circuit for correcting disturbance of the composite synchronization signal, A stabilizing synchronous superimposing circuit for superimposing an output of a synchronizing stabilizing circuit on the video signal, and detecting and optimizing reception quality of an antenna connected to the TV tuner from the stabilized synchronizing superimposed video signal from the stabilizing synchronous superimposing circuit. Selects an antenna, generates an antenna switching timing signal based on the stabilized synchronous superimposed video signal, and controls antenna switching by an antenna switching circuit. And a video display circuit that reproduces a video by outputting a stabilized synchronized superimposed video signal, and is already integrated as a reception status detection / antenna control circuit. An antenna switching circuit connected to a tuner when a component is used; detecting a reception quality of an antenna connected to the TV tuner from a stabilized synchronized superimposed video signal to select an optimum antenna; Since the synchronization separation circuit is integrated based on the antenna, even if the input is only a video signal, the synchronization stabilization signal is separated by using the stabilized synchronization superimposed video signal as input. Has the effect that stable operation is achieved.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

(Embodiment 1) FIG. 1 shows a mobile receiving television receiver according to a first embodiment of the present invention.
This will be described below with reference to FIG. The antenna 1 induces a high-frequency signal 2. The TV tuner 3 selectively tunes a high frequency signal of a TV channel to be received from the high frequency signal 2 and converts it into an intermediate frequency signal. Then, the converted intermediate frequency signal is detected to extract the video signal 4.
The synchronization separation circuit 5 separates a composite synchronization signal 6 including horizontal and vertical synchronization from the video signal 4 and supplies the composite synchronization signal 6 to a synchronization stabilization circuit 7. The synchronization stabilization circuit 7 creates a synchronization stabilization signal 22 based on the composite synchronization signal 6 as described later. The synchronization stabilization signal 22 is superimposed on the video signal 4 by the stabilization synchronization superimposition circuit 23 and supplied to the video display circuit 25.

FIG. 2 shows the horizontal synchronization section 7 of the synchronization stabilization circuit 7.
It is a figure showing composition of a. In FIG. 2, the composite sync signal 6 is supplied to a horizontal / vertical sync separation circuit 8. The horizontal / vertical sync separation circuit 8 converts the composite sync signal 6 into a horizontal sync signal 9
And a circuit that separates and outputs the two by utilizing the difference in frequency between the vertical synchronization signal 10 and the vertical synchronization signal 10.

On the other hand, a reference clock oscillator 11 is an oscillator for generating a reference clock signal 12 having a frequency f0.
It is obtained by exciting a highly stable crystal oscillator. NTS
In the case of the C system, there is a relationship of (Equation 1) and (Equation 2) between the color subcarrier frequency fsc, the horizontal synchronization frequency fh, and the vertical synchronization frequency fv.

Fsc = 910fh / 4 (Equation 1) fh = 525fv / 2 (Equation 2) Therefore, for example, when a crystal resonator having an oscillation frequency 4fsc four times the color subcarrier frequency fsc is used, the horizontal synchronization frequency fh On the other hand, an integer multiple of 4fsc = 910fh holds, and a signal equal to the horizontal synchronization period can be obtained by dividing the reference clock signal 12 by 910.

The frequency divider 13 has a frequency division number that satisfies the integer multiple of the frequency relationship between the reference clock signal 12 and the horizontal synchronization signal 9 as described above. , The horizontal synchronization stabilizing signal 14 having a cycle substantially equal to the horizontal synchronization signal 9 is output.

The phase difference detecting circuit 15 detects the direction of the phase shift between the horizontal synchronizing signal 9 and the horizontal synchronizing stabilization signal 14, outputs the detected value as a phase shift direction detecting signal 16, and detects the phase shift. It is detected whether it is within the range, and the detection result is output as a phase coincidence detection signal 17. The phase control cycle counter 18 counts the vertical synchronization signal 10,
Output the counter value.

The frequency division number control circuit 19 changes the frequency division number of the frequency division circuit 19 in a predetermined field cycle based on the phase shift detection result by the phase shift direction detection signal 16 for each predetermined field cycle. Control is performed to correct the frequency error df of the crystal resonator used as the reference clock.

The reset control circuit 20 judges from the counter value of the phase control cycle counter 18 and, if the detection result of the supplied phase coincidence detection signal 17 is a predetermined non-predetermined phase difference over a predetermined number of fields, is supplied. The horizontal synchronizing signal 9 is output as a reset signal 21 to the frequency dividing circuit 19 for a predetermined time. When the reset signal 21 is supplied, the frequency dividing circuit 13 resets the frequency dividing operation and the horizontal synchronizing signal 9
And the horizontal synchronizing stabilization signal 14 is in phase.

FIG. 3 shows the vertical synchronization section 7 of the synchronization stabilization circuit 7.
It is a figure showing composition of b. In FIG. 3, the vertical frequency dividing circuit 30 divides the supplied reference clock signal 12 from the reference clock oscillator 11 to generate a vertical synchronization stabilizing signal 31 oscillating at a cycle substantially equal to the vertical synchronization. It is supplied to the vertical phase control circuit 32. (Equation 2)
In the case where a signal twice as high as the horizontal synchronization frequency is obtained from the frequency divider 13 using the relationship, the vertical synchronization stabilization signal 31 can also be obtained by dividing the signal by 525. The vertical phase control circuit 32 detects a phase difference between the supplied vertical synchronization signal 10 and the supplied vertical synchronization stabilization signal 31. If the phase difference is not continuously within the predetermined phase difference over a predetermined field, the vertical synchronization signal By supplying 10 to the vertical frequency dividing circuit 30 as a vertical reset pulse signal 33, the phases of the vertical synchronization signal 10 and the vertical synchronization stabilization signal 31 are made to coincide.

The horizontal synchronization stabilization signal 14 and the vertical synchronization stabilization signal 31 obtained as described above from the synchronization stabilization circuit 7 in FIG. 1 are converted into a composite synchronization stabilization signal 22 as shown in FIG. It is supplied to the stabilizing synchronous superimposing circuit 23. In this case, the same effect can be obtained even if the horizontal synchronization stabilization signal 14 and the vertical synchronization stabilization signal 31 are supplied to the stabilization synchronization superimposition circuit 23 while being separated. The stabilization synchronization superimposition circuit 23 includes the synchronization stabilization circuit 7 in the video signal 4.
Is a circuit for superimposing the synchronization stabilization signal 22 obtained in the step (a).

FIG. 4 is a diagram showing a configuration of the stabilized synchronous superimposing circuit 23. In FIG. 4, a synchronization pulse adjustment circuit 40 adjusts the amplitude level of the synchronization stabilization signal 22 to a predetermined level by matching the polarity of the synchronization stabilization signal 22 with the polarity of the video signal 4. The addition circuit 41 adds the video signal 4 and the output signal of the synchronization pulse adjustment circuit 40. The amplifying circuit 42 outputs the stabilized synchronized superimposed video signal 24 in which the amplitude level of the output signal of the adding circuit 41 is set to a predetermined level.

FIG. 5 shows the video signal 4 and the output signal of the addition circuit 41 when the electric field condition is changed. In FIG. 5, (a) shows the waveform under the condition of strong electric field / multipath, (b) shows the waveform under the condition of strong electric field / multipath, and (c) shows the waveform under the condition of weak electric field / multipath. Under any of the conditions, a pulse waveform clearly appears in the synchronizing signal of the adder circuit output signal. The amplitude voltage of the synchronization pulse portion of the stabilized synchronized superimposed video signal 23 obtained as described above is
Is determined by the ratio of the peak-to-peak voltage Vin to the amplitude signal Vs of the output signal of the synchronous pulse adjustment circuit 40. In the case of the NTSC signal, the standard value of the voltage amplitude of the sync pulse portion is 40 Vin / 140 with respect to the peak-to-peak voltage Vin of the video signal 4. Synchronization stabilization can be achieved by increasing the amplitude value of the pulse section. In this case, if the amplitude level of the entire video signal is specified as a constant level, the amplitude level of the video information will decrease, but finally, this difference is eliminated by adjusting the gain of the video signal in the video display circuit. can do.

The video display circuit 25 reproduces the second stabilized synchronizing signal and the second video signal in the video display circuit by synchronizing and separating the stabilized synchronized superimposed video signal 24, and The second video signal reproduces and displays a video after color demodulation based on the synchronized signal. The difference between the video signal 4 output from the TV tuner 3 and the stabilized synchronized superimposed video signal 24 is that although the contained video information is the same, the stabilized synchronized superimposed video signal 24
In the example, the synchronization signal is a stabilized signal. Therefore, the video display circuit 25 can reproduce the video with stable synchronization even during traveling.

As described above, according to the present embodiment, even when the reception electric field condition is deteriorated during mobile reception and the synchronization signal is disturbed, the synchronization stabilization circuit corrects the synchronization disturbance for the synchronization stabilization signal. Generate. Further, even in a separate type television device in which the tuner housing and the housing of the video display circuit are separated from each other and connected by a cable or wirelessly, a synchronization signal superimposing circuit that superimposes a synchronization stabilization signal on a video signal is provided. There is no need to separate the stabilized synchronizing signal from the video signal and supply it to the video display circuit. This allows
Synchronization stabilization Even if a general-purpose video display circuit having no synchronization signal input is used, a stable video without disturbance of the synchronization signal can be obtained.

In this embodiment, a digital PL as shown in FIG.
L configuration is used, but an analog PL as shown in FIG.
A similar effect can be obtained even if the horizontal synchronizing unit 7c is configured as an L circuit.

In FIG. 6, reference numeral 50 denotes a phase difference detection circuit;
1 is an integrating circuit, 52 is a voltage controlled oscillator, 53 is a frequency dividing circuit, and the phase difference detecting circuit 50 is configured to divide the phase of a signal obtained by dividing the output signal of the voltage controlled oscillator 52 and the horizontal synchronizing signal 9 And outputs a voltage value according to the phase difference. The integrating circuit 51 is a phase difference detecting circuit 50
By temporally integrating the voltage output values of the above, there is an effect of removing a disturbance component due to noise or the like. Voltage controlled oscillator 52
Changes the oscillation frequency of the voltage controlled oscillator 52 in a direction to eliminate the phase difference between the horizontal synchronizing signal 9 and the output signal of the frequency dividing circuit 53 according to the output from the integrating circuit 51. With the above operation, the horizontal stabilized synchronizing signal 14 obtained by stabilizing the horizontal synchronizing signal 9 is obtained as the output signal of the frequency dividing circuit 53.

In the above description, the configuration corresponding to the analog broadcasting system has been described. However, even in the case where a signal obtained by digitally modulating an information source obtained by digitally encoding an NTSC signal is transmitted, the TV tuner 3 is not subjected to digital modulation. The same effect can be obtained by replacing the digital demodulator and the digital decoder corresponding to the system.

FIG. 7 shows another embodiment of the stabilized synchronous superimposing circuit 23. 4 is different from FIG. 4 in that a synchronization pulse processing circuit 55 for processing the pulse waveform of the synchronization signal after adjusting the polarity match and level of the input synchronization stabilization signal 22 with the video signal 4 is provided. Is a point.

This will be described below with reference to FIG. The process until the video signal 4 and the synchronization stabilization signal 22 are obtained is the same as the description in FIG. The synchronization pulse adjustment circuit 40 adjusts the amplitude level of the synchronization stabilization signal 22 to a predetermined level by matching the polarity of the synchronization stabilization signal 22 with the polarity of the video signal. The synchronous pulse processing circuit 55 outputs a synchronous processing signal 56 by inserting a cutting pulse before and after the output pulse waveform of the synchronous pulse adjusting circuit 40. The adding circuit 41 adds the video signal 4 and the synchronous processing signal 56. The amplifying circuit 42 controls the stabilized synchronized superimposed video signal 24 in which the amplitude level of the output signal of the adding circuit 41 is set to a predetermined level.
Is output.

FIG. 8A shows the output signal of the synchronization pulse adjusting circuit 40, and FIG. 8B shows the waveform of the synchronization pulse processing signal 56. In the synchronization pulse processing signal 56 of FIG. 8B, a cutting pulse having an amplitude level β and a time width Δt is inserted before and after a pulse of the output signal of the synchronization pulse adjustment circuit 40 that is input. By making a notch before and after the synchronization pulse in this way, when the video signal 4 and the synchronization processing signal 56 are superimposed, the phase difference between the originally existing synchronization pulse and the stabilized synchronization pulse superimposed in the video signal is within Δt. In this case, the effect of the synchronization pulse in the video signal can be reduced, and the pulse of the stabilized synchronization signal 22 can be made more prominent. This makes it possible for the video display circuit 25 to more reliably separate the synchronization pulse even when separating the second synchronization signal from the stabilized synchronization superimposed video signal 24 on which the stabilized synchronization signal 22 is superimposed. .

In this embodiment, an example in which the video signal 4 is a negative pulse is shown. However, the same effect can be obtained when the video signal 4 is a positive pulse. In this case, the synchronous pulse processing circuit 55 The cutting pulse is processed on the negative side.

(Embodiment 2) FIG. 9 shows a mobile-mounted television receiver according to a second embodiment of the present invention.
This will be described below with reference to FIG. Antenna An (n =
, K) are high-frequency signals Bn, respectively.
(N = 1, 2, 3,... K). The antenna switching circuit 60 selects one antenna As from the antenna An based on the antenna switching control signal 61 and connects it to the TV tuner 3. The TV tuner 3 selectively tunes a high-frequency signal of a TV channel to be received from a high-frequency signal Bs of the connected antenna As, and converts it into an intermediate frequency signal. Then, the converted intermediate frequency signal is detected to extract the video signal 4. The synchronization separation circuit 5 separates a composite synchronization signal 6 including horizontal and vertical synchronization from the video signal 4 and supplies the composite synchronization signal 6 to a synchronization stabilization circuit 7. The composite synchronization signal 6 is input to the synchronization stabilization circuit 7, and outputs a synchronization stabilization signal 22 in which the disturbance of the composite synchronization signal 6 has been corrected in the same manner as described with reference to FIGS. Similarly, the stabilized synchronizing superimposing circuit 23 outputs a stabilized synchronizing superimposed video signal 24 in which the synchronizing stabilizing signal 22 is superimposed on the video signal 4. The video display circuit 25 reproduces the second stabilized synchronization signal and the second video signal in the video display circuit 25 by synchronizing and separating the stabilized synchronized superimposed video signal 24, and performs the second stabilized synchronization. Based on the signal, the second video signal reproduces and displays the video after color demodulation.

The reception status detection / antenna control circuit 62 receives the stabilized synchronized superimposed video signal 24 and uses the third stabilized synchronized signal obtained by separating the synchronized signal contained in the signal. An antenna switching control signal 61 for detecting each reception state of the antenna An is output at an appropriate timing within the vertical flyback period. Then, an optimum antenna is selected by comparing the reception levels of the video signals 4 obtained by switching the respective antennas An. Then, an antenna switching control signal 61 for connecting the selection result is output, and the antenna switching circuit 60 is controlled. Thus, the optimum antenna is connected to the TV tuner 3 at a timing other than the vertical flyback period.

As described above, in this embodiment, the third stabilized synchronizing signal obtained by separating the stabilized synchronizing superimposed video signal 24 from the synchronizing signal is used as the reception status detection / antenna control circuit 62.
Since it is used as the reference timing of the antenna, the antenna switching control can always be performed at the timing of the accurate vertical retrace period, and the switching operation in the video information due to the erroneous timing operation does not occur, and when the switching appears on the received video. Does not cause a problem that the user views the video noise.
Further, in the present embodiment, when a component already integrated is used as the reception status detection / antenna control circuit 62, the synchronization separation circuit is integrated, so that the input is only a video signal. Also, by inputting the stabilized synchronized superimposed video signal 24, the third synchronized stabilized signal is separated, so that a stable operation is achieved.

[0042]

As described above, the present invention relates to a synchronization stabilization circuit for outputting a synchronization stabilization signal corrected for a vertical synchronization signal and a horizontal synchronization signal which are liable to be disturbed when receiving a moving picture, and a synchronization stabilization circuit. Synchronization stabilization even in a form in which the housing containing the tuner circuit and the housing containing the video display circuit are separated by the stabilization synchronization superimposition circuit that superimposes the digitized signal on the video signal There is no need to separate the signal and transmit it from the tuner circuit housing to the video display circuit housing. For this reason, a conventional general-purpose display can be used as it is, and the cost of the entire product can be reduced. Furthermore, the video signal output from the TV tuner and the video information included in the stabilized synchronized superimposed video signal are the same, but the synchronization of the synchronized signal included in the stabilized synchronized superimposed video signal is stabilized. The display circuit can reproduce an image with stable synchronization even when moving.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a television receiver mounted on a mobile object according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a horizontal synchronization unit of the synchronization stabilization circuit according to the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of a vertical synchronization unit of the synchronization stabilization circuit according to the first embodiment.

FIG. 4 is a block diagram showing a configuration of a stabilized synchronous superimposing circuit according to the first embodiment;

FIG. 5 is a waveform chart showing an operation example of the stabilized synchronous superimposing circuit according to the first embodiment.

FIG. 6 is a block diagram showing a configuration of another example of the synchronization stabilization circuit according to the first embodiment;

FIG. 7 is a block diagram showing a configuration of another example of the stabilized synchronous superimposition circuit according to the first embodiment;

FIG. 8 is a waveform chart showing an operation example of the stabilized synchronous superimposing circuit of FIG. 7;

FIG. 9 is a block diagram showing a configuration of a television receiver mounted on a mobile object according to a third embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional television receiver mounted on a mobile object.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Antenna 2 High frequency signal 3 TV tuner 4 Video signal 5 Synchronization separation circuit 6 Composite synchronization signal 7 Synchronization stabilization circuit 8 Horizontal / vertical separation circuit 9 Horizontal synchronization signal 10 Vertical synchronization signal 11 Reference clock oscillator 12 Reference clock signal 13 Divider circuit Reference Signs List 14 horizontal synchronization stabilization signal 15 phase difference detection circuit 16 phase shift direction detection signal 17 phase coincidence detection signal 18 phase control cycle counter 19 frequency division control circuit 20 reset control circuit 21 reset signal 22 synchronization stabilization signal 23 stabilization synchronization superimposition Circuit 24 Stabilized synchronous superimposed video signal 25 Video display circuit 30 Vertical frequency divider 31 Vertical synchronous stabilized signal 32 Vertical phase control circuit 33 Vertical reset pulse signal 40 Synchronous pulse adjusting circuit 41 Adder circuit 42 Amplifying circuit 50 Phase difference detecting circuit 51 Integrator 52 Voltage-controlled oscillator 53 Frequency dividing circuit 55 Synchronous pulse processing circuit 56 Synchronous processing signal 60 Antenna switching circuit 61 Antenna switching control signal 62 Reception status detection / antenna control circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Masahiko Nakamura Inventor Matsushita Communication Industrial Co., Ltd. 4-3-1 Ashimashimahigashi, Kohoku-ku, Yokohama, Kanagawa Prefecture (72) Inventor Masanobu Kanaya Amishima, Kohoku-ku, Yokohama, Kanagawa 4-3-1 East Higashi Matsushita Communication Industrial Co., Ltd. F-term (reference) 5C020 AA04 AA05 AA22 BA01 BA05 CA04 CA09 5K059 AA08 BB01 CC03 DD02 DD10 EE01

Claims (8)

[Claims] 1. A TV tuner for outputting a video signal detected from a reception signal obtained by an antenna, a synchronization separation circuit for separating a composite synchronization signal in which a vertical synchronization signal and a horizontal synchronization signal are mixed from the video signal, A synchronization stabilization circuit that corrects the disturbance of the composite synchronization signal, a stabilization synchronization superposition circuit that superimposes the output of the synchronization stabilization circuit on the video signal, and reproduces an image based on the output of the stabilization synchronization superposition circuit. And a video display circuit. 2. A reference clock oscillator that oscillates at an integer multiple of a horizontal synchronization frequency, and a frequency divider that divides an output of the reference clock oscillator and outputs a horizontal synchronization stabilization signal having a cycle substantially equal to the horizontal synchronization signal. A phase difference detector for detecting a phase shift direction of the horizontal sync signal with respect to the horizontal sync stabilizing signal, detecting whether the phase shift is within a predetermined range, and outputting the detected value as a phase match detection signal. A circuit, a phase control cycle counter that counts a vertical synchronization signal and outputs a counter value of a predetermined field cycle,
A frequency division number control circuit for increasing or decreasing the frequency division number of the frequency division circuit based on the phase shift detection result; and, based on the phase coincidence detection signal and the output of the phase control cycle counter, phase coincidence over a predetermined number of fields. A reset control circuit that outputs the horizontal synchronization signal to the frequency dividing circuit as a reset signal when the detection is not detected, and that causes a phase of the horizontal synchronization stabilization signal to match the horizontal synchronization signal. The television receiver according to claim 1, wherein: 3. A voltage-controlled oscillator capable of varying an oscillation frequency by a control voltage, a frequency-dividing circuit for dividing the output of the voltage-controlled oscillator and outputting a horizontal synchronization stabilization signal having a cycle substantially equal to the horizontal synchronization signal, A phase difference detection circuit that outputs a positive or negative voltage value according to a phase shift direction and a shift amount of the horizontal synchronization signal with respect to the horizontal synchronization stabilization signal; a control voltage of the voltage control oscillator that averages an output of the phase difference detection circuit; 2. The television receiver according to claim 1, further comprising a synchronization stabilization circuit including an integration circuit. 4. A vertical frequency divider circuit for dividing the output of a reference clock oscillator to output a vertical synchronization stabilization signal having a cycle substantially equal to the vertical synchronization signal, a supplied vertical synchronization signal and the vertical synchronization stabilization. Detecting phase coincidence with a signal, and when there is no phase coincidence continuously over a predetermined number of fields, outputting the vertical synchronization signal as a reset signal to the vertical frequency divider circuit, The television receiver according to claim 1, further comprising: a synchronization stabilization circuit including a vertical phase control circuit that matches a phase of the vertical synchronization stabilization signal. 5. A synchronizing pulse adjusting circuit for matching the polarity of a video signal and a composite synchronizing signal and setting the amplitude level of the composite synchronizing signal to a predetermined level, and adding the output of the synchronizing pulse adjusting circuit and the video signal. 2. The television receiver according to claim 1, further comprising a stabilizing synchronous superimposing circuit including an adder circuit and an amplifier circuit for setting the amplitude level of the adder circuit to a predetermined level. 6. A synchronizing pulse adjusting circuit for matching the polarity of a video signal and a composite synchronizing signal and setting an amplitude level of the composite synchronizing signal to a predetermined level, and a synchronizing pulse processing for processing an output pulse of the synchronizing pulse adjusting circuit. A stabilizing synchronous superimposing circuit including a circuit, an adding circuit for adding the output of the synchronous pulse processing circuit and the video signal, and an amplifier circuit for setting an amplitude level of the adding circuit to a predetermined level. The television receiver according to claim 1. 7. The television receiver according to claim 6, wherein a cutting pulse is inserted before and after the synchronization pulse to perform pulse processing. 8. A TV tuner for outputting a plurality of antennas, an antenna switching circuit for selecting one of the plurality of antennas, and a video signal detected from a reception signal obtained by the antenna selected by the antenna switching circuit. A synchronization separation circuit that separates a composite synchronization signal in which a vertical synchronization signal and a horizontal synchronization signal are mixed from the video signal; a synchronization stabilization circuit that corrects disturbance of the composite synchronization signal; and an output of the synchronization stabilization circuit. A stabilized synchronous superimposing circuit that superimposes the video signal on the video signal, and detects the reception quality of the antenna connected to the TV tuner from the stabilized synchronous superimposed video signal from the stabilized synchronous superimposing circuit, and selects an optimal antenna. A reception situation in which an antenna switching timing signal is generated based on the stabilized synchronous superimposed video signal and antenna switching by the antenna switching circuit is controlled. A television receiver comprising: a detection / antenna control circuit; and a video display circuit that reproduces a video by outputting the stabilized synchronized superimposed video signal.