JP2000208709A - Semiconductor integrated circuit device and ic card - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability for a noncontact type IC card or the like mounting a logic integrated circuit device by realizing a circuit device having a chip crack detecting function. SOLUTION: In a noncontact type IC card or the like provided with an antenna wiring AW, a resistance wiring RW for detecting chip cracks is formed along four sides of a semiconductor substrate CHIP of a logic integrated circuit device LSI, and a set input terminal and a reset input terminal are formed. A flip-flop in which an output signal turns into an internal reset signal IRST, a first delay circuit which contains the resistance wiring RW as a resistor R1, delays an external reset signal RST by a specific delay time, and transfers the signal to a cassette input terminal of the flip-flop, and a chip crack detecting circuit BD which receives practical resistance change of the resistor wiring RW and discriminates the generation of chip cracks in the semiconductor substrate CHIP are installed. The detection circuit BD contains a second delay circuit, which delays the external reset signal RST by a specific delay time and transfers the signal to the reset terminal of the flip-flop. The delay time is longer than the delay time of the first delay circuit in the normal state but is shorter than the delay time, when chip cracks are generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit device and an IC (Integrated Circuit).
The present invention relates to a card, for example, relates to a logic integrated circuit device having a nonvolatile memory such as a flash memory, a non-contact type IC card equipped with the same, and a technique particularly effective for improving reliability against chip breakage.

[0002]

2. Description of the Related Art There is a flash memory whose basic component is a memory array in which two-layer gate structure type memory cells having a control gate and a floating gate are arranged in a lattice, and a logic integrated circuit incorporating such a flash memory. There are semiconductor integrated circuit devices such as devices. In addition, there is a so-called non-contact type IC card in which the above-mentioned logic integrated circuit device is mounted on a card surface made of plastic or the like, and exchanges operating power, data, and the like via an antenna wiring formed on the card surface.

[0003]

Prior to the present invention, the present inventors engaged in the development of a non-contact type IC card having a logic integrated circuit device, and noticed the following problems. That is, logic integrated circuit devices and the like mounted on a non-contact type IC card tend to be highly integrated and scaled up with the progress of integrated circuit technology, and accordingly, the chip size has been increased. It is getting. However, non-contact type IC cards tend to be smaller and thinner than business cards, for example, in order to enhance their convenience, and accordingly, the base card is becoming thinner. For this reason, when stress / pressure is applied to the non-contact type IC card due to card bending or the like by the card user, it is considered that the semiconductor substrate (chip) of the logic integrated circuit device is cracked and cannot operate normally.

As is well known, an IC card is expected to be used in a money-related system such as electronic money, and is required to have sufficient reliability. Therefore, when the IC card cannot operate normally due to the chip breakage or the like as described above, it is necessary to completely stop the operation, but the current non-contact type IC card does not have a chip breakage detection function. However, sufficient reliability has not been secured.

An object of the present invention is to provide a semiconductor integrated circuit device such as a logic integrated circuit device having a chip crack detecting function. Another object of the present invention is to improve the reliability of a non-contact type IC card or the like on which a logic integrated circuit device or the like is mounted.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a non-contact type IC card or the like having an antenna wiring, a chip crack detection wiring is formed along four sides of a semiconductor substrate surface of a mounted logic integrated circuit device and the like, and a set input terminal and a reset input terminal are provided. A flip-flop whose output signal is used as an internal reset signal, and a wiring for detecting chip breakage as first resistance means for transmitting an external reset signal to a set input terminal of the flip-flop with a predetermined delay time. And a delay circuit for delaying the external reset signal by a predetermined delay time and transmitting it to the reset input terminal of the flip-flop, and the delay time is longer than the normal delay time of the first delay circuit, and chip cracking occurs. A second delay circuit shorter than the delay time at
A chip crack detection circuit is provided for identifying that a chip crack has occurred in the semiconductor substrate in response to a substantial change in the resistance value of the chip crack detection wiring.

According to the above means, when a chip break occurs in a logic integrated circuit device or the like mounted on a non-contact type IC card, this is detected and the invalid level of the external reset signal is changed to the invalid level of the internal reset signal. Can be selectively inhibited from being transmitted, and the subsequent operation of the logic integrated circuit device or the like can be completely stopped. As a result, malfunctions due to chip breakage of the logic integrated circuit device or the like can be prevented, and the reliability of the logic integrated circuit device or the like and the non-contact type IC card or the like mounting the same can be improved.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an external structural view of one embodiment of a non-contact type IC card ICC (IC card) mounted with a logic integrated circuit device LSI (semiconductor integrated circuit device) to which the present invention is applied. It is shown. FIG. 2 also shows FIG.
FIG. 1 is a block diagram of an embodiment of a non-contact type IC card ICC and a logic integrated circuit device LSI mounted thereon;
FIG. 3 shows a board layout of one embodiment of the logic integrated circuit device LSI of FIG. First, the outline of the configuration and operation of the non-contact type IC card ICC and the logic integrated circuit device LSI of this embodiment will be described with reference to these drawings.
The circuit elements constituting each part of the logic integrated circuit device LSI shown in FIGS. 2 and 3 are not particularly limited.
SFET (metal oxide semiconductor field effect transistor.
In this specification, a MOSFET is referred to as an insulated gate field effect transistor).
It is formed on the P plane. In the following description regarding FIGS. 1 and 3, the positional relationship in each drawing represents the upper, lower, left and right on the card surface or the semiconductor substrate CHIP surface.

Referring to FIG. 1, a non-contact type IC of this embodiment is shown.
Although not particularly limited, the card ICC includes, for example, a logic integrated circuit device LSI mounted as a chip CHIP below a card surface made of a plastic material, and an antenna wiring AW formed in a rectangular coil shape above the logic integrated circuit device LSI. Further, as shown in FIG. 2, the logic integrated circuit device LSI includes an interface circuit RFIF coupled to the antenna wiring AW, a chip crack detection circuit BD, a control logic unit LC, and a memory unit MEMU. The memory unit MEMU is, as shown in FIG. 3, a semiconductor substrate C on which a logic integrated circuit device LSI is formed.
The other interface circuit RFIF, chip crack detection circuit BD, and control logic unit LC are arranged under the HIP so as to occupy more than half of the area.
It is located above P.

In this embodiment, a logic integrated circuit device L
Around the interface circuit RFIF, the chip crack detection circuit BD, the control logic unit LC, and the memory unit MEMU constituting the SI, along the four sides of the semiconductor substrate CHIP, a resistance wire RW (for chip crack detection) made of, for example, polysilicon or the like is provided. Wiring) is arranged. This resistance wiring RW
Is a resistor R1 and constitutes a chip crack detection circuit BD together with other circuit elements (not shown), as will be described later.
Chip breakage due to excessive card bending of C is detected. For this reason, the resistance value of the resistance wiring RW, that is, the resistance value of the resistor R1 is set to a relatively small predetermined value R1 in a normal state, that is, when the semiconductor substrate CHIP is not in a chip crack state. It grows up to infinity.

Returning to FIG. Non-contact type IC of this embodiment
The card ICC is electrically coupled to a card driving device (not shown) without a connection means such as a connector, that is, via a radio signal transmitted and received from the antenna wiring AW. At this time, the interface circuit RFIF of the logic integrated circuit device LSI rectifies the carrier component of the radio signal, for example, so that the power supply voltage VCC and the ground potential VS.
S is generated and supplied as operation power for each unit.
The clock signal CK and the external reset signal RST are extracted from the received wireless signal and supplied to each unit of the logic integrated circuit device LSI including the chip crack detection circuit BD. Further, it extracts a valid reception signal RS from the received radio signal and transmits it to the control logic unit LC, converts the transmission signal TS supplied from the control logic unit LC into a radio signal, and outputs the radio signal to the card driving device.

The power supply voltage VCC is not particularly limited, but has a positive potential such as +2.5 V (volt). The external reset signal RST is a non-contact type IC.
When the card ICC is initially mounted on the card driving device, it is set to an effective level of a high level such as the power supply voltage VCC (hereinafter, the high level represents a potential such as the power supply voltage VCC), and the main operation of the IC card, that is, Immediately before the operation for realizing the main function is started, a low level such as the ground potential VSS (hereinafter, the low level represents a potential like the ground potential VSS) is set to an invalid level.

Next, the chip crack detection circuit BD of the logic integrated circuit device LSI detects a chip break of the logic integrated circuit device LSI due to a card bending or the like in response to a change in the resistance value of the resistance wiring RW, that is, the resistance R1. An internal reset signal IRST as an output signal is selectively formed. That is, the chip crack detection circuit BD is a non-contact type IC card I
Initially, when the CC is mounted on the card driving device, the internal reset signal IR is received in response to the high level of the external reset signal RST.
ST is set to a high effective level, and each unit of the logic integrated circuit device LSI including the control logic unit LC is reset. When the external reset signal RST is set to a low level in order to start the main operation of the logic integrated circuit device LSI, on the condition that the resistance value of the resistance wiring RW, that is, the resistance R1 is equal to or less than a predetermined value, that is, the logic integrated circuit Device LSI
Under the condition that the semiconductor substrate CHIP is not in a chip cracked state, the internal reset signal IRST is selectively set to the invalid level of the low level to enable the subsequent operation of the logic integrated circuit device LSI.

However, when the resistance value of the resistance wiring RW, that is, the resistance of the resistor R1 is larger than a predetermined value, that is, when a chip crack occurs in the semiconductor substrate CHIP of the logic integrated circuit device LSI, the internal reset signal IRST is set to a high effective level. The respective parts of the logic integrated circuit device LSI are kept in the reset state, and the subsequent operation is prohibited, and the malfunction of the logic integrated circuit device LSI is prevented.
It plays a role in improving the reliability of the IC and the non-contact type IC card ICC on which it is mounted. The specific configuration and operation of the non-contact type IC card ICC will be described later in detail.

On the other hand, the control logic unit LC of the logic integrated circuit device LSI is composed of a controller of a stored program system such as a CPU (Central Processing Unit), and controls and controls the operation of each unit. In addition, the memory unit MEMU
Comprises a non-volatile memory such as a flash memory, and functions as a storage unit for realizing a main function of the non-contact type IC card ICC. At this time, the control logic unit LC analyzes various commands based on the received signal RS transmitted from the interface circuit RFIF, selectively forms the memory control signal MCS, the address AD, and the data DT, and generates the memory unit MEMU. Control the write or read operation for Also, the memory unit M
The EMU according to the memory control signal MCS, the address AD and the data DT supplied from the control logic unit LC
A write or read operation for the specified address is performed, and the result is output to the control logic unit LC.

As described above, the control logic part LC is provided with the internal reset signal IR supplied from the chip break detection circuit BD.
Each part of the logic integrated circuit device LSI is reset according to ST, and the internal reset signal IRST is selectively set to an invalid level, that is, a low level, on condition that the semiconductor substrate CHIP of the logic integrated circuit device LSI is not in a chip breaking state. . Therefore, each part of the logic integrated circuit device LSI is selectively released from its reset state on condition that the internal reset signal IRST is at a low level, that is, on condition that the semiconductor substrate CHIP is not in a chip break state. The normal operation for realizing the main function of the contact type IC card ICC is started.

FIG. 4 shows the logic integrated circuit device LSI of FIG.
5 and FIG. 6 show signal waveform diagrams of the normal state and the embodiment of the chip breakage occurrence state in the case of chip breakage, respectively. With reference to these drawings, the specific configuration and operation of the chip breakage detection circuit BD included in the logic integrated circuit device LSI of this embodiment and its features will be described.

In FIG. 4, the chip break detection circuit BD of the logic integrated circuit device LSI of this embodiment is not particularly limited, but includes a set input terminal SB, a reset input terminal RB,
The non-inverting output terminal Q and the inverting output terminal QB (where
A so-called inverted signal or the like which is selectively set to a low level when it is made valid is indicated by adding a B to the end of its name. The same applies to the following.) An external reset signal RST is connected to a set input terminal SB of the flip-flop FF via a first delay circuit including an inverter V1, a resistance wiring RW, that is, a resistance R1 (first resistance means), a capacitor C1, and inverters V2 and V3. Are supplied to the inverting input terminals thereof, the inverter V4, the resistor R3 (second resistor means),
A second capacitor C2 and inverters V5 and V6
The external reset signal RST is supplied through the delay circuit. Also, the non-inverted output signal Q of the flip-flop FF
Is supplied to the control logic unit LC as an internal reset signal IRST.

A resistor R2 having a sufficiently larger resistance value than the resistors R1 and R3 is provided between the input terminal of the inverter V2 and the ground potential.
When the resistance wiring RW is completely cut off due to chip breakage, it works to prevent the input terminal of the inverter V2 from being in a floating state.

As described above, the external reset signal RST
Is set to a high-level valid level at the beginning when the non-contact type IC card ICC is mounted on the card driving device, and set to a low-level invalid level immediately before the main operation is started. The resistance value of the resistance wire RW, ie, the resistance of the resistor R1, which constitutes the chip crack detection circuit BD is a predetermined value, ie, the chip break detection circuit BD, when the semiconductor substrate CHIP of the logic integrated circuit device LSI is not in a chip crack state. When the semiconductor substrate CHIP is in a chip cracked state and a part of the resistance wiring RW is damaged or lost, the resistance is set to a value smaller than the resistance of the resistor R3. And the resistance wiring RW
Becomes infinite when is completely disconnected.

When the non-contact type IC card ICC is mounted on the card driving device and the external reset signal RST is set to the high effective level, the chip breakage detection circuit BD of the logic integrated circuit device LSI uses FIG. 5 and FIG. , The set input signal FF-SB and the reset input signal FF-RB to the flip-flop FF are both set to the low effective level. For this reason, the set priority type flip-flop FF is connected to the set input signal FF.
In response to the valid level on the -SB side, the internal reset signal IRST, which is the non-inverted output signal Q, is set to a high valid level. As a result, each unit of the logic integrated circuit device LSI including the control logic unit LC is in a reset state, that is, a standby state for normal operation.

Next, the non-contact type I
The operation of the C card ICC starts, and the external reset signal R
When ST is set to the low invalid level, in the logic integrated circuit device LSI, in accordance with the resistance value of the resistance wiring RW, that is, the resistor R1, in other words, the logic integrated circuit device LSI
The internal reset signal IRST, which is the output signal of the chip crack detection circuit BD, is selectively set to an invalid level or remains at an effective level depending on whether or not the semiconductor substrate CHIP has a chip crack.

That is, when the logic integrated circuit device LSI is in a normal state in which the chip is not broken, the chip break detection circuit BD which has received the change of the external reset signal RST to the low level, as shown in FIG. Resistance R
When a relatively short delay time tsn determined by a relatively small resistance value of 1 and the capacitance value of the capacitor C1 has elapsed, the set input signal FF-SB to the flip-flop FF changes from a low level to a high level. The resistance R3
When a delay time tr determined by the slightly larger resistance value and the capacitance value of the capacitor C2 has elapsed, the flip-flop F
The reset input signal FF-RB for F changes from low level to high level.

Therefore, the internal reset signal IR which is the non-inverted output signal Q of the set priority type flip-flop FF
ST changes to a low-level invalid level when the set input signal FF-SB is changed to the high level while the reset input signal FF-RB for the flip-flop FF is set to the low level. L
The normal operation for realizing the main function of the SI is started.

On the other hand, when the logic integrated circuit device LSI is in a chip break state, the chip break detection circuit BD which has received the change of the external reset signal RST to the low level, as shown in FIG. When a delay time tr determined by the value and the capacitance value of the capacitor C2 elapses, first, the reset input signal FF to the flip-flop FF
-RB changes from the low level to the high level, and the set input signal FF-SB has a relatively long delay determined by the relatively large resistance value of the resistance wiring RW, that is, the resistance R1 and the capacitance value of the capacitance C1 in the disconnected or missing state. When the time tsb has elapsed, the level changes from the low level to the high level or remains at the low level.

Therefore, the internal reset signal IR as the non-inverted output signal Q of the set-priority type flip-flop FF
ST is kept at a high effective level, which causes each part of the logic integrated circuit device LSI to remain in a reset state, and the control logic portion LC of the logic integrated circuit device LSI
Are kept in a standby state. As a result, it is possible to prevent a malfunction of the logic integrated circuit device LSI in a chip cracked state, whereby the logic integrated circuit device LS
Thus, the reliability of the non-contact type IC card ICC mounting the same can be improved.

When the resistance wiring RW of the logic integrated circuit device LSI is completely disconnected due to chip breakage, the change of the internal reset signal IRST to the low level is not transmitted to the set input terminal SB of the flip-flop FF. However, the chip crack detection circuit BD of this embodiment
As described above, the resistor R2 having a sufficiently large resistance value as compared with the resistors R1 and R3 is provided between the input terminal of the inverter V2 and the ground potential. This resistance R2
When the resistance wiring RW is completely disconnected due to chip breakage, the input signal of the inverter V2 is fixed at a low level, the set input signal FF-SB to the flip-flop FF is fixed at a low level, and the internal reset signal IRST At the invalid level. As a result, even if the resistance wiring RW is completely disconnected due to chip breakage, malfunction of the logic integrated circuit device LSI is prevented,
Logic integrated circuit device LSI and non-contact type I mounting the same
The reliability of the C card ICC can be further improved.

The functions and effects obtained from the above embodiment are as follows. (1) In a non-contact type IC card or the like having an antenna wiring, a chip crack detecting wiring is formed along four sides of a semiconductor substrate surface of a mounted logic integrated circuit device or the like, and a set input terminal and a reset input are formed. A flip-flop whose output signal is an internal reset signal; and a chip crack detection wiring as first resistance means. The external reset signal is delayed by a predetermined delay time to a set input terminal of the flip-flop. A first delay circuit to be transmitted, an external reset signal delayed by a predetermined delay time and transmitted to the reset input terminal of the flip-flop, and the delay time is longer than the normal delay time of the first delay circuit. A second delay circuit that is shorter than the delay time at the time of chip cracking. By providing a chip crack detection circuit for identifying that a chip crack has occurred in a semiconductor substrate in response to a qualitative change in resistance value, a logic integrated circuit device mounted on a non-contact type IC card can be subjected to card bending or the like. If a chip break occurs, this is detected, and the invalid level of the external reset signal is selectively prohibited from being transmitted as the invalid level of the internal reset signal, and the subsequent operation of the logic integrated circuit device or the like is completely prevented. The effect of being able to stop is obtained.

(2) According to the above item (1), an effect is obtained that a malfunction due to chip breakage of a logic integrated circuit device or the like can be prevented. (3) According to the above item (2), an effect is obtained that the reliability of the logic integrated circuit device and the like and the non-contact type IC card and the like mounting the same can be improved. (4) In the above items (1) to (3), a pull-down or pull-up resistor for fixing the set input terminal of the flip-flop to an effective level when the chip-break detection wiring is completely disconnected due to chip break. This prevents malfunctions of the logic integrated circuit device and the like even when the chip crack detection wiring is completely cut off, and reduces the reliability of the logic integrated circuit device and the like and the non-contact type IC card or the like on which the device is mounted. The effect that the property can be further improved is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, a logic integrated circuit device LSI mounted on a non-contact type IC card ICC includes, for example, a memory integrated circuit device corresponding to a memory unit MEMU, an interface circuit RFIF, a chip crack detection circuit BD, and a control logic unit LC. Can be formed separately from a logic integrated circuit device corresponding to
The capacitances C1 and C2 constituting D may be formed as a semiconductor integrated circuit device separate from other components. Non-contact type I
The C card ICC can take any shape, and the mounting position of the logic integrated circuit device LSI, the shape of the antenna wiring AW, and the like can take various embodiments. The IC card is not required to be a non-contact type, but may be connected to a card driving device via, for example, a connector or an electrode.

In FIG. 2, the resistance wiring RW may be replaced by a metal wiring layer such as aluminum, or may be formed using other various wiring materials. The blocks of the logic integrated circuit device LSI can take various embodiments, and the same applies to combinations and effective levels of signals transmitted and received between the blocks, polarities and absolute values of power supply voltages, and the like. In FIG. 3, the logic integrated circuit device L
The shape of the SI semiconductor substrate CHIP is not restricted by this embodiment. The arrangement position of each block can be arbitrarily designed, and the same applies to the arrangement of the resistance wiring RW.

In FIG. 4, the first and second delay circuits provided before the set input terminal SB and the reset input terminal RB of the flip-flop FF can have an arbitrary configuration, and the resistor R2 is connected to, for example, the inverter V3. It can be replaced with a pull-up resistor provided between the input terminal and the power supply voltage VCC. The specific configuration of the chip crack detection circuit BD can take various embodiments, and the effective levels of the external reset signal RST and the internal reset signal IRST can be arbitrarily set.

In FIGS. 5 and 6, the specific level and time relationship of each signal do not affect the gist of the present embodiment, and the same applies to the effective level.

In the above description, the case where the invention made by the inventor is mainly applied to a logic integrated circuit device and a non-contact type IC card on which the logic integrated circuit device is mounted has been described. The present invention is not limited thereto, and can be applied to, for example, various gate arrays, memory integrated circuit devices, and various IC cards equipped with the same. INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a semiconductor integrated circuit device having a risk of chip breakage, an IC card mounting the same, and a device or system including such a semiconductor integrated circuit device or IC card.

[0036]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a non-contact type IC card or the like having an antenna wiring, a chip crack detection wiring is formed along four sides of a semiconductor substrate surface of a mounted logic integrated circuit device and the like, and a set input terminal and a reset input terminal are provided. A flip-flop whose output signal is used as an internal reset signal, and a wiring for detecting chip breakage as first resistance means for transmitting an external reset signal to a set input terminal of the flip-flop with a predetermined delay time. And a delay circuit for delaying the external reset signal by a predetermined delay time and transmitting it to the reset input terminal of the flip-flop, and the delay time is longer than the normal delay time of the first delay circuit, and chip cracking occurs. And a second delay circuit that is shorter than the delay time at the time. By providing a chip crack detection circuit for identifying that a chip crack has occurred on a semiconductor substrate in response to a change in resistance, if a chip crack occurs in a logic integrated circuit device or the like mounted on a non-contact type IC card, By detecting this, the transmission of the invalid level of the external reset signal as the invalid level of the internal reset signal is selectively inhibited, and the subsequent operation of the logic integrated circuit device or the like can be completely stopped. As a result, malfunctions due to chip breakage of the logic integrated circuit device or the like can be prevented, and the reliability of the logic integrated circuit device or the like and the non-contact type IC card or the like mounting the same can be improved.

[Brief description of the drawings]

FIG. 1 is an external structural view showing one embodiment of a non-contact type IC card on which a logic integrated circuit device to which the present invention is applied is mounted.

FIG. 2 is a block diagram showing one embodiment of the non-contact type IC card of FIG. 1 and a logic integrated circuit device mounted thereon.

FIG. 3 is a board layout diagram showing one embodiment of a logic integrated circuit device mounted on the non-contact type IC card of FIG. 1;

FIG. 4 is a circuit diagram showing one embodiment of a chip crack detection circuit included in the logic integrated circuit device of FIG. 3;

FIG. 5 is a signal waveform diagram showing one embodiment of a normal state of the chip crack detection circuit of FIG. 4;

FIG. 6 is a signal waveform diagram showing one embodiment of the chip crack detection circuit of FIG. 4 when a chip crack occurs.

[Explanation of symbols]

ICC: non-contact IC card, LSI: logic integrated circuit device, CHIP: semiconductor substrate (chip), AW
Antenna wiring. RFIF ... Interface circuit, BD
…… Chip crack detection circuit, LC …… Logic control unit, MEM
U: Memory unit, RW: Resistance wiring, RST:
External reset signal, IRST ... Internal reset signal, C
K: clock signal, VCC: power supply voltage, VSS:
Ground potential, RS: received signal, TS: transmitted signal, MC
S: memory control signal, AD: address, DT: data. V1 to V6: inverters, R1 to R3: resistors, C1 to C2, capacitors, FFs: set-priority flip-flops. tsn, tsb, tr ... delay time.

Claims (8)

[Claims] A chip crack is generated in a semiconductor substrate in response to a substantial change in a resistance value of a chip crack detection wiring formed along each side of a semiconductor substrate surface and the chip crack detection wiring. And a chip crack detection circuit for identifying the situation. 2. The chip crack detection circuit according to claim 1, wherein the chip crack detection circuit changes the invalid level of the external reset signal supplied from outside when the resistance value of the chip crack detection wiring is smaller than a predetermined value. The semiconductor integrated circuit device is capable of selectively starting an operation for realizing its main function in response to the invalid level of the internal reset signal. A semiconductor integrated circuit device characterized by the above-mentioned. 3. The chip crack detecting wire according to claim 1, wherein the chip crack detection wiring has a relatively small predetermined resistance value in a normal state, and has a resistance value larger than the predetermined value when a chip crack occurs. A semiconductor integrated circuit device comprising a resistance wiring. 4. The flip-flop according to claim 1, further comprising a set input terminal and a reset input terminal, the output signal of which is the internal reset signal. A first delay circuit that includes a chip crack detection wiring as first resistance means, delays the external reset signal by a predetermined delay time, and transmits the external reset signal to a set input terminal of the flip-flop; The second delay is delayed by the delay time and transmitted to the reset input terminal of the flip-flop, and the delay time is longer than the normal delay time of the first delay circuit and shorter than the delay time when a chip break occurs. And a semiconductor integrated circuit device. 5. The second delay circuit according to claim 4, wherein a resistance value of the second delay circuit is larger than a resistance value of the first resistance means in a normal state and smaller than a resistance value of the first resistance means when a chip break occurs. A semiconductor integrated circuit device including resistance means. 6. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is mounted on a non-contact type IC card having a predetermined antenna wiring. A semiconductor integrated circuit device. 7. A chip crack is generated in the semiconductor substrate due to a substantial change in resistance of the chip crack detection wiring formed along each side of the semiconductor substrate surface and the chip crack detection wiring. An IC card comprising a semiconductor integrated circuit device including a chip crack detection circuit for identifying the fact. 8. The IC card according to claim 7, wherein the IC card is a non-contact type IC card having a predetermined antenna wiring.