JP2000200885A - Fabrication of capacitor - Google Patents

Fabrication of capacitor

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Publication number
JP2000200885A
JP2000200885A JP11001088A JP108899A JP2000200885A JP 2000200885 A JP2000200885 A JP 2000200885A JP 11001088 A JP11001088 A JP 11001088A JP 108899 A JP108899 A JP 108899A JP 2000200885 A JP2000200885 A JP 2000200885A
Authority
JP
Japan
Prior art keywords
substrate
capacitor
film
thin film
angle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP11001088A
Other languages
Japanese (ja)
Inventor
Setsuya Iwashita
節也 岩下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP11001088A priority Critical patent/JP2000200885A/en
Publication of JP2000200885A publication Critical patent/JP2000200885A/en
Withdrawn legal-status Critical Current

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  • Semiconductor Memories (AREA)

Abstract

PROBLEM TO BE SOLVED: To form an oxide dielectric thin film excellent in coverage and characteristics by facing a substrate and a deposition source at an appropriate angle when an oxide dielectric thin film is formed on an electrode of three- dimensional structure by physical film deposition and turning the substrate continuously during film deposition. SOLUTION: Ti0.7Al0.3N excellent in oxidation resistance is grown epitaxially as a buffer layer on an Si substrate by reactive deposition employing nitrogen plasma. Subsequently, Ru is deposited thereon as a metal layer 3 by sputtering and a metal oxide thin film layer 4 of RuO2 is formed by laser abrasion using R2O2, as a target. Furthermore, dry etching is performed and a three-dimensional lower electrode structure is formed by machining the RuO2/Ru before a capacitor 5 is formed by physical film deposition. In this regard, an angle α is set between the normal direction of the substrate 11 and the position of the deposition source 12, i.e., the target.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、3次元の電極構造
を有するギガビット級DRAMの酸化物誘電体薄膜から
なるキャパシターの形成技術、さらに詳しく言えば物理
的成膜法を用いたキャパシターの製造方法に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for forming a capacitor made of an oxide dielectric thin film of a gigabit-class DRAM having a three-dimensional electrode structure, and more particularly, to a method of manufacturing a capacitor using a physical film forming method. It is about.

【0002】[0002]

【従来の技術】DRAMの大規模集積化は、設計寸法の
縮小化に伴うメモリーセルの微細化により実現されてき
た。メモリーセルサイズが縮小されてもDRAMの安定
動作のためには、キャパシター容量値を一定以上に保つ
必要がある。そのため、メガビット世代では、容量電極
構造を3次元化してきた。しかし、ギガビット世代で
は、従来のSiON系の容量絶縁膜と3次元構造の組み
合わせでは必要とされるキャパシター容量値を得ること
が困難である。したがって、より大きな比誘電率をもつ
高誘電率薄膜が必要であり、その中でも(Ba,Sr)
TiO(BST)が有望と考えられている。ただし、
BSTを用いても、ギガビット世代では平面型キャパシ
ター構造の適用は困難であり、厚膜スタックなどの側面
を利用する3次元電極構造が必要である。種々の方法で
BSTをはじめとする酸化物誘電体薄膜の成膜が行われ
ているが、その中でもJpn.J.Appl.Phy
s.33,5129(1994)やJpn.J.App
l.Phys.35,5089(1996)に掲載され
ているように、電極構造側面にも回り込むCVD法が3
次元のキャパシターの形成技術として注目されている。
2. Description of the Related Art Large-scale integration of DRAMs has been realized by miniaturization of memory cells accompanying reduction in design dimensions. Even if the memory cell size is reduced, it is necessary to keep the capacitance value of the capacitor above a certain value for stable operation of the DRAM. Therefore, in the megabit generation, the capacitance electrode structure has been made three-dimensional. However, in the gigabit generation, it is difficult to obtain a required capacitor capacitance value by a combination of a conventional SiON-based capacitance insulating film and a three-dimensional structure. Therefore, a high-dielectric-constant thin film having a higher relative dielectric constant is required, and among them, (Ba, Sr)
TiO 3 (BST) is considered promising. However,
Even if BST is used, it is difficult to apply a planar capacitor structure in the gigabit generation, and a three-dimensional electrode structure using a side surface such as a thick film stack is required. Oxide dielectric thin films such as BST are formed by various methods. Among them, Jpn. J. Appl. Phys
s. 33 , 5129 (1994) and Jpn. J. App
l. Phys. 35 , 5089 (1996), there is a method using a CVD method which also extends to the side surface of the electrode structure.
It is attracting attention as a technology for forming a two-dimensional capacitor.

【0003】[0003]

【発明が解決しようとする課題】しかし、従来の成膜法
を用いたキャパシター形成技術には以下のような問題点
がある。
However, the capacitor forming technique using the conventional film forming method has the following problems.

【0004】まず、従来のスパッタ法、蒸着法、レーザ
ーアブレーション法などの物理的成膜法では、前記のよ
うに側面に回り込まないため、3次元電極構造上へのキ
ャパシター形成には単純に応用できない。
First, conventional physical film forming methods such as a sputtering method, a vapor deposition method, and a laser ablation method cannot simply be applied to the formation of a capacitor on a three-dimensional electrode structure because they do not go around the side as described above. .

【0005】一方、3次元構造の側面にも回り込むとさ
れるCVD法には熱CVD法とプラズマCVD法がある
が、次のような問題点を有する。熱CVD法では、80
%前後の高いカバレッジ(上面と側面の膜厚比)が得ら
れるが、低温成膜した後、結晶化させるために700℃
以上の加熱処理を必要とする。この加熱処理は工程が面
倒なだけでなく、下部の電極にも影響を与えるため、プ
ロセス上好ましくない。また、BSTを熱CVD法で成
膜する場合、成膜温度により組成が大きく変化する、あ
るいは面内分布の不均一性が大きい。組成は比誘電率や
リーク電流特性に影響を与えるため、組成変化は好まし
くない。さらに、側面での膜厚が均一ではない等の問題
を有する。
[0005] On the other hand, there are a thermal CVD method and a plasma CVD method as CVD methods which are supposed to reach the side surface of the three-dimensional structure, but have the following problems. In the thermal CVD method, 80
%, A high coverage (a film thickness ratio between the upper surface and the side surface) of about 700% is obtained.
The above heat treatment is required. This heat treatment is not preferable in terms of process because it not only complicates the process but also affects the lower electrode. In the case where BST is formed by a thermal CVD method, the composition greatly changes depending on the film forming temperature, or the in-plane distribution has large non-uniformity. Since the composition affects the relative dielectric constant and the leakage current characteristics, a change in the composition is not preferable. Further, there is a problem that the film thickness on the side surface is not uniform.

【0006】一方、プラズマCVD法は、熱CVD法に
比べ比較的低温でも結晶性の良いBST膜が得られ、よ
り広い基板温度範囲でも組成変化が小さく、面内分布の
均一性も良い。また、側面の膜厚も均一である。しか
し、プラズマCVDで成膜したときのカバレッジは50
%程度であり、熱CVDよりも劣る。さらに、熱CVD
法より結晶性が良いにも関わらず、BSTのteq(2
5fFを得るために必要な誘電体膜のSiO換算膜
厚)は、実膜厚30nmで0.4nm弱であり、これは
スパッタで作製したBST膜のteq0.2nm台より
劣っている。また、リーク電流も実膜厚30nmで10
―9〜10―8A/cm台であり、膜厚がさらに薄く
なるにしたがって、リーク電流増大と誘電率減少が見ら
れる。さらにCVD法は危険性のあるガスを用いるた
め、環境衛生上よくない。
On the other hand, in the plasma CVD method, a BST film having good crystallinity can be obtained even at a relatively low temperature as compared with the thermal CVD method, the composition change is small even in a wider substrate temperature range, and the in-plane distribution is uniform. Further, the film thickness on the side surface is also uniform. However, the coverage when the film is formed by plasma CVD is 50.
%, Which is inferior to thermal CVD. Furthermore, thermal CVD
Despite the better crystallinity than the BST method, the BST t eq (2
SiO 2 equivalent thickness of the dielectric film required to obtain a 5 fF) is 0.4nm just under real thickness 30 nm, which is inferior to t eq 0.2 nm stand BST films prepared by sputtering . Also, the leakage current is 10 at the actual film thickness of 30 nm.
−9 to 10 −8 A / cm 2 , and the leak current increases and the dielectric constant decreases as the film thickness is further reduced. Furthermore, the CVD method uses a dangerous gas, which is not good for environmental health.

【0007】本発明は以上述べた問題点を解決するもの
であり、安全で簡便な物理的成膜法を用いて3次元構造
の電極上にカバレッジが高く特性もよい酸化物誘電体薄
膜からなるギガビットDRAM用キャパシターの形成技
術を提供するものである。
The present invention solves the above-mentioned problems and comprises an oxide dielectric thin film having high coverage and good characteristics on a three-dimensional electrode by using a safe and simple physical film formation method. An object of the present invention is to provide a technology for forming a capacitor for a gigabit DRAM.

【0008】[0008]

【課題を解決するための手段】本発明のキャパシター形
成技術は上記課題を解決するものであり、物理的成膜法
による3次元構造の電極上への酸化物誘電体薄膜からな
るキャパシターの形成技術において、基板と蒸着源を適
当な角度で対向させ、かつ成膜中基板を連続的に回転さ
せること、さらに基板と蒸着源が対向する適当な角度
は、基板の法線方向に対する蒸着源の位置が30〜80
°であることを特徴とする。
The capacitor forming technique of the present invention solves the above-mentioned problems, and is a technique of forming a capacitor comprising an oxide dielectric thin film on an electrode having a three-dimensional structure by a physical film forming method. In the above, the substrate and the evaporation source are opposed at an appropriate angle, and the substrate is continuously rotated during film formation. Further, the appropriate angle at which the substrate and the evaporation source face each other depends on the position of the evaporation source with respect to the normal direction of the substrate. Is 30 to 80
°.

【0009】また、本発明のキャパシター形成技術は、
物理的成膜法による3次元構造の電極上への酸化物誘電
体薄膜からなるキャパシターの形成技術において、成膜
中基板と蒸着源の対向する角度を連続的に変化させ、か
つ基板も連続的に回転させること、さらに成膜中連続的
に変化させる基板と蒸着源の対向する角度は、基板の法
線方向に対する蒸着源の位置が−90°〜90°以内で
あることを特徴とする。
Further, the capacitor forming technique of the present invention
In a technology for forming a capacitor composed of an oxide dielectric thin film on a three-dimensionally structured electrode by a physical film forming method, the angle between the substrate and the evaporation source facing the film is continuously changed during film formation, and the substrate is continuously formed. The angle between the substrate and the vapor deposition source, which is continuously changed during film formation, is characterized in that the position of the vapor deposition source with respect to the normal direction of the substrate is within −90 ° to 90 °.

【0010】[0010]

【発明の実施の形態】以下、本発明を実施例にしたがっ
て詳細に説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to embodiments.

【0011】(実施例1)図1は本発明の実施例1に用
いるキャパシターの断面構造を示す図である。基板1、
バッファー層2、金属層3および金属酸化膜層4からな
る下部電極構造、酸化物誘電体からなるキャパシター
5、上部金属電極6で構成される。
(Embodiment 1) FIG. 1 is a view showing a sectional structure of a capacitor used in Embodiment 1 of the present invention. Substrate 1,
It comprises a lower electrode structure composed of a buffer layer 2, a metal layer 3, and a metal oxide film layer 4, a capacitor 5 composed of an oxide dielectric, and an upper metal electrode 6.

【0012】以下に本構造の作製方法を説明する。基板
1にはSi基板を用い、その上にバッファー層2として
耐酸化性に優れているTi0.7Al0.3Nを窒素プ
ラズマを用いた反応性蒸着によりエピタキシャル成長さ
せる。この時の基板温度は600℃とする。次にその上
に、スパッタにより金属層3としてRuを形成する。続
いて、さらにその上にRuOをターゲットに用いたレ
ーザーアブレーション(以下PLD)法により金属酸化
膜層4のRuO膜を形成する。このとき成膜中RFラ
ジカルビームガンにより酸素ラジカルを基板に照射す
る。その後、O+CFを用いたドライエッチングに
より、RuO/Ruを図1のように加工し、3次元の
下部電極構造を形成する。
Hereinafter, a method of manufacturing the present structure will be described. An Si substrate is used as the substrate 1, and Ti 0.7 Al 0.3 N having excellent oxidation resistance is epitaxially grown on the Si substrate as a buffer layer 2 by reactive deposition using nitrogen plasma. At this time, the substrate temperature is 600 ° C. Next, Ru is formed thereon as the metal layer 3 by sputtering. Subsequently, a RuO 2 film of the metal oxide film layer 4 is further formed thereon by a laser ablation (PLD) method using RuO 2 as a target. At this time, the substrate is irradiated with oxygen radicals by an RF radical beam gun during film formation. Thereafter, RuO 2 / Ru is processed as shown in FIG. 1 by dry etching using O 2 + CF 4 to form a three-dimensional lower electrode structure.

【0013】続いて、物理的成膜法を用いてキャパシタ
ー5を形成する。ここでは、物理的成膜法として、PL
Dを用いる。PLDは成膜条件を合わせ込めば広い基板
温度範囲でターゲット組成と薄膜組成がほぼ一致するこ
とから、多元系の酸化物の成膜には有効な方法である。
キャパシター5を形成する酸化物誘電体としてはSBT
を用いる。SBTの組成は(Ba0.3Sr0.7)T
iOとし、蒸着源として該組成のSBTの単一ターゲ
ットを用いる。図2は基板11と蒸着源12の位置関係
を模式的に示す図である。基板11の法線方向と蒸着源
12であるターゲットの位置がなす角度をαとする。こ
の場合、基板11は図1におけるSi基板からRuO
層までを指し、蒸着源12はSBTの単一ターゲットを
指す。ここで、ターゲットの位置を固定し、基板11の
角度を変化させる。PLDで多元系酸化物薄膜を作製す
る場合、薄膜の組成比はレーザーエネルギーに依存す
る。レーザーとしてKrFエキシマレーザーを用い、α
=0°のときに薄膜のカチオンの組成比が±2%内とな
るレーザーエネルギーに設定する。基板温度を500℃
として、αを固定し、基板を連続的に回転させて20n
m成膜したときのBSTのカバレッジとαの関係を図3
に示す。なお、成膜中および冷却中は基板に酸素ラジカ
ルを照射している。これからわかるように、αが70℃
までは線形的に変化し、60℃でほぼ100%のカバレ
ッジとなる。αが45〜50°で熱CVDと同程度のカ
バレッジが、またαが30°でプラズマCVDと同程度
のカバレッジが得られている。αが50°以上では、熱
CVDでも得られないカバレッジが得られている。この
カバレッジの値はRuO/Ruの下部電極構造の高さ
にほとんど依存せず一定である。また、BSTの側面の
膜厚はほぼ均一であり、上面と側面の表面はαに依存せ
ずどちらも平坦である。さらに、上面の領域と側面の領
域のどちらの組成比もターゲットの組成比とほとんど変
化ない。
Subsequently, the capacitor 5 is formed by using a physical film forming method. Here, as the physical film forming method, PL
D is used. PLD is an effective method for forming a multi-component oxide film because the target composition and the thin film composition are almost the same over a wide substrate temperature range if the film formation conditions are adjusted.
SBT is used as an oxide dielectric for forming the capacitor 5.
Is used. The composition of the SBT is (Ba 0.3 Sr 0.7 ) T
iO 3 is used, and a single target of SBT having the composition is used as an evaporation source. FIG. 2 is a diagram schematically showing a positional relationship between the substrate 11 and the evaporation source 12. As shown in FIG. The angle between the normal direction of the substrate 11 and the position of the target as the evaporation source 12 is defined as α. In this case, the substrate 11 is made of RuO 2 from the Si substrate in FIG.
Up to the layer, source 12 refers to a single target of SBT. Here, the position of the target is fixed, and the angle of the substrate 11 is changed. When a multi-component oxide thin film is formed by PLD, the composition ratio of the thin film depends on the laser energy. Using KrF excimer laser as laser, α
The laser energy is set so that the composition ratio of cations in the thin film is within ± 2% when = 0 °. Substrate temperature 500 ℃
Is fixed, and the substrate is continuously rotated for 20 n
FIG. 3 shows the relationship between the coverage of BST and α when the m film was formed.
Shown in Note that the substrate is irradiated with oxygen radicals during film formation and cooling. As can be seen, α is 70 ° C.
, Changes linearly until reaching approximately 100% coverage at 60 ° C. When α is 45 to 50 °, the same coverage as that of thermal CVD is obtained, and when α is 30 °, the same coverage as that of plasma CVD is obtained. When α is 50 ° or more, a coverage that cannot be obtained by thermal CVD is obtained. The value of this coverage is almost independent of the height of the lower electrode structure of RuO 2 / Ru and is constant. The thickness of the side surface of the BST is substantially uniform, and both the upper surface and the side surface are flat independently of α. Furthermore, the composition ratio of both the upper surface region and the side region hardly changes from the composition ratio of the target.

【0014】ここで、平坦なRuO電極上に成膜した
膜厚20nmのBSTのteqはαが0〜80°までほ
ぼ一定で0.15nm程度であった。しかし、80°以
上では高くなってしまった。また、リーク電流密度J
もαが80°までは10―10A/cm台(@1V)
と良好な値を示した。一方、電極を3次元構造にして側
面の膜厚が20nmとしたBSTの側面でのteqは、
αが大きくなるに従い低下し、50°以上でほぼ飽和し
た。αが30°以上で0.25nm以下、さらにαが5
0°以上で約0.18nmであった。また、Jもt
eqと同様な傾向を示し、30°以上で10―9A/c
台(@1V)以下、50°以上で10―10A/c
台(@1V)と良好な値を示した。さらに比誘電率
εも最高で400を超える値が得られている。実膜厚を
10nmまで薄くしても、J とεはほとんど劣化し
ない。これらの結果は、誘電体薄膜の結晶性が良いこと
を示している。
[0014] Here, t eq flat RuO 2 of the formed film thickness 20nm on the electrode BST was 0.15nm about almost constant until α is 0 to 80 °. However, it was higher at 80 ° and above. Also, the leak current density J L
Up to 80 °, 10 -10 A / cm 2 units (@ 1V)
And a good value. On the other hand, t eq of the side of the BST film thickness of the side and the electrode on the three-dimensional structure has a 20nm is
It decreased as α increased, and became almost saturated at 50 ° or more. α is 30 ° or more and 0.25 nm or less, and α is 5
It was about 0.18 nm at 0 ° or more. Also, J L is t
It shows the same tendency as eq, and 10 −9 A / c at 30 ° or more.
m 2 units (@ 1V) or less, 10 −10 A / c at 50 ° or more
Two m and (@ 1V) showed good values. Further, the relative dielectric constant ε has a value exceeding 400 at the maximum. Also by reducing the real thickness up to 10nm, J L and ε is hardly deteriorated. These results indicate that the crystallinity of the dielectric thin film is good.

【0015】以上のカバレッジ、teq 、Jの結果
から、αは30〜80°が好ましく、より好ましくはα
が50〜80°の時であり、CVD以上のカバレッジ、
、Jが得られ、また、4ギガビットDRAM
で必要とされる容量値が実現できる。なお、ここでは、
酸化物誘電体としてBSTを用いたが、これ以外の材料
でもよく、また、RuO以下の構造および材料も上記
実施例に限るものではない。さらに、物理的成膜法もレ
ーザーアブレーション法以外のスパッタ法や蒸着法でも
問題無い。 (実施例2)本発明の実施例2におけるキャパシターの
形成技術の詳細を実施例1の図1、図2を用いて以下に
示す。
[0015] The above coverage, t eq, from the results of J L, alpha is preferably 30 to 80 °, more preferably alpha
Is 50 to 80 °, and the coverage is higher than CVD,
t e q, J L is obtained, 4Gb DRAM
And the required capacitance value can be realized. Here,
Although BST was used as the oxide dielectric, other materials may be used, and the structure and material of RuO 2 or less are not limited to the above-described embodiment. In addition, there is no problem with a physical film forming method other than the laser ablation method, such as a sputtering method or a vapor deposition method. (Embodiment 2) Details of a capacitor forming technique in Embodiment 2 of the present invention will be described below with reference to FIGS.

【0016】作製するキャパシターの断面構造は、図1
と同様である。すなわち、基板1、バッファー層2、金
属層3および金属酸化膜層4からなる下部電極構造、酸
化物誘電体からなるキャパシター5、上部金属電極6で
構成される。用いる材料も図1と同じとする。上記構造
の作製方法は、3次元の下部電極構造の形成まで実施例
1と同様である。物理的成膜法を用いた3次元の下部電
極上へのキャパシター5の形成は以下の通りである。
The cross-sectional structure of the capacitor to be manufactured is shown in FIG.
Is the same as That is, the lower electrode structure includes the substrate 1, the buffer layer 2, the metal layer 3, and the metal oxide film layer 4, the capacitor 5 formed of an oxide dielectric, and the upper metal electrode 6. The materials used are the same as those in FIG. The manufacturing method of the above structure is the same as that of the first embodiment up to the formation of the three-dimensional lower electrode structure. The formation of the capacitor 5 on the three-dimensional lower electrode using the physical film forming method is as follows.

【0017】物理的成膜法として、PLDを用いる。P
LDは成膜条件を合わせ込めば広い基板温度範囲でター
ゲット組成と薄膜組成がほぼ一致することから、多元系
の酸化物の成膜には有効な方法である。キャパシター5
を形成する酸化物誘電体としてはSBTを用いる。SB
Tの組成は(Ba0.3Sr0.7)TiOとし、蒸
着源として該組成のSBTの単一ターゲットを用いる。
図2に示すように、基板11の法線方向と蒸着源12で
あるターゲットの位置がなす角度をαとする。この場
合、基板11は図1におけるSi基板からRuO層ま
でを指し、蒸着源12はSBTの単一ターゲットを指
す。ここで、ターゲットの位置を固定し、基板11の角
度を変化させる。PLDで多元系酸化物薄膜を作製する
場合、薄膜の組成比はレーザーエネルギーに依存する。
レーザーとしてKrFエキシマレーザーを用い、α=0
°のときに薄膜のカチオンの組成比が±2%内となるレ
ーザーエネルギーに設定する。3次元構造上にBSTを
成膜する前に、平坦な電極上に基板温度を500℃とし
て、αをー90°〜90°の範囲で連続的に変化させ、
基板11も連続的に回転させBSTを20nm成膜し
た。なお、成膜中および冷却中は基板に酸素プラズマを
照射している。その結果、teqは0.20nm,J
は10―10A/cm台(@1V)と良好な値を示し
た。続いて、3次元電極上に同様に成膜中αを−90°
〜90°の範囲で連続的に変化させ、かつ基板も連続的
に回転させてキャパシターであるBSTを形成した。そ
の結果、BSTのカバレッジはαを変化させる速度に依
存することがわかった。すなわち、αを変化させる速度
を調整することによって、カバレッジをコントロールす
ることができる。そこで、αを変化させる速度を調整
し、カバレッジが約100%になるようにBSTを形成
した。その時の側面のBSTのteqは0.22nmと
良好であり、キャパシターとしてのJも10―10
/cm台(@1V)であった。これらの値は、CVD
で形成した場合よりも良い結果を示している。なお、カ
バレッジがCVDと同程度の80%としても、t
eq 、J はCVDの場合より良い。εも実施例1の
場合と同様最高で400を超える値が得られている。ま
た、実膜厚を10nmまで薄くしても特性の劣化はほと
んど見られない。すなわち、αを連続的に変えることに
より均一で結晶性の良いBST膜が得られている。以上
より、成膜中αを連続的に変化させ、かつ基板も連続的
に回転させることは、3次元電極構造上へのキャパシタ
ーの形成に効果的である。ギガビット級のDRAMに要
求される容量値を得ることができる。また、αを変化さ
せる速度だけでなく、αを振る角度範囲をー90°〜9
0°内で変えることによってもカバレッジをコントロー
ルでき、同様な効果が得られる。
PLD is used as a physical film forming method. P
LD is an effective method for forming a multi-component oxide film because the target composition and the thin film composition are almost the same over a wide substrate temperature range if the film forming conditions are adjusted. Capacitor 5
SBT is used as an oxide dielectric for forming the semiconductor. SB
The composition of T is (Ba 0.3 Sr 0.7 ) TiO 3, and a single target of SBT having the composition is used as a vapor deposition source.
As shown in FIG. 2, the angle between the normal direction of the substrate 11 and the position of the target which is the evaporation source 12 is defined as α. In this case, the substrate 11 indicates from the Si substrate to the RuO 2 layer in FIG. 1, and the deposition source 12 indicates a single target of SBT. Here, the position of the target is fixed, and the angle of the substrate 11 is changed. When a multi-component oxide thin film is formed by PLD, the composition ratio of the thin film depends on the laser energy.
Using KrF excimer laser as the laser, α = 0
The laser energy is set so that the composition ratio of the cations in the thin film is within ± 2% at the time of °. Before forming the BST film on the three-dimensional structure, the substrate temperature is set to 500 ° C. on the flat electrode, and α is continuously changed in the range of −90 ° to 90 °,
The substrate 11 was also continuously rotated to form a 20 nm BST film. During the film formation and during the cooling, the substrate is irradiated with oxygen plasma. As a result, t eq is 0.20 nm, J L
Showed a good value of 10 −10 A / cm 2 units (@ 1 V). Then, during film formation on the three-dimensional electrode, α is also -90 °.
The BST, which is a capacitor, was formed by continuously changing the substrate in the range of 9090 ° and continuously rotating the substrate. As a result, it was found that the coverage of BST depends on the speed of changing α. That is, the coverage can be controlled by adjusting the speed at which α is changed. Therefore, the speed of changing α was adjusted, and BST was formed so that the coverage became about 100%. T eq of BST side at that time is good and 0.22 nm, J L also 10 -10 A as capacitor
/ Cm 2 (@ 1 V). These values are
It shows better results than the case of forming with. Note that even if the coverage is 80%, which is almost the same as that of CVD, t
eq, J L is better than the case of CVD. As for ε, a value exceeding 400 at the maximum was obtained as in the case of Example 1. Even when the actual film thickness is reduced to 10 nm, almost no deterioration in characteristics is observed. That is, a BST film having uniformity and good crystallinity is obtained by continuously changing α. As described above, continuously changing α during film formation and continuously rotating the substrate are effective in forming a capacitor on the three-dimensional electrode structure. It is possible to obtain a capacitance value required for a gigabit DRAM. Further, not only the speed at which α is changed, but also the angle range at which α is changed is from −90 ° to 9 °.
The coverage can also be controlled by changing the angle within 0 °, and the same effect can be obtained.

【0018】なお、ここでは、酸化物誘電体としてBS
Tを用いたが、これ以外の材料でもよく、また、RuO
以下の構造および材料も上記実施例に限るものではな
い。さらに、物理的成膜法もレーザーアブレーション法
以外のスパッタ法や蒸着法でも問題無い。
Here, BS is used as an oxide dielectric.
T was used, but other materials may be used.
The structures and materials of 2 or less are not limited to the above-described embodiment. In addition, there is no problem with a physical film forming method other than the laser ablation method, such as a sputtering method or a vapor deposition method.

【0019】[0019]

【発明の効果】以上述べたように本発明によれば、物理
的成膜法による3次元構造の電極上への酸化物誘電体薄
膜からなるキャパシターの形成技術において、基板と蒸
着源を適当な角度で対向させ、かつ成膜中基板を連続的
に回転させること、さらに基板と蒸着源が対向する適当
な角度は、基板の法線方向に対する蒸着源の位置が30
〜80°であることにより、安全で簡便な物理的成膜法
でもカバレッジが高くギガビット級のDRAMに応用で
きる特性を有するキャパシター形成技術を提供すること
ができる。
As described above, according to the present invention, in a technology for forming a capacitor comprising an oxide dielectric thin film on an electrode having a three-dimensional structure by a physical film forming method, an appropriate substrate and an evaporation source are used. An appropriate angle at which the substrate and the deposition source face each other is such that the position of the deposition source with respect to the normal direction of the substrate is 30 degrees.
When the angle is 80 °, it is possible to provide a capacitor forming technique which has high coverage and can be applied to a gigabit-class DRAM even with a safe and simple physical film forming method.

【0020】また、本発明によれば、物理的成膜法によ
る3次元構造の電極上への酸化物誘電体薄膜からなるキ
ャパシターの形成技術において、成膜中基板と蒸着源の
対向する角度を連続的に変化させ、かつ基板も連続的に
回転させること、さらに成膜中連続的に変化させる基板
と蒸着源の対向する角度は、基板の法線方向に対する蒸
着源の位置が−90°〜90°以内であることにより、
安全で簡便な物理的成膜法でもカバレッジが高くギガビ
ット級のDRAMに応用できる特性を有するキャパシタ
ー形成技術を提供することができる。
According to the present invention, in a technology for forming a capacitor comprising an oxide dielectric thin film on an electrode having a three-dimensional structure by a physical film forming method, the angle between a substrate and a deposition source during film formation may be changed. Continuously changing, and also rotating the substrate continuously, furthermore, the angle between the substrate and the vapor deposition source that is continuously changed during the film formation is such that the position of the vapor deposition source with respect to the normal direction of the substrate is -90 ° or more. By being within 90 °,
It is possible to provide a capacitor formation technique having a high coverage and a property applicable to a gigabit-class DRAM even by a safe and simple physical film formation method.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例1に用いるキャパシターの断面
構造を示す図である。
FIG. 1 is a diagram showing a cross-sectional structure of a capacitor used in Example 1 of the present invention.

【図2】本発明の実施例1における基板と蒸着源の位置
関係を模式的に示す図である。
FIG. 2 is a diagram schematically showing a positional relationship between a substrate and an evaporation source in Embodiment 1 of the present invention.

【図3】本発明の実施例1における基板の法線方向と蒸
着源の位置がなす角度αとカバレッジの関係を示す図で
ある。
FIG. 3 is a diagram illustrating a relationship between an angle α formed by a normal direction of a substrate, a position of an evaporation source, and coverage in Example 1 of the present invention.

【符号の説明】[Explanation of symbols]

1 基板 2 バッファー層 3 金属層 4 金属酸化膜層 5 キャパシター 6 上部金属電極 11 基板 12 蒸着源 DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 Metal layer 4 Metal oxide film layer 5 Capacitor 6 Upper metal electrode 11 Substrate 12 Evaporation source

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 物理的成膜法による3次元構造の電極上
への酸化物誘電体薄膜からなるキャパシターの製造方法
において、基板と蒸着源を適当な角度で対向させ、かつ
成膜中基板を連続的に回転させることを特徴とするキャ
パシターの製造方法。
In a method of manufacturing a capacitor comprising an oxide dielectric thin film on an electrode having a three-dimensional structure by a physical film forming method, a substrate and an evaporation source are opposed at an appropriate angle, and A method for manufacturing a capacitor, comprising continuously rotating the capacitor.
【請求項2】 基板と蒸着源が対向する適当な角度は、
基板の法線方向に対する蒸着源の位置が30〜80°で
あることを特徴とする請求項1記載のキャパシターの製
造方法。
2. An appropriate angle at which the substrate and the evaporation source face each other is as follows:
2. The method according to claim 1, wherein the position of the evaporation source with respect to the normal direction of the substrate is 30 to 80 [deg.].
【請求項3】 物理的成膜法による3次元構造の電極上
への酸化物誘電体薄膜からなるキャパシターの製造方法
において、成膜中基板と蒸着源の対向する角度を連続的
に変化させ、かつ基板も連続的に回転させることを特徴
とするキャパシターの製造方法。
3. A method of manufacturing a capacitor comprising an oxide dielectric thin film on an electrode having a three-dimensional structure by a physical film forming method, wherein a facing angle between a substrate and a deposition source is continuously changed during film formation. A method for manufacturing a capacitor, wherein the substrate is also continuously rotated.
【請求項4】 成膜中連続的に変化させる基板と蒸着源
の対向する角度は、基板の法線方向に対する蒸着源の位
置が−90°〜90°以内であることを特徴とする請求
項3記載のキャパシターの製造方法。
4. The method according to claim 1, wherein the angle between the substrate and the evaporation source which is continuously changed during the film formation is within a range of -90 ° to 90 ° with respect to the normal direction of the substrate. 4. The method for producing a capacitor according to 3.
JP11001088A 1999-01-06 1999-01-06 Fabrication of capacitor Withdrawn JP2000200885A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11001088A JP2000200885A (en) 1999-01-06 1999-01-06 Fabrication of capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11001088A JP2000200885A (en) 1999-01-06 1999-01-06 Fabrication of capacitor

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Publication Number Publication Date
JP2000200885A true JP2000200885A (en) 2000-07-18

Family

ID=11491758

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100438781B1 (en) * 2001-12-05 2004-07-05 삼성전자주식회사 Metal - Insulator - Metal capacitor and Method for manufacturing the same
JP2006128643A (en) * 2004-09-30 2006-05-18 Tdk Corp Dielectric thin film, thin film dielectric element and its manufacturing method
TWI424533B (en) * 2009-07-02 2014-01-21 Micron Technology Inc Methods of forming capacitors
JP2015134943A (en) * 2014-01-16 2015-07-27 東京エレクトロン株式会社 substrate processing apparatus

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100438781B1 (en) * 2001-12-05 2004-07-05 삼성전자주식회사 Metal - Insulator - Metal capacitor and Method for manufacturing the same
JP2006128643A (en) * 2004-09-30 2006-05-18 Tdk Corp Dielectric thin film, thin film dielectric element and its manufacturing method
JP4682769B2 (en) * 2004-09-30 2011-05-11 Tdk株式会社 Dielectric thin film, thin film dielectric element and manufacturing method thereof
TWI424533B (en) * 2009-07-02 2014-01-21 Micron Technology Inc Methods of forming capacitors
JP2015134943A (en) * 2014-01-16 2015-07-27 東京エレクトロン株式会社 substrate processing apparatus

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