JP2000200839A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device and a manufacturing method thereof, where the memory device is high in W/E(writing/erasing) reliability, and the source diffusion layer of a memory cell is protected against damage when a source wiring is formed in a self-aligned manner. SOLUTION: A semiconductor memory device is equipped with an element isolating insulating film 112 formed on the surface of a substrate, a plurality of memory cells which are each provided with a source diffusion layer 102 formed in a region isolated by the element isolation insulating film 112, and a wiring layer 113 which interconnects the source diffusion layers 102 of the memory cells adjacent to each other interposing the element isolation insulating film 112 between them is provided under the element isolation insulating film 112. In the manufacturing method of this semiconductor memory device, a source wiring layer is formed under a field oxide film by implantation of ions with a high acceleration energy without a field oxide film removing process. Therefore, the memory cell can be protected against damage caused by etching of an oxide film, so that a semiconductor non-volatile memory excellent in characteristics can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a nonvolatile semiconductor memory and a method of manufacturing the same.

[0002]

2. Description of the Related Art There are many types of nonvolatile semiconductor memories. One example of a nonvolatile semiconductor memory cell that has been widely used in the past is a NOR type batch erase type EE having a two-layer structure.
FIG. 7 shows a cross-sectional structure taken in a direction orthogonal to the control electrodes of a PROM (hereinafter referred to as a flash EEPROM).

[0003] As shown in FIG.
The EPROM has a gate structure in which a first gate insulating film 4, a floating gate 5, a second gate insulating film 6, and a control gate 7 are sequentially stacked on a semiconductor substrate 1. The top and side surfaces of such a stacked gate structure are covered with a thermal oxide film 8. Source / drain diffusion layer regions 2 and 3 are provided on the substrate surface on both sides of the stacked gate structure.
Are formed alternately.

[0004] An interlayer insulating film 9 is deposited on the whole of these, and a contact hole 10 is opened in a portion corresponding to the source / drain region, and aluminum or the like is buried in the contact hole 10. Are formed, and the whole is protected by the deposited protective film 12.

FIG. 8 is a plan view of the nonvolatile semiconductor memory shown in FIG. FIG. 7 is a cross-sectional view taken along the line BB 'in FIG. A field oxide film 13 is formed on the surface of the semiconductor substrate 1 in the form of a stripe in the vertical direction in FIG. It is formed in a stripe shape so as to be orthogonal to oxide film 13.

In the diffusion layer for the source wiring, after the field oxide film 13 sandwiched between the drain diffusion layer regions 3 is removed by oxide film etching, impurity ions are implanted into the hatched regions in the figure. Accordingly, the self-aligned source diffusion layer (Self-Ali
gned Source 15).

[0007]

In such a self-alignment step, the field oxide film 13 is removed by etching using a patterned resist mask. However, the condition is such that the field oxide film is sufficiently removed. When the etching is performed, since the source diffusion layer region 2 has no oxide film on the surface, the surface of the Si substrate is also etched and is damaged. FIG. 9 is a cross-sectional view of the memory cell region after the field oxide film etching, taken along the line AA ′ in FIG. 8, FIG. 10 in the completed state of the device, and along the line BB ′ in FIG. FIG. 11 is a sectional view. As apparent from FIGS. 9 and 10, a damage layer 16 is formed on the surface of the substrate 1 on which the self-aligned source diffusion layer 15 is formed adjacent to the portion 14 from which the field oxide film 13 has been removed. Further, as is apparent from FIG. 11, the substrate surface is over-etched when the field oxide film is etched.
7 results.

After ion implantation into the source diffusion layer region 2 damaged as described above, a thermal oxidation step is performed.
There is a concern that the damage of the source diffusion layer region 2 may be extended to the channel region, which may adversely affect the cell characteristics, particularly, the reliability of repetition of write / erase (W / E).

Therefore, according to the present invention, the source diffusion layer of the memory cell is not damaged when the source wiring is formed, and the W / E
It is an object of the present invention to provide a highly reliable nonvolatile semiconductor memory and a method for manufacturing the same.

[0010]

According to a semiconductor memory device of the present invention, an element isolation insulating film formed on a surface of a semiconductor substrate and a source formed in a region separated by the element isolation insulating film, respectively. A plurality of memory cells having a diffusion layer, and a wiring layer interconnecting the respective source diffusion layers of adjacent memory cells with the element isolation insulating film interposed therebetween,
It is characterized by being formed below the element isolation insulating film.

According to the method of manufacturing a semiconductor memory device of the present invention, a step of forming an element isolation insulating film in a stripe shape on a surface of a semiconductor substrate, and a step of forming a first gate insulating film in a region between the element isolation films. Forming a film, depositing a gate electrode material over the entire surface of the substrate, and selectively forming a floating gate, and performing thermal oxidation to form a second gate insulating film on the floating gate. Depositing a gate electrode material over the entire surface of the substrate and selectively forming a control gate orthogonal to the device isolation film; performing a first ion implantation using the control gate as a mask to form source and drain diffusion regions; Forming, and a product comprising the first insulating film, the floating gate, the second gate insulating film, and the control gate. Depositing an insulator serving as a side wall on the side surface of the structure, selectively forming a resist mask exposing a region corresponding to a wiring layer connecting source diffusion regions of each memory cell, and masking the resist mask And a second ion implantation step of implanting an impurity of the same conductivity type as the first ion implantation under the condition of passing through the element isolation film.

According to the semiconductor memory device and the method of manufacturing the same, the wiring layer connecting the source diffusion layers is passed under the element isolation film. There is no need to remove the separation film, and the characteristics of the memory cell do not deteriorate.

[0013]

1 to 6 show an embodiment of the present invention.
This will be described with reference to FIG. FIG. 1 is a sectional view in the gate width direction of a nonvolatile semiconductor memory cell according to the present invention. This figure shows a cross section taken along the line EE 'of FIG. 4, which will be described later. The gate wiring that cannot be directly seen is represented by an imaginary line.

As in the case of the prior art, this memory device includes a first gate insulating film 104, a floating gate 105, a second gate insulating film 106 in a region sandwiched between field oxide films 112 on a semiconductor substrate 101. The control gate 107 has a gate structure in which layers are sequentially stacked. On the substrate surface portions on both sides of the field oxide film 112,
Although the source / drain diffusion layer regions 102 are alternately formed, FIG. 1 shows a portion corresponding to the source diffusion region in FIG. The source diffusion layers 102 are electrically connected to each other by an impurity diffusion layer 113 for source wiring, which is formed thereunder and below the field oxide film 112. Thus, in this embodiment, the field oxide film 112 is not removed.

Next, a method of manufacturing such a semiconductor memory device will be described with reference to FIGS. FIG. 2 corresponds to the section taken along line FF ′ of FIG.

First, a well (not shown) is formed in the semiconductor substrate 101 as necessary, and then a LOCOS method, which is a selective oxidation method using a nitride film as an oxidation-resistant film, is used.
A field oxide film 112 is formed (FIG. 2A).

Then, after ion implantation into a channel region, thermal oxidation is performed to form a thermal oxide film 104 serving as a gate insulating film on the surface of the semiconductor substrate.
Deposit 0.1 μm by VD method (FIG. 2B).

Next, patterning is performed so that the polysilicon film 105 is separated on the field oxide film 112. On this, a second gate insulating film 106 is formed with a thickness of 160 nm (FIG. 2C). The second gate insulating film 106 has a so-called ONO structure including an oxide film (SiO ₂ ), a nitride film (SiN), and an oxide film (SiO ₂ ).

Next, a structure shown in FIG. 1 is obtained by depositing a polysilicon film 107 serving as a control gate to a thickness of 0.2 μm by the CVD method.

Note that the control gate 107 is
Although a two-layer structure such as oSi / polysilicon is mainly used, recently, a four-layer structure of SiO ₂ 116 / SiN 115 / WSi and polysilicon 107 may be used.

The laminated electrode thus formed is patterned into a predetermined shape by patterning a resist and etching such as RIE.

Next, after post-oxidation, the gate electrode 10
7 is used as a mask to perform ion implantation for forming the source / drain diffusion region 102. The ion implantation conditions at this time are as follows.
The implantation is performed at 0 keV and a dose of 6 × 10 ¹⁵ / cm ² . At the time of this ion implantation, the field oxide film 112 functions as an ion implantation mask, and the ions are not implanted below the field oxide film 112. Therefore, the source diffusion region 102 of each memory cell is separated by the field oxide film 112. Note that these separated source diffusion regions 102
Will eventually be all common, as described below.

FIG. 5 is a cross-sectional view taken along the line CC 'without a field oxide film in the plan view of FIG. 4, and FIG. 6 is a cross-sectional view taken along a line DD' with a field oxide film.

As shown in FIG. 5 and FIG. 6, SiO ₂ is deposited on the entire surface around the stacked gate structure,
7 is formed. This side wall is for forming a known LDD structure. The stacked gate structure shown here has a four-layer structure as described above, and includes a silicon oxide film (SiO ₂ ) 116 and a silicon nitride film (SiN) 1.
15.

The hatched portion in FIG.
Reference numeral 20 denotes a pattern which is formed so as to mask a portion other than a portion corresponding to a region where a source wiring layer is to be formed.

By using such a resist pattern 120, an impurity of the same kind as that of the source diffusion layer is ion-implanted to form a source wiring layer 122 under the field oxide film 112. In this case, as shown in FIG. 6, field oxide film 112 having a thickness of 250 nm separating source diffusion layer regions.
In order to form the impurity diffusion layer under the side walls 117 having a thickness of 150 nm, the ion implantation conditions need to have an acceleration energy of 700 keV or more. When ion implantation is performed such high acceleration energy, the impurity in the interior of the control gate and floating gate may be injected is concerned, FIG. 5, SiO ₂ on the control gate as shown in FIG. 6 Film 116 and SiN film 11
If 5 is deposited to a sufficient thickness, for example, about 350 nm, impurity implantation can be prevented. After the deposition of the side wall 117, the silicon oxide film also has a masking function on the gate cross section of the cell.
05 can be prevented from being implanted (FIG. 5).

In the case of FIG. 5, ion implantation is also performed at a high acceleration energy to the source diffusion layer 102 of the already formed cell to form a further enlarged diffusion layer 121. Therefore, no particular problem occurs. By this ion implantation, the source diffusion layer regions 102 and 121 formed in the active region and the impurity diffusion layer region 122 formed below the field oxide film are electrically connected, and can be used as a common source diffusion layer region.

Thereafter, the resist is removed, and a normal LDD
A sidewall is formed, and a diffusion layer of a MOSFET in a peripheral circuit portion is formed.

Thereafter, well-known electrode formation, wiring, protection film formation, and the like are performed to complete the semiconductor memory device.

As described above, according to the embodiment of the present invention, it is possible to form the common source diffusion layer without etching the field oxide film as in the related art, thereby preventing the characteristic deterioration of the memory cell. I can do it.

In the embodiment described above, the laminated gate structure, material, and the like can be appropriately changed.

[0032]

According to the semiconductor memory device and the method of manufacturing the same of the present invention, the source wiring layer is formed under the field oxide film by ion implantation with high acceleration energy without going through the step of removing the field oxide film. Therefore, since the memory cells are not damaged by the field oxide film etching, a semiconductor nonvolatile memory having good characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a nonvolatile semiconductor memory cell according to the present invention.

FIG. 2 is a cross-sectional view illustrating a step of obtaining a stacked gate structure according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a state of forming a source diffusion region in the present invention.

FIG. 4 is a plan view of an ion implantation mask for forming a source wiring according to the present invention.

FIG. 5 is a cross-sectional view showing a state of ion implantation for forming a source wiring in the present invention.

FIG. 6 is a sectional view showing a state of ion implantation for forming a source wiring in the present invention.

FIG. 7 shows a typical FLASH conventionally used.
FIG. 3 is a sectional view of a memory cell of the EEPROM.

8 is a plan view of a conventional memory cell corresponding to FIG.

FIG. 9 is a cross-sectional view taken along the line AA ′ of FIG. 8 for explaining removal of a field oxide film in a conventional memory cell and a problem associated therewith.

FIG. 10 is a diagram showing an element completed state of the same part as FIG. 9;
It is A 'sectional drawing.

FIG. 11 is a sectional view taken along the line BB ′ of FIG. 8 for explaining another problem associated with the removal of the field oxide film in the conventional memory cell.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1, 101 Semiconductor substrate 2, 102 Source diffusion layer region 3 Drain diffusion layer region 4, 104 First gate insulating film 5, 105 Floating gate 6, 106 Second gate insulating film 7, 107 Control gate 8 Post oxide film 9 Interlayer insulation Film 10 Contact hole 11 Wiring 12 Protective film 13, 112 Field oxide film 14 Field oxide film removed portion 15 Source diffusion layer by self-alignment 16 Damage layer 17 Step 115 SiN 116 SiO ₂ film 117 SiO ₂ film 120 Resist 121 Source diffusion layer 122 source wiring layer

Claims (3)

[Claims] A plurality of memory cells each including a device isolation insulating film formed on a surface of a semiconductor substrate, a source diffusion layer formed in a region separated by the device isolation insulating film, and the device isolation insulating film. A semiconductor memory device, wherein a wiring layer for interconnecting source diffusion layers of memory cells adjacent to each other is formed below the element isolation insulating film. 2. The semiconductor memory device according to claim 1, wherein said wiring layer is an impurity diffusion layer of the same conductivity type as said source diffusion layer. 3. A step of forming an element isolation insulating film in a stripe shape on a surface of a semiconductor substrate; a step of forming a first gate insulating film in a region between the element isolation films; Depositing and selectively forming a floating gate; performing thermal oxidation to form a second gate insulating film on the floating gate; depositing a gate electrode material over the entire surface of the substrate; Selectively forming a control gate perpendicular to the isolation film; performing first ion implantation using the control gate as a mask to form source and drain diffusion regions; and forming the first insulating film and the floating gate. Depositing an insulator serving as a side wall on a side surface of a stacked structure including a gate, the second gate insulating film, and the control gate; Selectively forming a resist mask that exposes a region corresponding to a wiring layer connecting a source diffusion region of the memory cell; and performing the first ion implantation under conditions that the resist mask is used as a mask and passes through the element isolation film. And a second ion implantation step of implanting impurities of the same conductivity type. A method for manufacturing a semiconductor memory device, comprising: