JP2000200788A - Structure of fine semiconductor element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure of a fine semiconductor element for realizing a hyperfine wiring and a semiconductor element in nano-meter order. SOLUTION: A structure 6 of a fine semiconductor element includes a semiconductor substrate 1, a semiconductor projected part 4 formed continuously according to a desired pattern with an epitaxial relation with the semiconductor substrate 1, and a metallic layer 5 selectively mounted on the semiconductor projected part 4. As an example, a plurality of metallic super-minute particles 2 are arranged according to a desired pattern on the semiconductor substrate 1 and treated by heat in a vacuum atmosphere. After a constituent element of the semiconductor substrate 1 is put in a solid solution state (or further melted) into the metallic hyperfine particles 2, the semiconductor substrate 1 is put in a gradually cooling treatment so that the constitutent element of the semiconductor substrate 1 is separated by sedimentation from the solid solution phase (liquid phase) and grown during the sedimentation. In this way, the structure of a minute semiconductor element can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure for a fine semiconductor device capable of realizing a nano-order ultrafine wiring or a semiconductor device portion, and a method for manufacturing the same.

[0002]

2. Description of the Related Art The degree of integration of semiconductor devices represented by DRAMs is increasing year by year. For example, the degree of integration of DRAMs has increased from 16 Mbits to 64 Mbits and 256 Mbits, and the development of semiconductor devices having an integration degree of Gbits or more has been advanced. Such high integration of semiconductor devices has been achieved by reducing the unit element size to the order of submicrons. Advances in lithography technology have greatly contributed to the miniaturization of unit element sizes. In addition to improving lithography technology,
Improvements in the element structure are also being made.

Regarding lithography technology, for example,
With the development of an exposure technique using a KrF excimer laser complying with the 25 μm rule, a 64 Mbit-DRAM has been mass-produced and a 256 Mbit-DRAM has been put into practical use. In addition, the improvement of the exposure technology using the KrF excimer laser supports the 0.18 μm rule,
Exposure technology using SOR light is being developed. However, with current lithography technology, 0.1
The μm rule is the limit. Therefore, in order to achieve higher integration, it is desired to realize a unit element size and a wiring width on the order of nanometers in the future.

On the other hand, quantum size devices will be used in future LS
It is expected to be a candidate for I technology. For example, quantum size effects such as quantum wire devices and quantum box devices using thin wires or box structures whose cross-sectional dimensions are comparable to the quantum mechanical wavelength of electrons, resonance tunnel effect devices and resonance tunnel devices using quantum wells, etc. Attempts have been made to realize new devices by utilizing the tunnel effect and the tunnel effect.

In order to develop a new device by actively utilizing the quantum effect, the characteristic dimensions of the device must be adjusted to the phase wavelength (0.1%).
It is important to bring them to the order of electron wavelength (10 to 100 nm), that is, the nanoscopic region, without being limited to the order of 1 μm, that is, the microscopic region. Furthermore, in order to use the quantum effect device more effectively, the unit element size and the wiring width are, for example, 10 to 100 nm,
Further, it is necessary to reduce the size to 10 nm or less. However, the current lithography technology cannot achieve this at all.

Further, recently, ultrafine particles have been applied to quantum size devices and the like. However, even if ultrafine particles can be obtained as a single particle in the conventional manufacturing method, the formation position is not sufficient. Can not be controlled. Therefore, it is extremely difficult to obtain ultrafine wiring or ultrafine devices using ultrafine particles with good reproducibility. Furthermore, the mere use of ultrafine particles cannot sufficiently enhance, for example, interface matching with a semiconductor substrate.

[0007]

As described above, research and development on ultra-high-integration semiconductor devices and quantum-size devices, which are expected as candidates for future LSI technology, are underway. In order to realize such an ultrafine device, it is necessary to achieve a unit element size and a wiring width on the order of nanometers. For this reason, there is a demand for the emergence of an ultrafine wiring technology that can achieve a wiring rule on the order of nanometers in realizing an ultra-highly integrated semiconductor device or a quantum size device.

An object of the present invention is to provide a structure for a fine semiconductor element capable of realizing a nano-order ultrafine wiring, a semiconductor element portion, and the like, and a method of manufacturing the same, which have been made to address such problems. It is an object.

[0009]

According to a first aspect of the present invention, there is provided a structure for a fine semiconductor device, wherein the structure is formed on a semiconductor substrate and has an epitaxial relationship with the semiconductor substrate. The semiconductor device further comprises a semiconductor protrusion having a continuous shape grown according to a desired pattern and a metal layer selectively disposed on the semiconductor protrusion.

In the structure for a fine semiconductor device according to the present invention, the semiconductor projection may be, for example,
The projection has a trapezoidal cross section and a maximum width of 100 nm or less. Further, as the constituent element of the metal layer, as described in claim 3, a constituent element which forms a solid solution with the constituent element of the semiconductor substrate in a high temperature region and is substantially separated in a low temperature region is used.

According to a seventh aspect of the present invention, there is provided a method for manufacturing a structure for a fine semiconductor element, wherein a plurality of ultrafine metal particles are continuously arranged on a semiconductor substrate according to a desired pattern. Heat-treating the semiconductor substrate in which the plurality of metal ultra-fine particles are arranged in a vacuum atmosphere to dissolve or dissolve constituent elements of the semiconductor substrate in the metal ultra-fine particles; and Is subjected to a slow cooling process, the constituent elements of the semiconductor substrate are sedimented and separated from the solid solution / liquid phase and epitaxially grown on the semiconductor substrate to form a semiconductor projection having a continuous shape on the semiconductor substrate. And forming a metal layer separated from the semiconductor protrusion on the semiconductor protrusion.

In the method of manufacturing a structure for a fine semiconductor element according to the present invention, the step of arranging the plurality of ultrafine metal particles has a slit according to a desired pattern on the semiconductor substrate. Place the target material,
This is performed by irradiating the inner wall of the slit with a high-energy beam from an oblique direction to separate constituent atoms or constituent molecules of the target material. According to such a process, a plurality of metal ultrafine particles can be arranged in a desired pattern with good reproducibility.

In the present invention, constituent atoms of a semiconductor substrate are dissolved in ultrafine metal particles in a vacuum atmosphere with respect to a semiconductor substrate on which a plurality of ultrafine metal particles are arranged according to a desired wiring pattern or the like. Heat treatment is performed at a temperature higher than a temperature at which a liquid phase in which constituent atoms of the semiconductor substrate and the metal ultrafine particles are uniformly dissolved is formed. By gradually cooling from such a state, that is, a state in which a solid solution phase or a liquid phase (solid solution / liquid phase) is formed, constituent elements of the semiconductor substrate are precipitated from the solid solution / liquid phase state.

By the precipitation from such a solid solution / liquid phase state, the constituent elements of the semiconductor substrate grow epitaxially on the semiconductor substrate, and the constituent elements of the semiconductor substrate and the ultrafine metal particles are separated. Therefore, a semiconductor protrusion having a continuous shape epitaxially grown on a semiconductor substrate can be formed according to the initial arrangement positions of the plurality of ultrafine metal particles. Further, after the constituent elements of the semiconductor substrate are precipitated and precipitated, the constituent elements of the ultrafine metal particles remain as a metal layer on the semiconductor protrusions. Accordingly, a structure for a fine semiconductor element having a heterojunction interface between a semiconductor layer (semiconductor projection) having a continuous shape and a metal layer can be obtained.

The semiconductor projection has, for example, a trapezoidal cross section. This trapezoidal semiconductor projection has a maximum width of, for example, 100 nm depending on the size of the initial metal ultrafine particles.
It can be: The width of the metal layer existing above the semiconductor protrusion can be substantially the same. In addition,
By removing the upper metal layer, only the semiconductor protrusion can be obtained. According to such a structure for a fine semiconductor element, it is possible to realize a nano-order unit element size and a wiring width required for, for example, an ultra-highly integrated semiconductor device and a quantum size device.

[0016]

Embodiments of the present invention will be described below.

FIG. 1 and FIG. 2 are diagrams schematically showing one embodiment of a manufacturing process of a structure for a fine semiconductor device of the present invention. FIG. 2 is a diagram showing a cross section taken along line XX of FIG. First, as shown in FIGS. 1A and 2A, a plurality of metal ultrafine particles 2 are continuously arranged on a semiconductor substrate 1 according to a desired pattern.

As the semiconductor substrate 1 and the ultrafine metal particles 2,
A combination that exhibits an endothermic reaction thermodynamically, that is, a combination in which the solid solubility limit is large in a high temperature range but the solid solubility limit is greatly reduced in a room temperature range is used. For example, when a Si substrate is used as the semiconductor substrate 1, Au, Ag, Cu, Al, or the like may be used as a constituent material of the ultrafine metal particles 2. Of these, Au, Ag, and Cu, which have a particularly high solid solubility in Si and a high diffusion coefficient, are preferably used. When a Ge substrate is used as the semiconductor substrate 1, Zn, Cd, Au, Ag, Al, or the like is used as a constituent material of the metal ultrafine particles 2.

In forming the ultrafine metal particles 2, the surface of the semiconductor substrate 1 is preferably kept sufficiently clean.
A plurality of ultrafine metal particles 2 are formed on the surface of the semiconductor substrate 1 under reduced pressure or vacuum, for example. The method for forming the metal ultrafine particles 2 is not particularly limited, but a method capable of forming the metal ultrafine particles 2 on the semiconductor substrate 1 in a normal temperature state is applied. When the ultrafine metal particles 2 are formed on the semiconductor substrate 1 in a heated state, a reaction layer or the like is formed at the interface between the semiconductor substrate 1 and the ultrafine metal particles 2, which may adversely affect subsequent steps.

Incidentally, the surface of the semiconductor substrate 1 may be covered in advance with a coating layer made of a material which does not hinder the diffusion of atoms. Such a coating layer can also function as an electron barrier after forming the semiconductor protrusion 4.

As a method for forming the plurality of ultrafine metal particles 2, for example, a method as shown in FIG. 3 is preferably applied. That is, first, as shown in FIG. 3A, a target material 11 serving as a raw material for forming ultrafine particles is formed on a semiconductor substrate 1.
Place. As shown in FIG. 4, the target material 11 has a slit 12 corresponding to the target shape of the metal ultrafine particles 2, and a high-energy beam is applied to an inner wall 13 of the slit 12 as described later. 14 is irradiated from above in an oblique direction, and a plurality of metal ultrafine particles 2 are formed by the oblique irradiation of the high energy beam 14.

The shape of the slit 12 is not limited to a linear shape as shown in FIG. 4, but may be a shape having a bent portion as shown in FIG. 5, for example, or a slit having a more complicated shape. It is also possible to apply 12.
As such a target material 11, a material in which a slit 12 is formed on a film made of a desired metal material by a chemical method such as etching or an electrochemical method, or a slit 12 formed by a laser beam or the like is used. can do. The target material 11 used is
It is not limited to one, and a plurality of target materials can be used in combination.

As the target material 11, various metal materials selected according to the above-described semiconductor substrate 1 are used. Here, various conditions are the impact resistance of the target material 11 to the high energy beam 14, in other words, the target material 1
The setting is made in consideration of the detachability of the constituent atoms from the target material 11, which is almost determined by the binding energy of the crystal 1.

The slits 12 of the target material 11 provide a position for forming the plurality of ultrafine metal particles 2, and the inner wall 13 serves as a material for forming the ultrafine metal particles 2, that is, a supply surface of constituent atoms of the target material 11. Therefore, the shape of the slit 12 and the thickness of the target material 11 are set in consideration of the shape and the arrangement position of the metal ultrafine particles 2 to be formed, the incident angle θ of the high energy beam 14, and the like. Specifically, the width w of the slit 12 in the direction parallel to the irradiation direction of the high energy beam 14 is 0.1 to 10
It is preferable that the thickness t of the target material 11 is about 0.1 to 100 μm.

The width w of the slit 12 and the thickness t of the target material 11 affect the incident angle θ of the high energy beam 14. The incident angle θ of the high energy beam 14 is
For example, in order to obtain the ultrafine metal particles 2 having a diameter of about 100 nm or less, it is preferable to set the angle to be in the range of 15 to 60 °.
The thickness t of ¹ is preferably set so that tan ^-1 (t / w) is in the range of 15 to 60 °. More preferably, the width w of the slit 12 and the thickness t of the target material 11 are set so that tan ^-1 (t / w) is in the range of 30 to 45 °.

As shown in FIG. 3B and FIG. 6, a high energy beam 14 is applied to the slit inner wall 13 of the target material 11 from an oblique direction from above. The oblique irradiation of the high energy beam 14 may be performed simultaneously (collectively) on the entire inner wall 13 of the slit, or the high energy beam 14 having a reduced beam diameter may be used.
May be repeatedly and continuously irradiated along the slit inner wall 13.

Further, a high-energy beam 14 is obliquely applied to a certain position of the slit inner wall 13 until the ultrafine metal particles 2 having a desired diameter are formed on the semiconductor substrate 1, and then irradiated in the longitudinal direction of the slit 12. Similarly, by shifting the position, the high energy beam 14
Irradiation is performed continuously along the shape of the slit 12, and various irradiation modes can be adopted.

The oblique irradiation of the slit inner wall 13 with the high energy beam 14 causes the target material 1
The constituent atoms of 1 depart from each other (indicated by dotted arrows in the figure), and these adhere to the semiconductor substrate 1 to form the ultrafine metal particles 2.

Here, the high energy beam 14 to be irradiated
Is not particularly limited as long as it has an energy capable of releasing constituent atoms from the target material 11. For example, acceleration voltage 2-5kV, beam current 0.1-1mA
An ion beam such as an argon ion beam of a certain degree, an electron beam, a laser beam, an X-ray, a γ-ray, and a neutron beam capable of giving the same impact to the target material 11 as the ion beam are exemplified. The irradiation atmosphere of the high energy beam 14 may be set according to the beam to be used, and examples thereof include a vacuum atmosphere and an inert atmosphere such as an argon atmosphere.

The above-described oblique irradiation of the high-energy beam 14 is continued for a certain period of time to continuously separate constituent atoms from the target material 11, whereby the metal ultrafine particles 2 are grown to a target shape. Here, the individual size of the metal ultrafine particles 2 is determined by the semiconductor substrate 1 during the heat treatment as described later.
Any size may be used as long as semiconductor atoms (e.g., Si atoms) diffusing on the surface of the semiconductor substrate can be taken in and a semiconductor-metal solid solution phase can be formed.
The diameter of the ultrafine metal particles 2 is preferably 100 nm or less, more preferably 50 nm or less.

By forming the above-described metal ultrafine particles 2 simultaneously or continuously on the entire inner wall 13 of the slit, as shown in FIG. The metal ultrafine particles 2 can be continuously arranged. In addition, even when the high energy beam 14 is sequentially irradiated along the slit inner wall 13, by controlling each irradiation position of the high energy beam 14, the plurality of ultrafine metal particles 2 can be continuously arranged in a desired shape. .

The plurality of metal ultrafine particles 2 formed by oblique irradiation of the high energy beam 14 are, for example, shown in FIG.
As shown in (d), by irradiating the whole with, for example, an electron beam 15, it is also possible to fuse the adjacent metal ultrafine particles 2 with each other. By using such a metal ultrafine particle fusion body 16, it is also possible to form a semiconductor projection described later. The electron beam 15 used for fusion between the ultrafine metal particles 2 preferably has an intensity of, for example, 1 × 10 ¹⁹ e / cm ² · sec or more.

After the plurality of ultrafine metal particles 2 are continuously arranged on the semiconductor substrate 1 by the above-described process, the temperature is higher than the temperature at which the constituent atoms of the semiconductor substrate 1 are dissolved or dissolved in the ultrafine metal particles 2 in a vacuum atmosphere. Heat treatment at a temperature of As shown in FIG. 2B, when the semiconductor substrate 1 on which the ultrafine metal particles 2 are arranged is subjected to a heat treatment in a vacuum atmosphere, for example, the constituent atoms 1a of the semiconductor substrate 1 Fast diffusion occurs. The diffusion atoms (semiconductor atoms) 1a are taken into the ultrafine metal particles 2, and a semiconductor-metal solid solution phase and a semiconductor-metal liquid phase are formed.

The heat treatment is preferably carried out at a temperature not lower than a temperature at which a liquid phase in which the ultrafine metal particles 2 and the semiconductor atoms 1a are uniformly dissolved is formed.
A liquid phase 3 of the metal is obtained. The heat treatment temperature is set at the semiconductor substrate 1
When eutectic is formed between the metal and the ultrafine metal particles 2, it is preferable that the eutectic temperature be at least the eutectic temperature or higher. In any case, the temperature may be higher than the temperature at which the semiconductor-metal solid solution / liquid phase 3 is formed. The state of the semiconductor-metal phase is preferably a liquid phase, but may be a pseudo liquid phase in which semiconductor atoms and metal atoms are in a solid solution state and diffuse (move) at high speed. .

After the semiconductor-metal solid solution / liquid phase 3 is formed, it is gradually cooled. As shown in FIG. 2C, in the slow cooling process, the constituent atoms of the semiconductor substrate 1 are changed from the semiconductor-metal solid solution / liquid phase 3 to the solid-solution / liquid phase 3 between the semiconductor solution 1 and the semiconductor substrate 1. It precipitates at the liquid interface and further precipitates while maintaining an epitaxial relationship with the semiconductor substrate 1. The sedimentation and precipitation of the constituent atoms of the semiconductor substrate 1 are carried out by the semiconductor-metal solid solution
It is considered to be based on the size effect, heat treatment temperature, cooling rate and the like. The cooling rate varies depending on the constituent materials and the like, but is preferably about 2 ° C./min or less.

As described above, the constituent atoms of the semiconductor substrate 1 gradually settle out of the semiconductor-metal solid solution / liquid phase 3 and precipitate while maintaining an epitaxial relationship with the semiconductor substrate 1. A semiconductor layer 4 'grows between the solution / liquid phase 3 and the semiconductor substrate 1 in a projecting manner. That is, the constituent atoms of the semiconductor substrate 1 are grown by liquid phase epitaxy from the semiconductor-metal solid solution / liquid phase 3. On the semiconductor substrate 1, a protruding semiconductor layer 4 'is gradually formed.
The growth of the protruding semiconductor layer 4 ′ depends on each metal ultrafine particle 2.
Occur collectively when they are arranged in contact with each other, and occur individually when the metal ultrafine particles 2 are arranged apart from each other.

By terminating the precipitation of semiconductor atoms from the semiconductor-metal solid solution / liquid phase 3 in the cooling step, as shown in FIGS. 1 (b) and 2 (d), the metal matrix ( A semiconductor protrusion 4 having a continuous shape almost completely separated from the metal ultrafine particles 2) is formed.
On the other hand, the plurality of ultrafine metal particles 2 remain as the metal layer 5 above the semiconductor protrusion 4. In this manner, the structure 6 for a fine semiconductor element having a two-layer structure of the semiconductor protrusion 4 having a continuous shape and the metal layer 5 selectively disposed on the semiconductor protrusion 4 is formed on the surface of the semiconductor substrate 1. Can be formed.

The semiconductor projection 4 and the metal layer 5 in the structure 6 for a fine semiconductor element can be almost completely separated from each other. As shown in FIG. 7, the overall shape of the semiconductor projection 4 can be a continuous shape according to the initial arrangement positions of the plurality of ultrafine metal particles 2. In other words, by arranging the initial plurality of ultrafine metal particles 2 according to a desired pattern, it is possible to obtain a semiconductor projection 4 having a continuous shape grown according to the desired pattern.

When the plurality of metal ultrafine particles 2 are arranged apart from each other, as shown in FIG. 8, the semiconductor projection 4 has a partially concave shape, in other words, a truncated conical shape. It becomes a continuous shape as if only the skirt part of the projection was fused. In this case, the metal layer 5 is formed discontinuously on the semiconductor protrusion 4.

The cross section of the semiconductor projection 4 in the width direction is a projection having a substantially trapezoidal cross section because the semiconductor atoms gradually precipitate and grow from the semiconductor-metal solid solution / liquid phase 3 and grow. The semiconductor projection 4 has a cross-sectional shape such that the maximum width is 100 nm or less and the minimum width is about 50 nm or less according to the size of the metal ultrafine particles 2 at the beginning. Further, the metal layer 5 has a shape (substantially triangular in cross section) having a width substantially similar to the minimum width of the semiconductor protrusion 4, for example.

By forming a coating layer such as a surface oxide layer on the surface of the semiconductor substrate 1 on which the plurality of ultrafine metal particles 2 are disposed, except for the position where the ultrafine metal particles 2 are disposed.
The surface diffusion of the semiconductor atoms 1a is suppressed. In such a case, the supply of the semiconductor atoms 1a to the metal ultrafine particles 2 is limited, and the constituent atoms of the semiconductor substrate 1 and the constituent atoms of the metal ultrafine particles 2 interdiffuse only through their interface in the heat treatment step. I do. The semiconductor-metal solid solution / liquid phase 3 may be formed by such a method.

After forming the fine semiconductor element structure 6 having a two-layer structure of the semiconductor projection 4 having a continuous shape and the metal layer 5, an electron barrier is formed at the interface between the semiconductor projection 4 and the semiconductor substrate 1. It can also be formed. For example, before disposing the metal ultrafine particles 2, a coating layer that does not hinder the mutual diffusion between the constituent atoms of the electron barrier and the constituent atoms of the metal ultrafine particles 2 is formed on the surface of the semiconductor substrate 1. Can be obtained. Further, after forming the semiconductor protrusion 4, a material which is liable to diffuse at the interface is arranged around the semiconductor protrusion 4 (for example, as the above-described coating layer), and such a material is diffused between the semiconductor protrusion 4 and the semiconductor substrate 1. May be formed.

As described above, by applying the manufacturing method of the present invention, for example, the maximum width is set to 100 nm or less (or 50 nm or less) at a position corresponding to a desired pattern on the surface of the semiconductor substrate 1.
nm or less) and a continuous semiconductor projection 4 selectively epitaxially grown with respect to the semiconductor substrate 1 can be formed. Further, the semiconductor projection 4 is selectively disposed on the semiconductor projection 4, and A metal layer 5 that is almost completely separated from 4 can be arranged. In other words, a two-layered structure for a fine semiconductor element 6 having a semiconductor / metal heterojunction interface almost completely separated is obtained.

The arrangement shape (arrangement pattern) of the semiconductor protrusions 4 on the surface of the semiconductor substrate 1 can be controlled by arranging a plurality of metal ultrafine particles 2 in accordance with a desired pattern. Further, the width of the semiconductor projection 4 can be controlled by the initial size of the metal ultrafine particles 2 and the heat treatment temperature.

According to the structure 6 for a fine semiconductor element having a two-layer structure, it is possible to realize, for example, a unit element size and a wiring width on the order of nanometers. This is extremely effective in realizing an ultra-highly integrated semiconductor device or a quantum size device. In addition to these, the present invention can be applied to various ultrafine semiconductor devices. When only the semiconductor protrusion 4 is required, the metal layer 5 may be removed before use.

[0046]

Next, specific examples of the present invention will be described.

Example 1 First, an Si (111) single crystal substrate (non-doped, a ₀ = 0.54
After the Si (111) single crystal substrate was chemically cleaned, the substrate was immersed in a dilute HF solution (2% by weight) for 30 seconds to remove the natural oxide film and obtain a hydrogen-terminated Si surface. A plurality of Au ultrafine particles having a diameter of about 10 nm were continuously arranged on a Si (111) single crystal substrate having been subjected to such a pretreatment according to a desired wiring pattern.

As shown in FIG. 3, a plurality of Au ultrafine particles are prepared by first forming an Au target 1 having a slit 12 corresponding to the arrangement shape (linear shape having a width of 0.5 μm) of the Au ultrafine particles 2.
1 (thickness: 0.5 μm) was placed on the Si single crystal substrate 1. After setting this on the room temperature stage in the vacuum chamber,
For the entire slit inner wall 13 of the Au target 11,
An Ar ion beam 14 having an acceleration voltage of 3.5 kV and a beam current of 0.5 mA was irradiated from an oblique direction for 180 seconds. The incident angle θ of the Ar ion beam was 40 °. The atmosphere during Ar ion beam irradiation is a vacuum of about 1 × 10 ⁻³ Pa (including Ar).
And

After the irradiation with the Ar ion beam 14 described above, the TEM observation of the Si single crystal substrate 1 showed that FIG.
As shown in FIGS. 2 (a), 2 (a), 3 (c) and 6, a plurality of Au ultrafine particles having a diameter of about 10 nm are formed on the Si single crystal substrate 1 in accordance with the shape of the slit 12. It was confirmed that 2 was continuously formed.

As described above, by irradiating the inner wall 13 of the Au target 11 with the Ar ion beam 14 obliquely along the shape of the slit 12, Au atoms (Au clusters) are emitted from the Au target 11. As a result, the Au ultrafine particles 2 are formed,
Since the formed Au ultrafine particles 2 are continuously arranged along the shape of the slit 12, a plurality of Au ultrafine particles 2 can be continuously arranged in a desired shape.

Next, the Si single crystal substrate 1 on which a plurality of Au ultrafine particles 2 were continuously arranged was heat-treated in a high vacuum chamber of 1 × 10 ⁻⁸ Torr or less. This heat treatment was first heated to 800 ° C. at a rate of 15 ° C./min and maintained at that temperature for 30 minutes.
Thereafter, it was gradually cooled to room temperature at a cooling rate of -2 ° C / min.

The structure and composition of the heat-treated sample were measured using a high-resolution transmission electron microscope (HRTEM, JEOL-201).
0) and a dispersive X-ray spectrometer (EDX, Oxford Link ISIS). As a result, FIGS. 1 (b) and 2
As shown in (d) and FIG. 7, continuous projections 6 having a two-layer structure are formed on the surface of the Si single crystal substrate 1 in accordance with the initial configuration (formation pattern) of the Au ultrafine particles. It was confirmed. In the continuous projection 6 having the two-layer structure,
The lower layer portion 4 had a projection shape with a trapezoidal cross section, and had a maximum width of about 20 nm and a minimum width of about 10 nm.

In order to evaluate the composition of each of the layers 4 and 5, EDX analysis was performed. As a result, only the Si peak appeared from the measurement result of the Si substrate portion, and it was found that the Si (111) single crystal substrate 1 maintained that state even after the heat treatment.

From the measurement result of the lower layer portion 4, almost only the Si peak appeared, and it was found that the lower layer portion 4 was composed of a single crystal layer of Si. In fact, in the TEM image, 2
A lattice image of Si was clearly obtained in the lower layer portion 4 of the continuous protrusion 6 having a layer structure. In addition, the TEM image clearly shows that the lower layer portion (Si layer portion) 4 of the continuous projection 6 has the same crystal orientation with respect to the Si (111) single crystal substrate 1. As described above, the Si protrusion 4 is formed by epitaxial growth on the Si (111) single crystal substrate 1.

Further, from the measurement results of the upper layer portion 5, it was found that Au is the dominant component in the upper layer portion 5 of the continuous projection 6 having the two-layer structure. Thus, the continuous projection 6
Is a continuous Si projection 4 epitaxially grown on the Si (111) single crystal substrate 1, and Au is selectively disposed on the Si projection 4 and separated from the Si projection 4.
And the Au layer 5 formed alone. That is, a Si-Au nanocomposite wiring having a Si / Au interface almost completely separated was obtained.

The Si-Au nanocomposite wiring as described above can be used for various fine semiconductor elements such as ultrafine wiring, ultrafine element, ultrafine device and the like. Specifically, application to ultra-highly integrated semiconductor devices and quantum size devices that are expected as candidates for future LSI technology can be considered.

[0057]

As described above, according to the present invention, it is possible to form a continuous semiconductor projection having a nano-order wiring width and an element size on a semiconductor substrate. Such a structure for a fine semiconductor element greatly contributes to the realization of, for example, an ultra-highly integrated semiconductor device or a quantum size device.

[Brief description of the drawings]

FIG. 1 is a perspective view schematically showing a main part of a manufacturing process of a fine semiconductor element structure according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view schematically illustrating a manufacturing process of a structure for a fine semiconductor device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing an example of a process of forming a plurality of ultrafine metal particles used in the process of manufacturing the fine semiconductor element structure of the present invention.

FIG. 4 is a perspective view showing an example of a target material used in a process of forming a plurality of ultrafine metal particles.

FIG. 5 is a perspective view showing another example of a target material used in a process of forming a plurality of ultrafine metal particles.

FIG. 6 is a perspective view showing a partial cross section of a main part of a process of forming a plurality of ultrafine metal particles.

FIG. 7 is a view showing a schematic structure of an embodiment of a structure for a fine semiconductor element of the present invention in a longitudinal section.

FIG. 8 is a view showing a schematic structure of another embodiment of the structure for a fine semiconductor element of the present invention in a longitudinal section.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Ultrafine metal particles 4 ... Semiconductor protrusion 5 ... Metal layer 6 ... Structure for fine semiconductor element

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F033 HH08 HH11 HH13 HH14 MM26 PP07 PP31 QQ53 QQ68 QQ85 XX03

Claims (8)

[Claims] A semiconductor substrate formed on the semiconductor substrate and having a continuous shape grown according to a desired pattern while having an epitaxial relationship with the semiconductor substrate; and the semiconductor projection. And a metal layer selectively disposed on the portion. 2. The micro-semiconductor element structure according to claim 1, wherein said semiconductor protrusion has a trapezoidal cross section and a maximum width of 100 nm or less. Element structure. 3. The structure for a fine semiconductor element according to claim 1, wherein constituent elements of the metal layer are solid-dissolved with constituent elements of the semiconductor substrate in a high temperature range and are substantially separated in a low temperature range. A structure for a fine semiconductor element characterized by the above-mentioned. 4. The structure for a fine semiconductor element according to claim 1, wherein the semiconductor substrate and the semiconductor protrusion include Si.
In addition, the metal layer contains at least one selected from Au, Ag and Al. 5. The structure for a fine semiconductor device according to claim 1, wherein the semiconductor substrate and the semiconductor protrusion include Ge.
In addition, the metal layer contains at least one selected from Zn, Cd, Au, Ag and Al. 6. The structure for a fine semiconductor device according to claim 1, wherein an electron barrier layer is interposed between the semiconductor protrusion and the metal layer. body. 7. A step of continuously arranging a plurality of ultrafine metal particles on a semiconductor substrate according to a desired pattern; and heat-treating the semiconductor substrate on which the plurality of ultrafine metal particles are arranged in a vacuum atmosphere; A step of solid-solving or dissolving the constituent elements of the semiconductor substrate in the metal ultrafine particles; and performing a slow cooling treatment on the solid-solution / liquid phase to convert the constituent elements of the semiconductor substrate from the solid-solution / liquid phase. Forming a semiconductor protrusion having a continuous shape on the semiconductor substrate by epitaxially growing the semiconductor substrate while sedimentation and separation, and forming a metal layer separated from the semiconductor protrusion on the semiconductor protrusion. A method for producing a structure for a fine semiconductor element, characterized by comprising: 8. The method for manufacturing a structure for a fine semiconductor element according to claim 7, wherein a target material having a slit according to the desired pattern is arranged on the semiconductor substrate, and a target material having a height higher than an inner wall of the slit is provided. By irradiating an energy beam from an oblique direction to detach constituent atoms or constituent molecules of the target material, a plurality of ultrafine metal particles are continuously arranged on the semiconductor substrate, for a fine semiconductor element. The method of manufacturing the structure.