JP2000200731A - Laminated ceramic electronic component and its manufacture - Google Patents

Laminated ceramic electronic component and its manufacture

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Publication number
JP2000200731A
JP2000200731A JP10377168A JP37716898A JP2000200731A JP 2000200731 A JP2000200731 A JP 2000200731A JP 10377168 A JP10377168 A JP 10377168A JP 37716898 A JP37716898 A JP 37716898A JP 2000200731 A JP2000200731 A JP 2000200731A
Authority
JP
Japan
Prior art keywords
ceramic
sintered body
internal electrode
electronic component
multilayer ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10377168A
Other languages
Japanese (ja)
Other versions
JP3459186B2 (en
Inventor
Kiyoji Handa
喜代二 半田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marcon Electronics Co Ltd
Original Assignee
Marcon Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marcon Electronics Co Ltd filed Critical Marcon Electronics Co Ltd
Priority to JP37716898A priority Critical patent/JP3459186B2/en
Publication of JP2000200731A publication Critical patent/JP2000200731A/en
Application granted granted Critical
Publication of JP3459186B2 publication Critical patent/JP3459186B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide the laminated ceramic electronic component which can be treated by flow soldering, hardly has a microcrack, and is superior in stress resistance in and after substrate mounting. SOLUTION: This laminated ceramic electronic component is constituted by forming a laminated ceramic capacitor element 4 by forming external electrodes 3 on both exposed end surfaces of internal electrode layers 1 embedded in a ceramic capacitor sinter 2, connecting a metal copper plate 7 to the external electrodes 3 respectively, and coating the part of the ceramic capacitor element 4 with insulating resin 10.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、信頼性に優れ、基
板実装が容易な積層セラミック電子部品及びその製造方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic electronic component having excellent reliability and easy to mount on a substrate, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】一般に角形チップ形状の積層セラミック
電子部品、例えば、積層セラミックコンデンサ、積層バ
リスタ、積層フィルタ等は、小形で高性能、高密度実装
が可能なことから広く用いられている。
2. Description of the Related Art Generally, multilayer ceramic electronic components having a square chip shape, such as multilayer ceramic capacitors, multilayer varistors, multilayer filters, etc., are widely used because of their small size, high performance and high density mounting.

【0003】しかして、これら角形チップ形状の電子部
品は、図6に示すように直方体のセラミック焼結体21
の内部に複数の内部電極層22が埋め込まれ、これら内
部電極層22の一方端部は交互に対向するセラミック焼
結体21の端面に露出し、外部電極23と接続してい
る。外部電極23は銀、ニッケル、銅等の金属粉末とガ
ラス粉末、樹脂、溶剤をペースト状に混練し、前記内部
電極層22の露出端面に塗布し、乾燥後、ガラスが溶融
する温度、一般的には600〜800℃で焼成すること
によって形成される。そして、焼成後の外部電極23と
セラミック焼結体21の接着は主にガラスによることか
ら、外部電極23中のガラスの量が多いほど外部電極2
3とセラミック焼結体21の接着強度は増すが、一方で
は、外部電極23のはんだ濡れ性が低下し、基板にはん
だ付け実装する際に、はんだ付け不良が起きる恐れがあ
る。また、銀は、大気中で焼成できることから一般化し
ているが、高温の溶融はんだ中に拡散するためフローは
んだ付け方式ができない問題を抱えている。
As shown in FIG. 6, these rectangular chip-shaped electronic components have a rectangular parallelepiped ceramic sintered body 21.
Are embedded with a plurality of internal electrode layers 22, and one end of each of the internal electrode layers 22 is exposed on the end face of the ceramic sintered body 21 which faces alternately, and is connected to the external electrode 23. The external electrode 23 is formed by kneading a metal powder of silver, nickel, copper, or the like, a glass powder, a resin, and a solvent into a paste, applying the kneaded paste to the exposed end surface of the internal electrode layer 22, drying the glass, and melting the glass at a temperature generally lower. Is formed by firing at 600 to 800 ° C. Further, since the bonding between the external electrode 23 and the ceramic sintered body 21 after firing is mainly made of glass, the larger the amount of glass in the external electrode 23, the larger the external electrode 2
3 and the ceramic sintered body 21 have increased adhesive strength, but on the other hand, the solder wettability of the external electrode 23 is reduced, and there is a possibility that soldering failure may occur when soldering and mounting on the substrate. Further, silver is generally used because it can be fired in the atmosphere, but has a problem that the flow soldering method cannot be performed because it is diffused into high-temperature molten solder.

【0004】そのため、これらの問題を解決する手段と
して、図7に示すように銀を焼き付けてなる外部電極2
3の表面にニッケル膜24、更にその上にはんだめっき
膜25をそれぞれ電気めっき法によって形成することに
より、銀の拡散防止とはんだ付け性の確保を図ってい
る。
Therefore, as a means for solving these problems, as shown in FIG. 7, an external electrode 2 formed by printing silver is used.
By forming a nickel film 24 on the surface of No. 3 and a solder plating film 25 thereon by an electroplating method, silver diffusion is prevented and solderability is ensured.

【0005】しかしながら、めっき工程のコストが高い
という問題があることは元より、めっき液が外部電極を
介してセラミック焼結体の内部に浸透して信頼性を大幅
に低下させる欠点を有し、特に酸化亜鉛系のバリスタの
場合はセラミック焼結体の表面が導電性であるためセラ
ミック焼結体表面までめっきされる問題を有していた。
However, there is a problem that the cost of the plating step is high, and in addition, the plating solution penetrates into the inside of the ceramic sintered body via the external electrode, thereby significantly reducing the reliability. Particularly, in the case of a zinc oxide-based varistor, the surface of the ceramic sintered body is conductive, so that there is a problem that the surface is plated up to the surface of the ceramic sintered body.

【0006】また、これら積層セラミック電子部品は、
外表面がセラミックであることから、機械的な衝撃に弱
くクラックが入り易く、微小なクラックでも内部電極層
に達していると使用中に空気中の水分が浸透しショート
や絶縁抵抗低下になる場合があり、特に問題になるの
は、図8に示すように、実装した基板26に外力による
曲げ、捩じれが生じたり、急激な温度変化による膨張・
収縮が起こった場合、応力が外部電極23のはんだ付け
部27に集中して外部電極23からセラミック焼結体2
1の内部までクラック28が入り、その結果、電気的特
性が低下するのみならず、使用中に水分と電界の作用に
より内部電極層22間で電極イオンのマイグレーション
が起こりショートになる問題を抱える結果となってい
た。
[0006] These multilayer ceramic electronic components also include:
Since the outer surface is ceramic, it is susceptible to mechanical shock and cracks are easy to occur.If even small cracks reach the internal electrode layer, moisture in the air permeates during use and shorts or insulation resistance decreases. Particularly, as shown in FIG. 8, the mounting board 26 may be bent or twisted by an external force as shown in FIG.
When the shrinkage occurs, the stress concentrates on the soldering portion 27 of the external electrode 23 and the ceramic sintered body 2
In addition, cracks 28 enter the inside of the electrode 1, and as a result, not only the electrical characteristics are deteriorated, but also the ion ions migrate between the internal electrode layers 22 due to the action of moisture and an electric field during use, resulting in a short circuit. Had become.

【0007】[0007]

【発明が解決しようとする課題】以上述べたように、従
来の角形チップ形状の積層セラミック電子部品は、基板
へ実装する場合、前述のように多くの特性劣化要因を抱
える結果となり、実用上解決すべき課題を抱えていた。
As described above, when a conventional square chip-shaped multilayer ceramic electronic component is mounted on a substrate, as described above, it has many characteristics deterioration factors as described above, and is practically solved. Had a task to be done.

【0008】本発明は、上記の点に鑑みてなされたもの
で、はんだ付性、はんた耐熱性に優れ、フローはんだ付
けが可能で、マイクロクラックが生じ難く、基板実装時
及び実装後の対応力性に優れた高信頼性の積層セラミッ
ク電子部品及びその製造方法を提供しようとするもので
ある。
The present invention has been made in view of the above points, and has excellent solderability and solder heat resistance, can be flow-soldered, hardly causes micro cracks, and can be used during and after board mounting. An object of the present invention is to provide a highly reliable multilayer ceramic electronic component having excellent responsiveness and a method for manufacturing the same.

【0009】[0009]

【課題を解決するための手段】上記のような課題を解決
するために、請求項1記載の積層セラミック電子部品
は、セラミックグリーンシートと内部電極層を交互に積
層し、この内部電極層の一方端部を交互に対向端面に露
出させ焼結して形成したセラミック焼結体と、このセラ
ミック焼結体の前記内部電極層が露出した端面に形成し
た外部電極と、この外部電極に接続した金属板と、この
金属板の表面を除き前記セラミック焼結体全面を被覆し
た絶縁樹脂とからなることを特徴とする。
In order to solve the above-mentioned problems, a multilayer ceramic electronic component according to the present invention is characterized in that ceramic green sheets and internal electrode layers are alternately laminated, and one of the internal electrode layers is formed. A ceramic sintered body formed by exposing and sintering the end portions alternately to the opposite end surface, an external electrode formed on the end surface of the ceramic sintered body where the internal electrode layer is exposed, and a metal connected to the external electrode A plate and an insulating resin covering the entire surface of the ceramic sintered body except for the surface of the metal plate.

【0010】この発明の積層セラミック電子部品では、
基板への接続部が外部電極に接続したはんだ付け良好な
金属板となっているため、はんだ付け方法や条件に左右
されず良好なリフローはんだ付けは元より、良好なフロ
ーはんだ付けが可能であると同時に、セラミック焼結体
の表面が樹脂で被覆されているため、振動フィーダ等で
の部品同士のぶつかり合いやチップマウンターの吸着ノ
ズルの衝撃があってもクラック発生となることはない。
In the multilayer ceramic electronic component of the present invention,
Since the connection part to the board is a metal plate with good solderability connected to the external electrode, good flow soldering is possible as well as good reflow soldering regardless of the soldering method and conditions At the same time, since the surface of the ceramic sintered body is covered with the resin, cracks will not occur even if there is a collision between parts with a vibration feeder or the like or an impact of a suction nozzle of a chip mounter.

【0011】したがって、基板実装の際の制約もなく、
且つ、特性劣化要因も解消され、信頼性に富む積層セラ
ミック電子部品が得られる作用効果を得ることができ
る。
Therefore, there is no restriction in mounting the substrate,
In addition, the characteristic deterioration factor is eliminated, and the effect of obtaining a highly reliable multilayer ceramic electronic component can be obtained.

【0012】請求項2に記載の発明は、請求項1に記載
の積層セラミック電子部品を効率良く作製する製造方法
に関するものであり、一対の金属板間に、予め作製した
セラミック焼結体の内部に複数の内部電極層が埋め込ま
れ、これら内部電極層の一方端部を交互に対向端面に露
出し、この露出端面に外部電極を形成したセラミック素
子複数個を、複数個間で一定の間隔を保持し、外部電極
部と金属板との当設部を導電性接着剤を介して接着して
一体化し、しかる後、一対の金属板の間隔となる三面部
を蓋にて閉塞し、残り一面の口から注型用の液状エポキ
シ樹脂を注入−硬化させ、予め前記金属板面に付してあ
る切断線となる枡目に沿って切断し、単位の積層セラミ
ック電子部品を得ことを特徴とする。
A second aspect of the present invention relates to a manufacturing method for efficiently manufacturing the multilayer ceramic electronic component according to the first aspect of the present invention. A plurality of internal electrode layers are buried, one end of each of these internal electrode layers is alternately exposed to the opposite end face, and a plurality of ceramic elements having external electrodes formed on the exposed end face are spaced at a constant interval between the plurality of ceramic elements. Holding, the contact portion between the external electrode portion and the metal plate is bonded and integrated via a conductive adhesive, and thereafter, the three surface portions that are the gap between the pair of metal plates are closed with a lid, and the remaining one surface is covered. A liquid epoxy resin for casting is injected through the opening of-and cured, and cut in advance along a grid line serving as a cutting line attached to the metal plate surface, to obtain a unitary multilayer ceramic electronic component. I do.

【0013】この発明の積層セラミック電子部品の製造
方法によれば、金属板間に複数の積層セラミック素子を
固着し、予め金属板に付した切断線となる枡目に沿って
切断することで一度に多数の信頼性に富む積層セラミッ
ク電子部品を得ることができる特徴を有するものであ
る。
According to the method of manufacturing a multilayer ceramic electronic component of the present invention, a plurality of multilayer ceramic elements are fixed between metal plates and cut once along a grid line which is a cutting line previously attached to the metal plate. Thus, it is possible to obtain a large number of highly reliable multilayer ceramic electronic components.

【0014】[0014]

【発明の実施の形態】本発明の積層セラミック電子部品
は、スラリーをドクターブレード法によりグリーンシー
トに成形し、このグリーンシートに電極ペーストをパタ
ーン状にスクリーン印刷し、これを一定寸法に打ち抜
き、印刷パターンが切断後交互に切断面に露出するよう
に位置合せして複数枚積み重ね、上下に印刷していない
ダミーシートを所定枚数重ね、加熱、加圧することによ
り圧着一体化し積層体を形成し、しかる後、この積層体
を所定の位置で個々のチップ状に切断−焼結し積層セラ
ミック焼結体を作製し、この積層セラミック焼結体の内
部電極が露出している両端面に、外部電極を形成し積層
セラミック素子を形成する。
BEST MODE FOR CARRYING OUT THE INVENTION The multilayer ceramic electronic component of the present invention is obtained by forming a slurry into a green sheet by a doctor blade method, screen-printing an electrode paste on the green sheet in a pattern, and punching the green paste into a predetermined size. After cutting, a plurality of dummy sheets are stacked while being aligned so that they are alternately exposed on the cut surface, and a predetermined number of dummy sheets not printed up and down are stacked, and heated and pressed to form a laminate by pressure bonding and integration. Thereafter, the laminated body is cut and sintered into individual chips at predetermined positions to produce a laminated ceramic sintered body, and external electrodes are provided on both end surfaces of the laminated ceramic sintered body where the internal electrodes are exposed. To form a multilayer ceramic element.

【0015】次に、切断線となる格子状の罫線によって
形成された複数の枡目を設けた金属板の前記枡目の中央
に外部電極の一方面を接着し複数個の積層セラミック素
子を固着し、更に、外部電極の他方面部に、前述と同様
に形成した金属板を同一方法で接着し、金属板に挟ん
で、この金属板と複数個の積層セラミック素子を一体化
した状態とする。
Next, one surface of an external electrode is adhered to the center of the mesh on a metal plate provided with a plurality of meshes formed by grid-like ruled lines serving as cutting lines, and a plurality of laminated ceramic elements are fixed. Further, a metal plate formed in the same manner as described above is adhered to the other surface of the external electrode by the same method, sandwiched between the metal plates, and the metal plate and a plurality of laminated ceramic elements are integrated. .

【0016】次に、前記一対の金属板の間隔となる三面
部を蓋にて閉塞し、残り一面の口から注型用の樹脂を注
入−硬化させ、しかる後、蓋を取り除き一体化物を形成
する。
Next, a three-sided portion, which is a gap between the pair of metal plates, is closed with a lid, and a casting resin is injected and cured from the remaining one side of the opening. Thereafter, the lid is removed to form an integrated product. I do.

【0017】次に、この一体化物の金属板面に付してあ
る切断線となる枡目に沿って切断することによって、外
部電極に金属板が固着され、積層セラミック素子全面が
絶縁樹脂で被覆されたチップ形の積層セラミック電子部
品を得るものである。
Next, the metal plate is fixed to the external electrodes by cutting along the grid line which is a cutting line attached to the metal plate surface of the integrated product, and the entire surface of the multilayer ceramic element is covered with an insulating resin. To obtain a chip-shaped multilayer ceramic electronic component.

【0018】[0018]

【実施例】以下に、積層形セラミックコンデンサを例示
して図面を参照して説明する。まず、誘電体組成とし
て、例えば、マグネシウムニオブ酸鉛、亜鉛ニオブ酸
鉛、チタン酸鉛の三成分からなり、さらにこの内の鉛の
一部をバリウムで置換した鉛系複合ペロブスカイト構造
を持つ誘電体粉末を作製した。次に、この粉末にバイン
ダとしてポリブチラール樹脂、DOP,溶剤を加え混合
することにより得られたスラリーをドクターブレード法
により厚さ15μmのグリーンシートに成形し、このグ
リーンシートに銀/パラジウムを含む電極ペーストをパ
ターン状にスクリーン印刷し、これを一定寸法に打ち抜
き、印刷パターンが切断後交互にに切断面に露出するよ
うに位置合せして100枚積み重ね、上下に印刷してい
ないダミーシートを各20枚重ね、加熱、加圧すること
により圧着一体化し積層体を形成し、しかる後、この積
層体を所定の位置で個々のチップ状に切断し、1000
℃で焼結しセラミックコンデンサ焼結体を作製し、この
セラミックコンデンサ焼結体の内部電極が露出している
両端面に、銀粉末を含む電極ペーストを塗布し、800
℃で焼成して外部電極を形成し長さ5.2mm,幅4.
7mm,厚さ1.5mmのチップ形の積層セラミックコ
ンデンサ素子を形成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A multilayer ceramic capacitor will be described below with reference to the drawings. First, as the dielectric composition, for example, a lead-based composite perovskite structure composed of three components of lead magnesium niobate, lead zinc niobate, and lead titanate, and further substituting a part of the lead with barium A powder was made. Next, a slurry obtained by adding and mixing a polybutyral resin, DOP and a solvent as a binder to the powder is formed into a green sheet having a thickness of 15 μm by a doctor blade method, and the green sheet contains an electrode containing silver / palladium. The paste is screen-printed in a pattern, punched out to a certain size, and the printed pattern is stacked so as to be alternately exposed on the cut surface after cutting, and 100 sheets are stacked. The sheets are stacked, heated and pressed to be integrated by pressure bonding to form a laminate. Thereafter, the laminate is cut into individual chips at predetermined positions,
C. to form a ceramic capacitor sintered body. Electrode paste containing silver powder was applied to both end surfaces of the ceramic capacitor sintered body where the internal electrodes were exposed.
Baking at ℃ to form external electrodes, length 5.2mm, width 4.
A chip-type multilayer ceramic capacitor element having a thickness of 7 mm and a thickness of 1.5 mm is formed.

【0019】次に図2に示すように、錫90/鉛10の
組成で厚さ10μmのめっきを施した厚さ0.15mm
で150mm角状で、表裏両面に切断線となる格子状の
罫線5によって形成された5.3×2.1mmの枡目6
を設けた金属銅板7を用い、図3〜図4に示すように、
この金属銅板7の前記罫線5によって得られたそれぞれ
の枡目6中央に、前述のような手段によって得られたチ
ップ状の積層セラミックコンデンサ素子4の外部電極3
の一方面を銀粉末と樹脂からなる導電性接着剤8を用い
て接着硬化させ、外部電極3の他方面に、前述と同様に
形成した金属銅板7を同一方法で接着し、金属銅板7に
挟んで、この金属銅板7と複数個のチップ形の積層セラ
ミックコンデンサ素子4を一体化した状態とする。
Next, as shown in FIG. 2, a 0.15 mm-thick plated with a composition of tin 90 / lead 10 and a thickness of 10 μm.
A 5.3 × 2.1 mm grid 6 formed by a grid-shaped ruled line 5 which is a 150 mm square and is a cutting line on both sides.
Using a metal copper plate 7 provided with
The external electrodes 3 of the chip-shaped multilayer ceramic capacitor element 4 obtained by the above-described means are provided at the centers of the respective meshes 6 obtained by the ruled lines 5 of the metal copper plate 7.
Is bonded and cured using a conductive adhesive 8 made of silver powder and resin, and a metal copper plate 7 formed in the same manner as described above is bonded to the other surface of the external electrode 3 by the same method. The metal copper plate 7 and a plurality of chip-shaped multilayer ceramic capacitor elements 4 are integrated with each other.

【0020】次に、前記一対の金属銅板7の間隔となる
三面部を蓋(図示せず)にて閉塞し、残り一面の口から
注型用の液状エポキシ樹脂を注入−硬化させ、蓋を取り
除き図5に示す一体化物9を形成する。
Next, a three-sided portion, which is a gap between the pair of metal copper plates 7, is closed with a lid (not shown), and a liquid epoxy resin for casting is injected and cured from the remaining one side of the opening, and the lid is closed. The removal is performed to form the integrated body 9 shown in FIG.

【0021】次に、この一体化物9の金属銅板7面に付
してある罫線5によって形成された枡目6に沿って、厚
さ0.3mmの回転ダイヤモンドブレードのカッターで
切断することによって、図1に示すように、長さ5.7
mm,幅5.0mm,厚さ1.8mmの積層セラミック
コンデンサを完成させる。図中、1は内部電極、2はセ
ラミックコンデンサ焼結体、10は絶縁樹脂である。
Next, the integrated material 9 is cut along a mesh 6 formed by the ruled lines 5 attached to the surface of the metal copper plate 7 with a cutter of a rotating diamond blade having a thickness of 0.3 mm. As shown in FIG.
mm, a width of 5.0 mm and a thickness of 1.8 mm are completed. In the figure, 1 is an internal electrode, 2 is a ceramic capacitor sintered body, and 10 is an insulating resin.

【0022】次に、上記実施例によって作製した図1に
示す本発明品(A)と、図6に示す従来構造品(B)の
比較試験について表1に示す。
Next, Table 1 shows a comparative test of the product of the present invention (A) shown in FIG. 1 and the conventional structure (B) shown in FIG.

【0023】なお、試験項目及び条件は以下の通りで、
従来構造品(B)の組成及び内部電極材は、本発明品
(A)と同一である。 (1)耐衝撃性:プラスチック製のタッパー容器2個を
準備し、本発明品及び従来構造品それぞれを100個ず
つ入れて、振幅100mm,2サイクル/秒で10秒振
動させ、15倍の拡大鏡を用いて表面のクラックの有無
を調べ、クラックのあるものを不良とした。 (2)耐基板曲げ性:JIS C 6429附属書2に
示されている方法。ただし、撓み量を3mmとした試験
をそれぞれ100個の試料について行い、静電容量が1
0%以上減少したもの、及びクラックが発生したものを
不良とした。 (3)耐ヒートサイクル/耐湿性複合試験:JIS C
6429に規定する試験用基板Aに、それぞれ100
個の試料をはんだ付けし、−55℃/+125℃各30
分で100サイクルの温度サイクル試験を行った後、温
度85℃、相対湿度85%でDCバイアス25Vを50
0時間連続印加後、耐電圧(定格電圧の250%)、静
電容量、絶縁抵抗を測定し、初期規格値を満足しないも
のを不良とした。 (4)はんだ耐熱性:JIS C 6429附属書3に
示されている方法。ただし、はんだ温度280℃、浸漬
回数を2回とした試験をそれぞれ100個の試料につい
て行い、試験後、電極の消失部分があるものを不良とし
た。
The test items and conditions are as follows.
The composition and internal electrode material of the conventional structural product (B) are the same as those of the present invention product (A). (1) Impact resistance: Two plastic tapper containers are prepared, and each of the present invention product and the conventional structure product is put in 100 pieces, and the product is vibrated for 10 seconds at an amplitude of 100 mm and 2 cycles / sec. The presence or absence of cracks on the surface was examined using a mirror, and those having cracks were judged to be defective. (2) Substrate bending resistance: a method shown in JIS C 6429 Annex 2. However, a test in which the amount of deflection was 3 mm was performed on each of 100 samples, and the capacitance was 1
Those which were reduced by 0% or more and those which had cracks were regarded as defective. (3) Heat cycle / moisture resistance composite test: JIS C
Each of the test substrates A specified in 6429 has 100
Each sample was soldered and the temperature was -55 ° C / + 125 ° C for 30
After a temperature cycle test of 100 cycles per minute, a DC bias of 25 V was applied at a temperature of 85 ° C. and a relative humidity of 85% for 50 minutes.
After continuous application for 0 hours, the withstand voltage (250% of the rated voltage), the capacitance, and the insulation resistance were measured. (4) Solder heat resistance: a method shown in Annex 3 of JIS C 6429. However, a test in which the solder temperature was 280 ° C. and the number of times of immersion was two was performed on each of 100 samples, and after the test, those having a portion where the electrode disappeared were regarded as defective.

【0024】[0024]

【表1】 [Table 1]

【0025】なお、上記実施例では、積層セラミックコ
ンデンサを例示して説明したが、積層バリスタ、又は積
層フィルタ等に適用できることは勿論である。
In the above embodiment, a multilayer ceramic capacitor has been described as an example. However, it is needless to say that the present invention can be applied to a multilayer varistor, a multilayer filter or the like.

【0026】[0026]

【発明の効果】以上述べたように、本発明によれば、は
んだ付け性、はんだ耐熱性に優れ、リフローはんだ付け
は基より、フローはんだ付けが可能で、マイクロクラッ
クが生じ難く、基板実装時及び実装後の対応力性に優れ
た積層セラミック電子部品及びその製造方法を提供でき
る。
As described above, according to the present invention, the solderability and the solder heat resistance are excellent, the flow soldering can be performed more easily than the reflow soldering, the micro cracks are less likely to occur, and the mounting of the circuit board can be easily performed. In addition, it is possible to provide a multilayer ceramic electronic component having excellent responsiveness after mounting and a method of manufacturing the same.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明に係る積層セラミックコンデンサを示
す断面図。
FIG. 1 is a sectional view showing a multilayer ceramic capacitor according to the present invention.

【図2】 本発明に係る金属銅板を示す平面図。FIG. 2 is a plan view showing a metal copper plate according to the present invention.

【図3】 本発明に係り製造途中の積層セラミックコン
デンサ素子と金属銅板を一体化した状態を示す斜視図。
FIG. 3 is a perspective view showing a state in which a multilayer ceramic capacitor element and a metal copper plate which are being manufactured according to the present invention are integrated.

【図4】 図3の矢印方向から見た正面図。FIG. 4 is a front view as seen from the direction of the arrow in FIG. 3;

【図5】 本発明に係り製造途中の積層セラミックコン
デンサ素子と金属銅板を一体化し金属銅板間に樹脂を注
入−硬化させて形成した一体化物を示す斜視図。
FIG. 5 is a perspective view showing an integrated product formed by integrating a multilayer ceramic capacitor element and a metal copper plate during manufacturing according to the present invention and injecting and curing a resin between the metal copper plates.

【図6】 従来例に係る積層セラミック電子部品を示す
断面図。
FIG. 6 is a sectional view showing a multilayer ceramic electronic component according to a conventional example.

【図7】 他の従来例に係る積層セラミック電子部品を
示す断面図。
FIG. 7 is a cross-sectional view showing a multilayer ceramic electronic component according to another conventional example.

【図8】 従来例に係り積層セラミック電子部品を基板
に搭載し、基板を撓ませたときの積層セラミック電子部
品不具合状態を示す断面図。
FIG. 8 is a cross-sectional view showing a failure state of a multilayer ceramic electronic component when a multilayer ceramic electronic component is mounted on a substrate and the substrate is bent according to a conventional example.

【符号の説明】[Explanation of symbols]

1 内部電極層 2 セラミックコンデンサ焼結体 3 外部電極 4 積層セラミックコンデンサ素子 5 罫線 6 枡目 7 金属銅板 8 導電性接着剤 9 一体化物 10 絶縁樹脂 REFERENCE SIGNS LIST 1 internal electrode layer 2 ceramic capacitor sintered body 3 external electrode 4 multilayer ceramic capacitor element 5 ruled line 6 grid 7 metal copper plate 8 conductive adhesive 9 integrated object 10 insulating resin

フロントページの続き Fターム(参考) 5E001 AB03 AC10 AE00 AE02 AE03 AF00 AF02 AF06 AG01 AH01 AH05 AH06 AH07 AH09 AJ02 AJ03 5E082 AA01 AB03 BC23 BC33 EE04 EE23 EE35 FG06 FG26 FG27 FG54 GG08 GG11 HH27 HH43 HH48 JJ03 JJ05 JJ12 JJ21 JJ26 LL01 LL02 LL03 LL35 MM22 MM24 Continued on the front page F-term (reference) LL03 LL35 MM22 MM24

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 セラミックグリーンシートと内部電極層
を交互に積層し、この内部電極層の一方端部を交互に対
向端面に露出させ焼結して形成したセラミック焼結体
と、このセラミック焼結体の前記内部電極層が露出した
端面に形成した外部電極と、この外部電極に接続した金
属板と、この金属板の表面を除き前記セラミック焼結体
全面を被覆した絶縁樹脂とからなることを特徴とする積
層セラミック電子部品。
1. A ceramic sintered body formed by alternately laminating ceramic green sheets and internal electrode layers, exposing one end of the internal electrode layers alternately to opposing end surfaces, and sintering the ceramic green sheets. An external electrode formed on the end face where the internal electrode layer of the body is exposed, a metal plate connected to the external electrode, and an insulating resin covering the entire surface of the ceramic sintered body except for the surface of the metal plate. Characterized multilayer ceramic electronic components.
【請求項2】 一対の金属板間に、セラミック焼結体の
内部に複数の内部電極層が埋め込まれ、この内部電極層
の一方端部を交互に対向端面に露出し、この露出端部が
位置する前記セラミック焼結体面に前記内部電極の露出
端部と接続して外部電極を形成した複数個の積層セラミ
ック素子を、複数個間で一定の間隔を保持し、外部電極
と金属板との当設部を導電性接着剤を介して接着一体化
する工程と、一対の金属板間に配設された複数の積層セ
ラミック素子間の空隙部に絶縁樹脂を注入−硬化させて
一体化物を形成する工程と、この一体化物の前記金属板
面に予め付してある切断線となる枡目に沿って切断し、
前記積層セラミック素子の外部電極部に金属板が接続さ
れ、且つセラミック焼結体部が絶縁樹脂にて被覆された
単位積層セラミック電子部品を得る工程とを順次経るこ
とを特徴とする積層セラミック電子部品の製造方法。
2. A plurality of internal electrode layers are buried in a ceramic sintered body between a pair of metal plates, and one ends of the internal electrode layers are alternately exposed on opposing end faces, and the exposed ends are A plurality of laminated ceramic elements having external electrodes formed by being connected to the exposed ends of the internal electrodes on the surface of the ceramic sintered body that is located, maintaining a constant interval between the plurality of ceramic elements, A step of bonding and integrating the attached portion via a conductive adhesive, and injecting and curing an insulating resin into a gap between a plurality of laminated ceramic elements disposed between a pair of metal plates to form an integrated product And cutting along a mesh that is a cutting line previously attached to the metal plate surface of the integrated product,
A step of obtaining a unitary multilayer ceramic electronic component in which a metal plate is connected to an external electrode portion of the multilayer ceramic element and a ceramic sintered body portion is coated with an insulating resin. Manufacturing method.
JP37716898A 1998-12-29 1998-12-29 Manufacturing method of multilayer ceramic electronic component Expired - Fee Related JP3459186B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP37716898A JP3459186B2 (en) 1998-12-29 1998-12-29 Manufacturing method of multilayer ceramic electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP37716898A JP3459186B2 (en) 1998-12-29 1998-12-29 Manufacturing method of multilayer ceramic electronic component

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JP2000200731A true JP2000200731A (en) 2000-07-18
JP3459186B2 JP3459186B2 (en) 2003-10-20

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Country Link
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