JP2000196680A - Receiver circuit and signal transmission system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable fast signal transmission (signal detection) with high accuracy. SOLUTION: This receiver circuit contains a capacity network part 1 receiving a differential input signal and a comparator part 2 receiving an output of the capacity network part. The capacity network is provided with capacity means 17 and 18 which accumulate charges and switching means 11 to 14 which control the supply of the input signal to the capacity means. The comparator part is provided with inverters 21 and 22 which amplify an output of the capacity network part and a common mode feedback circuit 3 which receives outputs of the inverters and maintains a common mode voltage to an almost fixed value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a receiver circuit and a signal transmission system, and more particularly to a receiver circuit capable of high-speed signal transmission. In recent years, the performance of components constituting computers and other information processing devices has greatly improved. For example, the performance of semiconductor storage devices such as DRAMs and processors has been remarkably improved. And
With the improvement in the performance of the semiconductor memory device, the processor, and the like, the situation is that the performance of the system cannot be improved unless the signal transmission speed between each component or element is improved. Specifically, for example, a DRAM
And the like, the signal transmission speed between the main storage device and the processor is hindering the performance improvement of the entire computer. Further, not only signal transmission between a housing and a board (printed wiring board) such as a server and a server via a main storage device or a network, but also high integration and enlargement of a semiconductor chip and reduction in power supply voltage. Due to (eg, lowering the signal amplitude), it is necessary to improve the signal transmission speed in signal transmission between chips and between elements and circuit blocks in a chip. Therefore, there is a demand for a receiver circuit and a signal transmission system capable of transmitting signals with higher accuracy and higher speed.

[0002]

2. Description of the Related Art FIG. 1 schematically shows an example of a conventional signal transmission system. In FIG. 1, reference numeral 101 indicates
Denotes a differential driver, 102 denotes a cable, 103 denotes a differential receiver (receiver circuit), and 104 denotes a terminating resistor. As shown in FIG. 1, differential signal transmission is generally performed, for example, in high-speed signal transmission between boards or enclosures (for example, between a server and a main storage device). Here, for example, the differential driver 101 is provided in a server (main storage device) on the signal transmission side, and the receiver circuit 103 is provided in a main storage device (server) on the signal reception side. Further, on the input side (differential input) of the receiver circuit 103, a termination resistor 104 connected to the termination voltage Vtt is provided.
Is provided. Note that signal transmission by differential signals (complementary signals) is used not only between boards and housings, but also between elements and circuit blocks in a chip when the signal amplitude is small, for example.

[0003]

In the conventional signal transmission system as shown in FIG. 1, the differential driver 101 is relatively easy to operate at a high speed, whereas the differential circuit 101 is operated at a high speed. There are difficult aspects to do. Therefore, for example, when performing signal transmission between the housing of the server and the main storage device, the characteristics of the receiver circuit 103 may directly determine the performance of the system.

Specifically, in the signal transmission system shown in FIG. 1, a differential signal transmitted from a differential driver 101 on a transmitting side via a cable is differentially amplified by a differential amplifier provided in a receiver circuit 103 on a receiving side. It is designed to be dynamically amplified. The factor that hinders high-speed operation in the conventional signal transmission system is that the cable 102
Of the high-frequency component of the signal at the
And the frequency band of the differential amplifier. That is,
When the signal transmission speed becomes high, such as several hundred megabits to several gigabits BPS (Bit / sec), it has become difficult for a normal differential amplifier to perform a sufficiently high-speed operation.

Further, under the required high-speed operation conditions, the conventional receiver circuit 103 effectively removes the common mode voltage (the average value of the voltages of the two signal lines for transmitting the differential signal) to achieve a highly accurate signal. The transmission (signal detection) was not sufficiently performed. Conventionally, a transformer was sometimes used to remove the common mode voltage. However, such use of the transformer was not preferable in terms of cost and occupied volume.

An object of the present invention is to provide a receiver circuit and a signal transmission system capable of high-accuracy and high-speed signal transmission in view of the conventional signal transmission technology described above.

[0007]

According to a first aspect of the present invention, there is provided a receiver circuit including a capacitance network unit for receiving a differential input signal and a comparator unit for receiving an output of the capacitance network unit. The capacitor network unit includes a capacitor unit that accumulates electric charge, and a switch unit that controls supply of the input signal to the capacitor unit; the comparator unit includes an inverter that amplifies an output of the capacitor network unit; Further, there is provided a receiver circuit including a common mode feedback circuit which receives an output of the inverter and maintains the common mode voltage at a substantially constant value.

According to a second aspect of the present invention, a differential driver circuit, a cable connected to the differential driver circuit for transmitting a differential signal from the differential driver circuit, and a cable connected to the cable, A signal transmission system comprising a receiver circuit for detecting a differential signal, wherein the receiver circuit receives a differential input signal,
A comparator unit for receiving an output of the capacitance network unit, wherein the capacitance network unit includes capacitance means for accumulating electric charge, and switch means for controlling supply of the input signal to the capacitance means; Provides an inverter that amplifies the output of the capacitance network unit, and a common mode feedback circuit that receives the output of the inverter and keeps the common mode voltage at a substantially constant value. Is done.

According to the present invention, the capacity network unit comprises:
Capacitance means for accumulating electric charge, and switch means for controlling supply of an input signal to the capacitance means,
The comparator section includes an inverter that amplifies the output of the capacitance network section, and a common mode feedback circuit that receives the output of the inverter and maintains the common mode voltage at a substantially constant value. As a result, it is possible to provide a receiver circuit and a signal transmission system capable of high-accuracy and high-speed signal transmission.

FIG. 2 is a diagram showing a principle configuration of a receiver circuit according to the present invention. In FIG. 2, reference numeral 1 denotes a capacity network unit, and reference numeral 2 denotes a comparator unit. The capacity network unit 1 includes switches 11 to 16 and capacitors 17 and 18. One input V + of the receiver circuit is connected to a switch 1 provided in series.
1 and the capacitor 17 are connected to one input of the comparator unit 2 (input of the inverter 21). Similarly, the other input V− is connected to the comparator unit 2 via the switch 14 and the capacitor 18 provided in series. Is connected to the other input (input of the inverter 22).

A connection node between the switch 11 and the capacitor 17;
The connection node between the switch 14 and the capacitor 18 includes:
A first reference voltage Vref is applied via switches 12 and 13, respectively. Further, a connection node between the capacitor 17 and the inverter 21 and a capacitor 1
The second reference voltage Vref ′ is applied to the connection node between the inverter 8 and the inverter 22 via the switches 15 and 16, respectively. Then, the common mode voltage included in the differential signal is removed to some extent by the capacitance network unit 1. Note that the common mode voltage corresponds to an average value of voltages of two signal lines transmitting a differential signal.

The comparator unit 2 includes two inverters 2
1, 2 and common mode feedback circuit 3
And amplifies the supplied output of the capacitance network unit 1 at high speed and high bandwidth, and further removes the common mode voltage by feedback. FIG. 3 is a diagram for explaining removal of a common mode voltage by the receiver circuit shown in FIG. 2, and the vertical axis represents a common mode voltage removal ratio (CMRR: Common Mode voltage R).
ejection ratio), and the horizontal axis is frequency (log f).

As shown in FIG. 3, in a low frequency region (for example, a DC region to several kilohertz) A1, the common mode voltage is removed by the capacitance network unit 1 of the receiver circuit, and a high frequency region is obtained. At A2 (for example, several kilohertz or more), the common mode voltage is further removed by the comparator unit 2 of the receiver circuit.

That is, the capacitor network unit 1 alternately repeats the accumulation of the signal voltage, the precharging of the input terminal of the comparator unit 2 and the input of the signal to the comparator unit 2 to alternately generate the common signal included in the differential signal. Mode voltage is removed to some extent. Here, as is clear from FIG. 3, the common mode voltage removed by the capacitance network unit 1 increases as the frequency decreases, and the DC component of the common mode voltage decreases with respect to the DC component of the common mode voltage.
Is sufficiently removed.

In the comparator section 2, the signal from which the common mode voltage has been removed is amplified to a certain extent. This amplification is performed by a high-speed and high-band amplification using two inverters 21 and 22 instead of a normal differential amplifier. Has become. Further, the common mode voltage included in the outputs of the inverters 21 and 22 is removed by the common mode feedback circuit 3 that performs feedback so that the common mode voltage becomes constant.

As described above, since the receiver circuit of the present invention can use an inverter circuit instead of a normal differential amplifier as an amplifier circuit, it can perform low-voltage operation and high-speed operation. Further, according to the present invention, it is possible to provide a receiver circuit and a signal transmission system capable of transmitting signals with high accuracy and high speed.

[0017]

Embodiments of a receiver circuit and a signal transmission system according to the present invention will be described below in detail with reference to the drawings. FIG. 4 is a circuit diagram showing a first embodiment of the receiver circuit according to the present invention. 4, reference numeral 1 denotes a capacitance network unit, 2 denotes a comparator unit, and a common mode feedback circuit 3.

The capacity network section 1 is composed of switches 11 to 16 and capacitors 17 and 18 as in FIG. And one input V + of the receiver circuit
Is connected to one input (input of the inverter 21) of the comparator unit 2 via the switch 11 and the capacitor 17 provided in series, and similarly, the other input V- is connected to the switch 14 and the switch 14 provided in series. It is connected to the other input of the comparator unit 2 (input of the inverter 22) via the capacitor 18.

A connection node between the switch 11 and the capacitor 17;
The connection node between the switch 14 and the capacitor 18 includes:
A first reference voltage Vref0 is applied via switches 12 and 13, respectively. Further, a connection node between the capacitor 17 and the inverter 21 and a capacitor 1
The second reference voltage Vref ′ is applied to the connection node between the inverter 8 and the inverter 22 via the switches 15 and 16, respectively. Then, the common mode voltage (the average value of the voltages of the two signal lines transmitting the differential signal) included in the differential signal is removed to some extent by the capacitance network unit 1 (see the area A1 in FIG. 3). .

Here, the first reference voltage Vref0 is determined according to the standard of an interface circuit (for example, an interface circuit connecting between casings) connected to the receiver circuit, and is, for example, an intermediate signal amplitude of the interface circuit. Defined as voltage. On the other hand, the second reference voltage V
ref 'is a voltage suitable for the internal circuit of the receiver circuit,
For example, a voltage (bias voltage) that optimizes the operation of the inverters 21 and 22 of the comparator unit 2 at the subsequent stage.
Is defined as

In the capacitance network unit 1, in the first phase, the switches 11 and 14 are turned off and the switches 12 and 13 are turned on, and the switches 15 and 16 are turned on to store the capacitances 17 and 18. In addition, the input terminal of the comparator unit 2 is precharged. That is, a bias voltage that optimizes the operation is applied to the inverters 21 and 22 of the comparator unit 2 at the subsequent stage. Further, in the second phase, the switches 11 and 14 are turned on, the switches 12, 13 and the switches 15, 16 are turned off, and the voltage of the differential signal (complementary signal) is passed through the capacitors 17 and 18. To the input of the comparator unit 2 (inverters 21 and 22). Then, by repeating the first phase and the second phase alternately,
The common mode voltage included in the differential signal can be removed to some extent. The common mode voltage removed by the capacitance network unit 1 increases as the frequency decreases, and the DC component can be sufficiently removed.

The comparator unit 2 includes two inverters 2
1, 2 and common mode feedback circuit 3
And amplifies the supplied output of the capacitance network unit 1 at high speed and high bandwidth, and further removes the common mode voltage by feedback. Inverters 21 and 22 are P-channel MOS
Transistors (PMOS transistors) 211; 221
And an N-channel type MOS transistor (NMOS transistor) 212; 222 as a single-ended inverter. That is, each input signal (differential signal) is supplied to the NMOS transistor 212
The PMOS transistors 211 and 221 have a predetermined bias voltage Vcp applied to their gates to form a constant current load. Here, inverters 21 and 22
In order to further increase the speed by reducing the input capacitance (gate capacitance), a constant current load inverter with an NMOS transistor input as shown in FIG. 4 is preferable. For example, a signal is transmitted through a cable (102). In the case of the driver circuit of the first stage for receiving, it is not necessary to care much about the input capacitance, so that the inverter is of a normal CMOS configuration (an inverter that supplies an input signal to both gates of the PMOS transistor and the NMOS transistor in common). You may comprise.

The common mode feedback circuit 3 is configured as a current mirror differential amplifier having two pairs of input transistors, and includes a PMOS transistor 311 and an N.
Detection unit 3 including MOS transistors 312 to 318
1 and a feedback unit 32 composed of PMOS transistors 321 and 322 and NMOS transistors 3323 and 324. The detection unit 31 includes two pairs of transistors (transistors 313 and 31) for differentially detecting the reference voltage Vref1 and the outputs of the inverters 21 and 22.
4 and 316, 317) are common transistors 311
And 312. Further, the feedback unit 32 receives the output of the detection unit 31
It comprises two PMOS transistors 321 and 322 and two NMOS transistors 323 and 324 to which a predetermined bias voltage Vcn is applied. The connection node between the transistors 321 and 323 is connected to the output of the inverter 21, and the connection node between the transistors 322 and 324 is connected to the output of the inverter 22. Note that the bias voltage Vcn is also applied to the gates of the transistors 315 and 318.

Then, the common mode feedback circuit 3 takes the sum of the voltages at the outputs of the inverters 21 and 22 (corresponding to the common mode voltage) by the detection section 31 and applies feedback so that the common mode voltage is canceled by the feedback section 32. It has become. The common mode feedback circuit 3 further reduces the common mode voltage which has been removed to some extent by the capacitance network unit 1 even in a high frequency region (see region A2 in FIG. 3).

According to the receiver circuit of the first embodiment, since the inverters 21 and 22 can be used to obtain a differential gain, low voltage operation is possible. A large common mode voltage rejection ratio (CMRR) can be obtained with the feedback circuit 3, and high-speed operation can be performed. FIG. 5 is a circuit diagram showing a second embodiment of the receiver circuit according to the present invention,
The capacity network unit 1 uses PRD (Partial Response Det)
ector: partial response detection circuit). In FIG. 5, reference numerals 111, 112, 141,
142, 15, 16 are switches and 171, 17
Reference numerals 2,181 and 182 denote capacitances.

FIG. 6 is a circuit diagram showing an example of a configuration of a capacitance network unit (PRD) in the receiver circuit shown in FIG. 5, and FIG. 7 is an example of a control signal used in the capacitance network unit shown in FIG. It is a timing diagram shown. FIG.
As shown in FIG.
1, 172, 181, and 182, and transfer gates 111, 112, 141, 142, 15, and 16. Transfer gates 111 and 142
Are controlled by a control signal φ2 (/ φ2), and the transfer gates 112, 141, 15 and 16 are controlled by a control signal φ1 (/ φ1). Here, the signals / φ1 and / φ2 are inverted logic signals of the signals φ1 and φ2, respectively. The timing of the control signals φ1 and φ2 with respect to the clock CLK is as shown in FIG.

FIG. 8 is a diagram for explaining the operation of the capacity network unit shown in FIG. The capacitance network unit (PRD) shown in FIG. 6 alternately performs the operations shown in FIGS. 8A and 8B by controlling the control signals φ1 and φ2. That is, when the control signal φ1 is at a high level “H” (/ φ1 is at a low level “L”) and the control signal φ2 is at a low level “L” (/ φ2 is at a high level “H”), FIG.
As shown in FIG. 8A, when the intersymbol interference component estimating operation is performed and the control signal φ1 is at the low level “L” and the control signal φ2 is at the high level “H”, the operation shown in FIG. Signal determination operation is performed so that the Note that the input node of the comparator (2) is precharged during the period in which the intersymbol interference component estimation operation is performed.

In the above, assuming that the values of the capacitors 171 and 182 are C1 and the values of the capacitors 172 and 181 are C2, the values C1 and C2 of these capacitors are expressed by the following equation: C1 /
If it is determined that (C1 + C2) = (1 + exp (-T / τ)) / 2, the intersymbol interference can be theoretically completely estimated. However, in an ideal state, it suffices to satisfy this formula. However, since parasitic capacitance and the like are actually included, the capacitance ratio should be set to a value close to satisfying this formula. Here, t indicates the time constant of the cable (bus), and T indicates the time during which one bit of data appears on the bus or the cycle of one bit.

As described above, by using the PRD as the capacitance network unit as in the second embodiment, it is possible to estimate the intersymbol interference generated in the signal transmission path in addition to the effect of removing the common mode voltage. As a result, it is possible to transmit a high-speed signal even with a cable using a thin core wire. FIG. 9 is a circuit diagram showing a third embodiment of the receiver circuit according to the present invention, and shows an inverter / precharge circuit corresponding to the switches 15 and 16 and the inverters 21 and 22 in the receiver circuit of FIG. is there.

As shown in FIG. 9, in the third embodiment, the inputs and outputs of inverters 21 and 22 provided at each input of the comparator section 2 are connected to transistors 15 and 22, respectively.
0, 160 to apply negative feedback. That is, a single-ended (constant current load) inverter 211 provided at each input of the comparator unit 2,
Transistors 150 (160) each having a gate supplied with a precharge control signal PCS are provided between the input and output of 212 (221, 222). Here, the precharge control signal PCS is, for example,
Control signal φ1 of transfer gate 15 (16) in FIG.
Can be used. Thereby, the pre-charge operation of each input terminal of the comparator unit 2 and the auto-zero operation of the input amplification stages (inverters 21 and 22) can be performed simultaneously, and the comparator unit 2 having a small input offset voltage can be configured. Become.

FIG. 10 shows a fourth embodiment of the receiver circuit according to the present invention.
FIG. 2 is a circuit diagram showing an embodiment, showing one configuration example of the common mode feedback circuit 3. FIG. 11 is a circuit diagram obtained by rewriting the circuit diagram of FIG. FIG.
0, in the fourth embodiment, the common mode feedback circuit 3 is connected to four CMOS inverters 30.
1 to 304. The output of the inverters 21 and 22 in the input amplification stage of the comparator unit 2 is controlled by the inverter 3
01 and 302 are provided to feed back to the output of the inverter 21, and inverters 303 and 304 are provided for the output of the inverters 21 and 22 to provide the inverter 2
2 is fed back. Here, CM
OS inverters 301 to 304 are used as transconductors for converting a voltage to a current,
1 and 302 convert the voltages of the two signal lines (outputs of the inverters 21 and 22) into currents, add the currents, and feed back the current to one signal line (the output of the inverter 21).
The voltages of the two signal lines are converted into currents by the inverters 303 and 304, added, and fed back to the other signal line (the output of the inverter 22).

Here, the circuit shown in FIG. 10 can be rewritten as shown in FIG. 11, and the common mode feedback circuit 3 of the fourth embodiment includes a CMOS inverter 301,
It can also be interpreted as a structure in which a clamp circuit in which the input and output of 304 is short-circuited is provided for each signal line, and a CMOS latch circuit (302, 303) is provided between two signal lines.

In the fourth embodiment, the common mode feedback circuit 3 can be constituted entirely by CMOS inverters.
Since there are no internal nodes connected to other than the input and output lines of FIG. FIG. 12 is a circuit diagram showing a fifth embodiment of the receiver circuit according to the present invention.

As is clear from the comparison between FIG. 11 and FIG. 12, in the fifth embodiment, the single-ended inverters 21 and 22 in the fourth embodiment are configured as CMOS inverters 210 and 220. Similarly to the third embodiment, switches 201 and 202 (corresponding to the NMOS transistors 150 and 160 in FIG. 9) for inputting and outputting to the inverters 210 and 220 are provided to apply negative feedback. .

According to the fifth embodiment, the comparator 2
By including the inverters 21 and 22 (210 and 220) of the input amplifying stages as CMOS inverters, the characteristics of each CMOS inverter are matched, and the design is facilitated. In the fifth embodiment as well, since the input amplification stage of the comparator unit 2 and the common mode feedback circuit 3 can all be constituted by CMOS inverters, the same as in the above-described fourth embodiment,
Low voltage and high speed operation are possible.

FIG. 13 shows a sixth embodiment of the receiver circuit according to the present invention.
It is a circuit diagram showing an example. As is clear from the comparison between FIG. 13 and FIG. 12, in the sixth embodiment, a clamp circuit (351, 352) is provided in the fifth embodiment, and the output amplitude of the comparator 2 fluctuates to the full power supply voltage. Not configured. That is, a clamp circuit composed of NMOS transistors 351 and 352 is provided for the output (differential output terminal) of the comparator unit 2, and the amplitude of the output signal of the comparator unit 2 is diode-connected to the differential output terminal. The transistors 351 and 352 are clamped so as not to exceed the forward voltage.

FIG. 14 shows a seventh embodiment of the receiver circuit according to the present invention.
It is a circuit diagram showing an example. In the seventh embodiment, similarly to the sixth embodiment, the clamp circuits (371, 372;
391, 392) are provided to reduce the output amplitude of the signal. That is, in the seventh embodiment, the inverters 306 and 307 as the next amplification stages are
A clamp circuit 371, 372 and 391, 392 for connecting the input and output of each inverter 306 and 307 is provided. As in the sixth embodiment, for example, a circuit composed of two NMOS transistors 371, 372; 391, 392 is used as the clamp circuit.

As described above, according to the sixth and seventh embodiments of the present invention, the output amplitude of the comparator section 2 is suppressed to a small level (within a predetermined level range) by the clamp circuit, thereby achieving a higher speed operation. Becomes possible. FIG.
FIG. 5 is a diagram showing a circuit example to which the seventh embodiment shown in FIG. 14 is applied. As is clear from the comparison between FIG. 14 and FIG.
In the circuit example shown in FIG.
Is constituted by a transfer gate, and the switching of the transfer gates 201 and 202 is controlled by the switching control signal LAT (and the inverter 200). The inverters 301 and 30
2, 303 and 304 are each configured as a CMOS inverter, and a clamp circuit connecting the input and output of the inverters 306 and 307 is configured of two NMOS transistors 371, 372 and 391 and 392, respectively.

FIG. 16 is a diagram showing an example of a circuit subsequent to the circuit (comparator circuit 2) shown in FIG. As shown in FIG. 16, a PMOS
Through a differential amplifier circuit composed of transistors 401 to 404 and NMOS transistors 405 to 409,
A latch circuit including NAND gates 410 and 411 is provided. Here, the output (differential output) of the comparator unit 2 at the preceding stage is supplied to the gates of the transistors 407 and 408, respectively. The gates of the transistors 401, 404 and 409 are supplied with a latch control signal SL for latching at a high level "H". Note that the latch control signal SL has a low level “L”.
In the case of, reset is performed. In addition, the latch circuit (NA
The output of the ND gates 410 and 411) is the inverter 4
12 is output.

FIG. 17 shows an eighth embodiment of the receiver circuit according to the present invention.
FIG. 18 is a circuit diagram showing an embodiment, and FIG.
FIG. 4 is a timing chart illustrating an example of a control signal used in the embodiment. As shown in FIG. 17, in the eighth embodiment, for example, in the fifth embodiment shown in FIG.
Inverters 361 and 381 whose connection is controlled by 2, 363, 382, and 383 are provided on each signal line, and the differential gain of the common mode feedback circuit 3 is changed. Here, the switch 201
And 202 are turned on when the control signal S1 (corresponding to the precharge control signal PCS in FIG. 9) is at a high level "H" to connect (precharge) the inputs and outputs of the inverters 210 and 220, and to switch 362,3
63, 382, and 383 are turned on when the control signal S2 is at a high level "H", and connect the inverters 361 and 362 to each signal line.

As shown in FIG. 18, the control signal S2
Is a signal detection period (measurement period) after a precharge period (reset period) in which the control signal S1 becomes high level “H”.
To a high level "H" for a predetermined time to increase the differential gain of the common mode feedback circuit 3, and
The control signal S2 becomes low level "L" immediately before the control signal S1 becomes high level "H" again, and operates the common mode feedback circuit 3 as a latch circuit to latch the signal. This eliminates the need for a latch section (differential amplifier circuit, latch circuit, and the like) provided at a stage subsequent to the comparator section 2 described above, thereby simplifying the circuit and achieving higher speed.

As described above, according to the eighth embodiment, since an amplifier having a small input offset voltage is operated as a latch, high-accuracy and high-speed signal detection is possible. In the above, the receiver circuit according to each embodiment of the present invention performs signal transmission such that the differential signal from the differential driver circuit (101) is supplied via a cable (102) for transmission. Can be applied to the system. Further, the receiver circuit is used not only for signal transmission between a housing and a board such as a server and a server via a main storage device or a network, but also for signal transmission between chips and signal transmission between elements and circuit blocks in a chip. Can also be applied.

[0043]

As described above in detail, according to the present invention, it is possible to provide a receiver circuit and a signal transmission system capable of transmitting a signal with high accuracy and high speed.

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating an example of a conventional signal transmission system.

FIG. 2 is a diagram showing a principle configuration of a receiver circuit according to the present invention.

FIG. 3 is a diagram for explaining removal of a common mode voltage by the receiver circuit shown in FIG. 2;

FIG. 4 is a circuit diagram showing a first embodiment of the receiver circuit according to the present invention.

FIG. 5 is a circuit diagram showing a second embodiment of the receiver circuit according to the present invention.

FIG. 6 is a circuit diagram showing one configuration example of a capacitance network unit in the receiver circuit shown in FIG. 5;

FIG. 7 is a timing chart showing an example of a control signal used in the capacity network unit shown in FIG. 6;

FIG. 8 is a diagram for explaining an operation of the capacity network unit shown in FIG. 6;

FIG. 9 is a circuit diagram showing a third embodiment of the receiver circuit according to the present invention.

FIG. 10 is a circuit diagram showing a fourth embodiment of the receiver circuit according to the present invention.

11 is a circuit diagram obtained by rewriting the circuit diagram of FIG.

FIG. 12 is a circuit diagram showing a fifth embodiment of the receiver circuit according to the present invention.

FIG. 13 is a circuit diagram showing a sixth embodiment of the receiver circuit according to the present invention.

FIG. 14 is a circuit diagram showing a seventh embodiment of the receiver circuit according to the present invention.

FIG. 15 is a diagram showing an example of a circuit to which the seventh embodiment shown in FIG. 14 is applied.

16 is a diagram illustrating a circuit example at a subsequent stage of the circuit illustrated in FIG. 15;

FIG. 17 is a circuit diagram showing an eighth embodiment of the receiver circuit according to the present invention.

FIG. 18 is a timing chart showing an example of a control signal used in the eighth embodiment shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Capacitance network part 2 ... Comparator part 21, 22 ... Inverter 3 ... Common mode feedback circuit 101 ... Differential driver 102 ... Cable 103 ... Receiver circuit 104 ... Terminal resistance

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Makoto Zhang 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term within Fujitsu Limited (reference) 5J056 AA01 AA05 BB02 CC02 CC09 CC12 CC14 CC19 DD29 DD51 EE07 FF08 GG06 KK01 5K029 AA11 DD02 GG07 HH01 LL06

Claims (15)

[Claims] 1. A receiver circuit comprising: a capacitance network unit that receives a differential input signal; and a comparator unit that receives an output of the capacitance network unit, wherein the capacitance network unit includes a capacitance unit that accumulates electric charges;
And a switch unit for controlling the supply of the input signal to the capacitance unit. The comparator unit amplifies an output of the capacitance network unit, and receives the output of the inverter and keeps the common mode voltage substantially constant. A receiver circuit comprising a common mode feedback circuit for maintaining the value of the common mode feedback circuit. 2. The receiver circuit according to claim 1, wherein the capacitance network unit reduces a common mode voltage in a low frequency region of the differential input signal, and the comparator unit operates the differential input signal. A receiver circuit for reducing a common mode voltage in a high frequency region of an input signal. 3. The receiver circuit according to claim 1, wherein said capacitance network unit constitutes a partial response detection circuit. 4. The receiver circuit according to claim 1, wherein said receiver circuit further comprises a precharge means provided at an input of said comparator section. 5. The receiver circuit according to claim 4, wherein said precharge means performs a precharge by applying a predetermined power supply voltage to an input of said comparator section. Receiver circuit. 6. The receiver circuit according to claim 4, wherein said precharge means performs precharge by feeding back an output of an inverter provided at an input of said comparator section to an input. Characteristic receiver circuit. 7. The receiver circuit according to claim 1, wherein the inverter provided in the comparator section is a constant current load inverter. 8. The receiver circuit according to claim 1, wherein the inverter provided in the comparator section comprises a C
A receiver circuit, which is a MOS inverter. 9. The receiver circuit according to claim 1, wherein the common mode feedback circuit includes a detection unit including a differential amplifier having two pairs of input transistors, and a feedback unit connected in a current mirror. A receiver circuit. 10. The receiver circuit according to claim 1, wherein said common mode feedback circuit detects a common mode voltage by coupling outputs of two CMOS inverters for amplifying each of a pair of signal lines to each other. A receiver circuit comprising: 11. The receiver circuit according to claim 1, wherein all the amplification stages used in the comparator section are CMs.
A receiver circuit comprising an OS inverter. 12. The receiver circuit according to claim 1, wherein said comparator unit further comprises a clamp circuit for suppressing an amplitude of an output signal of said comparator unit to a predetermined level range or less. Receiver circuit. 13. The receiver circuit according to claim 12, wherein said predetermined level range is a range of a power supply voltage. 14. The receiver circuit according to claim 1, wherein the comparator unit includes a unit that changes an amplification degree of the common mode feedback circuit with respect to a differential mode, and amplifies a signal supplied from the capacitance network unit. A receiver circuit, wherein the amplification degree in a differential mode is increased later to operate as a latch circuit. 15. A differential driver circuit, a cable connected to the differential driver circuit for transmitting a differential signal from the differential driver circuit, and a receiver circuit connected to the cable and detecting the differential signal. A signal transmission system comprising: the receiver circuit according to claim 1, wherein the receiver circuit is the receiver circuit according to claim 1.