JP2000196468A - Viterbi decoder and biterbi decoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration in processing performance due to the number of times of memory accesses to a path memory in the case of trace-back processing and to reduce a capacity of the path memory. SOLUTION: An ACS processing section 13 estimates a most probable path in each state at a present time on the basis of a path metric calculated by branch metric processing for each unit time and a path metric up to a preceding time stored in either of a couple of path metric buffers 18a, 18b, rearranges maximum likelihood decoding information up to the preceding time stored either of a couple of data buffers 17a, 17b on the basis of the estimated path and writes the rearranged information to the other, updates the path metric stored in either of a couple of the path metric buffers 18a, 18b and writes the updated path metric to the other. A trace back processing section 14 retrieves decoded data on the basis of the path metric stored up to a present time stored in the path metric buffers 18a, 18b and the maximum likelihood decoding information up to the present time stored in the data buffers 17a, 17b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoding device and a Viterbi decoding method using a trace-back method, and more particularly to a Viterbi decoding device capable of shortening a trace-back time and speeding up Viterbi decoding. And a Viterbi decoding method.

[0002]

2. Description of the Related Art In a communication field, an error correction technique is one of very important techniques. As an example of error correction technology, Viterbi decoding is known as a general algorithm of the maximum likelihood decoding method for convolutional codes, and as a decoding method in a transmission method having a communication path in which a transmission error easily occurs due to its high error correction capability. A Viterbi decoding device including a dedicated LSI and a digital signal processor (DSP) is often used. In recent years, the performance and functionality of microprocessors have been remarkably improved, and Viterbi decoding processing, which was conventionally performed by hardware such as a dedicated LSI, is to be realized by software (high-performance microprocessor + software). Is becoming possible.

Here, a problem is processing performance.
Compared to the conventional dedicated LSI, which is processed by the dedicated LSI alone (single task) by the command from the CPU, the software processing by the microprocessor is often used in a multitask environment by OS execution etc. To reduce microprocessor resources by one.
It is difficult to occupy 00%, and a higher speed than conventional processing performance is required.

A conventional Viterbi decoding device and a conventional Viterbi decoding method will be described with reference to the drawings. 9 is a block diagram showing a convolutional coding device, FIG. 10 is an explanatory diagram showing states of the device in FIG. 9, FIG. 11 is an explanatory diagram showing state transitions of the device in FIG. 9, and FIG. 12 is a trellis of the device in FIG. FIG. 13 is an explanatory diagram showing an example of state transition of the device in FIG. 9, FIG. 14 is a block diagram showing a conventional Viterbi decoding device, and FIG. 15 shows the path memory in FIG. 14 in detail. 16 is a block diagram, FIG. 16 is an explanatory diagram showing a state transition showing a decoding operation by the traceback method, FIG. 3 is a flowchart showing a branch metric process, and FIG. 17 is an ACS (Add Compare Se
FIG. 18 is a flowchart showing a traceback process.

[0005] First, an algorithm of convolutional (trellis) coding which forms a pair with Viterbi decoding will be described.
FIG. 9 shows a constraint length of 3 and a coding rate of 1 for simplicity of explanation.
2 shows an encoding device that performs convolutional encoding of / 2.
The convolutional encoding device 81 includes a 3-bit shift register R
1 (the bits are set to "1", "2", "3" in order from the input in) and two exclusive OR circuits C1 and C2. The exclusive OR circuit C1 calculates the exclusive OR of all the bits “1”, “2”, and “3” of the 3-bit shift register R1, outputs the result as an output signal out1, and outputs the exclusive OR circuit C2. Calculates the exclusive OR of bit "1" and bit "3" of the 3-bit shift register R1 and outputs the result as an output signal out2.

Here, the value of the information bit stored in bit "1" of the 3-bit shift register R1 is a, and the value of the information bit stored in bit "2" is b.
Assuming that 1-bit information is newly input to the bit shift register R1, the values of the bits stored in the 3-bit shift register R1 are, in order from bit “1”, the input 1-bit information, information bits a, b, the convolutional encoder 8 when one bit of information is input
The number of states X of 1 is a combination of (a, b) (X = 0,
1, 2, 3). In this case, as shown in FIG. 10, there are four states of s0 = (0,0) s1 = (0,1) s2 = (1,0) s3 = (1,1)

In general, the number of states X when the constraint length is n
Can be represented by 2 ＾ (n−1) (＾ indicates a power). FIG. 11 shows the current state and the input information bits (i
n), the output (out2, out1), and the transition state. For example, state s0 (a = b
(= 0), when "0" is input as an input information bit, (out2, out1) = (0, 0) is output, and the state transits to the state s0 (the state does not change).

Similarly, in the state s0 (a = b = 0),
When "1" is input as an input information bit, (out
(2, out1) = (1, 1) is output, and it can be seen that the state transits to the state s1. That is, the convolutional encoder 8
In the convolutional coding of 1, two code bits (coding rate 1/2) are output for one input information bit. The convolutional coding algorithm performs coding by repeating the above operation on the input information bits at time tn (n = 1, 2, 3,...).

FIG. 12 is a diagram (called a trellis diagram) showing a state transition when convolutional encoding is performed by the convolutional encoding device 81. "0" as input information bit
Is indicated by a solid line, and a case where 1 is input as an input information bit is indicated by a dotted line. The data encoded in this way has excellent random error correction capability. For example, the most probable path (most likely path) is determined by Viterbi decoding, and converted to decoded data to obtain highly reliable data. Data can be obtained.

Next, an algorithm in the case where the data encoded by the convolutional encoding device 81 is subjected to Viterbi decoding (traceback method) by the Viterbi decoding device 131 will be described. Here, the initial state of the convolutional encoder 81 is set to state s0 (a = b = 0), and (1,1,0,
Assuming that information bits are input in the order of (0, 0, 1, 1), the convolutional encoder 81 transits to the state shown by the solid line in FIG. 13 and performs encoding. Specifically, when the first information bit = 1 is input, the convolutional encoding device 81
Encoding is performed to output 2-bit encoded data (1, 1). By repeating the above processing for each input information bit, encoded data (11, 10, 10, 11, 00, 11, 10) is obtained.

Next, an error occurs in the first bit (fifth bit) of the third encoded data with respect to this encoded data, and (11, 10, 00, 11, 00, 11, 10) The description of Viterbi decoding will be made on the assumption that the data of (1) is transmitted to the Viterbi decoding device 131 shown in FIG. Viterbi decoding processing includes branch metric processing, ACS
(Addition → comparison → selection) processing and traceback processing. Processing such as those shown in the flowcharts of FIG. 3 (branch metric processing), FIG. 17 (ACS processing), and FIG. Do.

(1) Branch metric processing When a received signal is input to the branch metric processing unit 12, the branch metric processing unit 12 executes step S3 shown in FIG.
In steps 1 to S38, branch metrics are calculated for all paths that can transition from time t [n-1] to one unit time at time tn, and output to the ACS processing unit 133.
Specifically, at time t1, the encoded data (1, 1)
Is received, the state s0 at time t1 (variable X =
The path at the previous time t0 that can transition to 0) is state s0, state s
2 are clear from the trellis diagram of FIG.

Here, when the state transits from the state s0 at the time t0, the output = (0, 0), and at that time, the input = 0. Similarly, when the state transits from the state s2 at time t0,
It can be easily estimated that output = (1,1) and input = 0 at that time (step S33 in FIG. 3). These outputs (00, 11) and the received encoded data =
A branch metric is obtained from (1, 1) (step S34 in FIG. 3). In the branch metric calculation, the output (00, 11) and the received encoded data = (1, 1)
A Hamming distance (branch metric) indicating the sum of the differences for each bit is obtained.

When the state transits from the state s0 at the time t0, the first bit and the second bit do not match, so that the Hamming distance = 2. Similarly, when the state transits from the state s2 at the time t0, the first bit and the second bit match, so that the Hamming distance = 0. The above processing is performed for all the other three states (variable X = 1, 2, 3 in FIG. 3) (steps S37 and S38 in FIG. 3).

(2) ACS (addition → comparison → selection) processing
When the branch metric calculated by the branch metric process is input to the ACS processing unit 133, the ACS processing unit 133 performs steps S71 to S78 shown in FIG. 17 based on the relationship between the branch metric and the path estimated before. , The most probable path is estimated for each state. More specifically, the path metric (cumulative Hamming distance) up to the state s0 at the time t0 and the state s2 up to that state at which the state can transit to the state s0 at the time t1 (variable X = 0)
And the branch metric (Hamming distance) calculated by the branch metric processing unit 12, and the path metric up to time t1 is calculated. In this case, since the time t0 is the initial state, when the calculation is performed with the accumulated Hamming distance = 0, in the above input example, when the state transits from the state s0 at the time t0, the path metric = 2 (= 0 + 2) and the state s2 at the time t0 In the case of transition, the path metric = 0 (= 0 +
0) (step S73 in FIG. 17).

Next, the path metrics for each path are compared, and it is estimated that the state has transited from the state with the smaller path metric (if the path metric is the same, it is estimated from the state with the smaller state number). Then, the input at that time is set as a decoded data candidate, and a pointer to the path memory, a path metric to the path memory, and a decoded data candidate are written in the area of the state s0 at the time t1 in the path memory 135.

In this case, in the above input example, when the state transits from the state s0 at the time t0, the path metric = 2, and when the state transits from the state s2 at the time t0, the path metric = 2.
Since it is 0, it is estimated that the state has transitioned from the state s2 at the time t0 to the state s0 at the time t1, and the pointer to the area of the state s2 at the time t1 in the path memory 135. -Path metric value = 0-Decoded data candidate = 0 is written (Fig. 17)
Step S76). The above processing is performed for all the other three states (variable X = 1, 2, 3 in FIG. 17) (FIG. 17).
Steps S73 and S74).

(3) Traceback processing When a series of processings of branch metric processing and ACS processing are performed on the encoded data received at each time, and inference has been completed for all received signals (encoded data) State transition is as shown in FIG. Traceback processing unit 13
In step S4, in steps S81 to S87 shown in FIG. 18, at the last time t, the past is traced back from the state sX (tn) with the smallest path metric to obtain a decoded data candidate.

More specifically, the path metrics of all the states at the last time tn (n = 7) are read, and the state s3 having the smallest path metric is selected. Next, when iteratively reads the pointer to the path memory of the path estimated from the state and goes back to the past (step S85 in FIG. 18), the state transitioned to the state indicated by the solid line in FIG. Can be estimated. This state transition is the same as the state transition of FIG. 13, and the decoded data candidate of this state transition (FIG. 16)
When the (boxes with half-tone dots in the middle) are sequentially extracted from the past, they become (1,1,0,0,0,1,1), which indicates that they match the data before being encoded. As described above, in the Viterbi decoding, it is possible to correct an error included in the transmitted encoded data and decode the data to correct data.

In the above description of the conventional example, when the encoded data string is short (11, 10, 00, 11, 0)
(14 bits of 0, 11, and 10), but since general encoded data is quite long, the capacity of the path memory 135 and the time of traceback processing become enormous when strictly performing Viterbi decoding. Would. For this reason, in an actual Viterbi decoding device, the path memory 135 has an arbitrary length, stores the latest path corresponding to the length of the path memory 135 from the current time, and traces the path when writing a new path. After performing the back process and outputting the decoded data candidate of the oldest pass, the oldest pass is discarded.
Generally, the length of the path memory 135 (traceback length)
It is known that by setting the constraint length to 5 to 6 times the constraint length of the encoding device, the error of the truncation can be almost ignored.

Another conventional example is disclosed in, for example, JP-A-5-5
As shown in JP-A-5931, the path metric value is represented by a small number of bits in order to reduce the circuit scale.
In order to increase the speed, a method has been proposed in which the normalization processing is performed not every time but at a cycle that does not cause the path metric to overflow. As another conventional example, a method of combining a plurality of Viterbi decoders has been proposed as disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 6-77845 to improve transmission efficiency. In addition, Japanese Patent Application Laid-Open No. H6-197027 proposes a method for improving an error rate. Japanese Patent Application Laid-Open No. 8-167858 discloses A
There has been proposed a configuration in which a path memory is operated by n buffers and distributors after CS processing. Further, Japanese Patent Application Laid-Open No. 9-51
No. 278 discloses that 1 / n is used instead of one path memory.
Has been proposed to operate independently using n buffers of the size of.

[0022]

A first problem with the conventional Viterbi decoding method using the traceback method is that the number of memory accesses to the path memory 135 in one decoding process increases, and the processing performance decreases. It is to be. The reason is, for example, assuming that the traceback length = 16 (a general value used in actual Viterbi decoding), in the traceback processing, the reading of the path metric values of all the states of the arrival time and the previous one Since the “reading of the pointer to the path memory of the estimated path” occurs for the traceback length, the memory access to the path memory 135 occurs 4 + 16 = 20 times. This number increases as the constraint length of the encoding device increases. In recent years, the operating speed of a microprocessor has been increased, but the access time of a memory used in an actual system is slow (a trade-off with cost). Therefore, an increase in the number of memory accesses directly lowers the processing performance. Cause it.

The second problem is that the memory (path memory 13)
5) An increase in capacity. The reason is that the path memory 135
Is dependent on the traceback length.
Under the above conditions (traceback length = 16, number of states = 4), the capacity of the path memory 135 is 3 × 4 × 16 = 192 (words). Although this value does not cause any problem when a general memory is assumed, it causes a serious problem in a memory (such as a cache memory) built in a microprocessor (a decrease in processing performance due to an increase in cache misses). ).

[0024]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and can prevent a decrease in processing performance due to the number of memory accesses to a path memory during traceback processing. It is an object of the present invention to provide a Viterbi decoding device, a Viterbi decoding method, and a computer program recording medium that can be reduced.

[0025]

In order to achieve the above object, a Viterbi decoding apparatus according to the present invention calculates a branch metric for all paths that can transition in one unit time from the previous time to the current time. Metric processing means, a pair of data buffers for storing the maximum likelihood decoding information up to the previous time and the maximum likelihood decoding information up to the current time, and a path metric up to the previous time and a path metric up to the current time, respectively. A pair of path metric buffers for storage, and a branch metric calculated by the branch metric processing means and a path metric up to a previous time stored in one of the pair of path metric buffers for each unit time. The most probable path in each state at the current time is estimated based on this path, and based on this path, the pair of data It rearranges maximum likelihood decoding information up to the time before stored in one of Ffa writes to the other, ACS writing to the other to update the path metrics stored in one of the path metrics buffer of said pair
Processing means; and traceback processing means for searching for decoded data based on the path metric up to the current time stored in the path metric buffer and the maximum likelihood decoding information up to the current time stored in the data buffer. It is characterized by.

With the above configuration, for each unit of the ACS processing,
The maximum likelihood decoding information stored in the data buffer and the path metric stored in the path metric buffer are updated. Therefore, in the traceback processing, decoding can be performed only by accessing the maximum likelihood decoding information up to the current time based on the path metric up to the current time.

The data buffer stores a maximum likelihood decoded data candidate and a maximum likelihood state transition history for each pass as maximum likelihood decoding information.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a Viterbi decoding device according to the present invention, and FIG. 2 is a configuration diagram showing a data buffer and a path metric buffer of FIG.

1, the Viterbi decoder 11 according to the present invention comprises a pair of identically configured data buffers 17a for storing decoded data candidates, as shown in FIG.
17b and a pair of identically configured path metric buffers 18a and 18b for storing path metrics. One of the data buffers 17a and 17b stores decoded data candidates up to the previous time, and the other stores decoded data candidates at the current time. In this case, ACS (Add Compare
Selection) processing, the data buffers 17a, 1
At the time of updating the data buffer 7b, the line storing the estimated previous state information is read from one of the data buffers 17a and 17b storing the decoded data candidates up to the previous time, and the other current buffer of the data buffers 17a and 17b is read. The estimated decoded data candidate is added to the state line and written.

By performing the above processing for each state at each time, each line of the data buffers 17a and 17b becomes a decoded data candidate sequence of the maximum likelihood path in each state. Instead of going back, it is possible to go back directly to an arbitrary time, thereby shortening the traceback processing time.

More specifically, the Viterbi decoding device 11
Comprises a path memory 15, a branch metric processing unit 12 for calculating branch metrics for all paths transitable in one unit time from the previous time to the current time, and outputting the calculated branch metrics to the ACS processing unit 13, Based on the branch metric calculated by the processing unit 12 and the path metrics stored in the path metric buffers 18a and 18b up to the time before the time selected by the selector 16 in the path memory 15, the most accurate value in each state at the current time is obtained. An ACS processing unit 13 for estimating a likely path and rearranging decoded data candidates, and a selector 16 in the path memory 15.
Path metric buffer 18 at the current time selected by
The traceback processing unit 14 searches for decoded data to be output based on the path metrics stored in the data buffers 17a and 18b and the decoded data candidates stored in the data buffers 17a and 17b at the current time.

As shown in FIG. 2, the path memory 15 includes a pair of identically configured data buffers 17a and 17b for storing decoded data candidates equal to the number of states × the traceback length.
A pair of identically configured path metric buffers 18a, 18b for storing path metrics for the number of states, and buffers (17a, 17b), (18a, 18b) for each unit time
And a selector 16 for performing the switching.

FIG. 3 is a flowchart showing the branch metric processing of the present invention, and FIGS. 4 and 5 are the ACS of the present invention.
FIG. 6 is a flowchart showing the processing, and FIG.
FIGS. 7A and 7B are explanatory diagrams showing operations of the data buffers 17a and 17b, FIG. 7 is an explanatory diagram showing transitions of the data buffers 17a and 17b and the path metric buffer 18, and FIG.

In the description, the flow of time is set to t1, t2,... Tn for each unit time, and t [n-1] is set for one unit time before each time (one unit of time t3). The time before is time t2). The a-side buffer groups 17a and 18a switched by the selector 16 are at time t1,
The read operation is performed at t3..., and the write operation is performed at times t2, t4.
b is a write operation at times t1, t3,.
At time t4, the read operation is performed, and the encoded data to be Viterbi-decoded (data before encoding is 1,
1, 0, 0, 0, 1, 1) are the same data (11, 10, 00, 11, 00, 11, 1, 1) as described in the conventional example.
0).

(1) Branch metric processing The branch metric processing unit 1 of the Viterbi decoder 11
2, the branch metric processing unit 12
At steps S31 to S38 shown in FIG.
-1], branch metrics are calculated for all paths that can transition to one unit time at time tn, and output to the ACS processing unit 13. Specifically, when coded data = (1, 1) is received at time t1, the state s0 at time t1 is received.
It is clear from the trellis diagram shown in FIG. 12 that there are two paths at state t0 and state s2 at the previous time t0 at which the state can transition to. Here, when the state transits from the state s0 at the time t0, the output is (0, 0), and the input at that time is 0. Similarly, when the state transits from the state s2 at the time t0, it can be easily estimated that the output = (1, 1) and the input = 0 at that time (step S33 in FIG. 3).

A branch metric is determined from these outputs (00, 11) and the received encoded data = (1, 1) (step 34 in FIG. 3). In the branch metric calculation, the output (00, 11) and the received encoded data =
A Hamming distance indicating the sum of the difference of each bit of (1, 1) is obtained. When the state transits from the state s0 at time t0, the first
Hamming distance =
It becomes 2. Similarly, when the state transits from the state s2 at the time t0, the first bit and the second bit match, so that the Hamming distance = 0. The above processing is performed for the other three (variable X in FIG. 3).
= 1, 2, 3) (steps S37 and S38 in FIG. 3).

(2) ACS Processing The branch metric calculated in the branch metric processing is input to the ACS processing unit 13, and the ACS processing unit 13 performs steps S41 to S61 shown in FIG. The most probable path is estimated for each state based on the relationship between the branch metric and the path previously estimated. Specifically, the path metric (cumulative Hamming distance) up to that in state s0 and state s2 at time t0, which can transit to state s0 at time t1, and the branch metric (hamming distance) calculated by branch metric processing unit 12 are calculated. Then, a path metric up to time t1 is calculated.

In this case, at the time of the path metric at time t0, the selector 16 selects the path metric buffer 18a on the a side. At this time, since the path metric buffer 18a is in the initial state and is calculated with path metric = 0, if the state transits from the state s0 at the time t0, the path metric = 2 (= 0 + 2) and the state s at the time t0
When the transition is made from 2, the path metric = 0 (= 0 + 0)
(Step S44 in FIG. 4).

Next, the path metrics for each path are compared, and it is estimated that the state has transited from the state with the smaller path metric (if the path metric is the same, it is estimated from the state with the smaller state number). The path metric at that time is stored in the path metric buffer 1 on the b side.
8b (step S47 in FIG. 5). in this case,
In the above input example, the path metric when transitioning from the state s0 at time t0 = 2, and the path metric when transitioning from the state s2 at time t0 = 0, so that the state s2 at time t0 changes from the state s2 to the state s0 at time t1. Presumed to have transitioned, b
The path metric value = 0 is written to the state s0 of the side path metric buffer 18b.

Next, from the data buffer 17a on the a side,
The decoded data candidate sequence in the estimated state s2 is read (step S48 in FIG. 5), and the estimated bus (s2 → s
0) is added to the decoded data candidate = 0, and b
(Step S49 in FIG. 5, time t in FIG. 6)
1). The above processing is repeated for the other three (variable X = 1, 2, 2,
This is performed for all the states of 3) (Step S50 in FIG. 5,
S51).

At the next time t2, the encoded data =
When (1, 0) is received, after the branch metric processing, the state s at time t1 that can transition to the state s0 at time t2
0, the path metric up to that time in the state s2 and the branch metric calculated by the branch metric processing unit 12 are added to calculate the path metric until time t2. In this case, the path metric at time t1 is the selector 1
6, the path metric buffer 18b on the b side is selected. At this time, since the path metric of the state s0 of the path metric buffer 18b is 0, if the state transits from the state s0 of the time t1, the path metric is 1 (= 0 +
1) When the state transits from the state s2 at the time t1, the path metric becomes 2 (= 1 + 1).

Next, the path metrics for each path are compared, it is estimated that the state has transited from the state with the smaller path metric, and the path metric at that time is written to the path metric buffer 18a on the a side. In this case, in the above input example, the path metric when the state transits from the state s0 at the time t1 = 1, and the path metric when the state transits from the state s2 at the time t1 = 2. It is estimated that the state has transited to the state s0, and the state s0 of the path metric buffer 18a on the a side is
Is written with the path metric value = 1.

Next, from the data buffer 17b on the b side,
Read the decoded data candidate sequence in the estimated state s0,
A decoded data candidate = 0 determined by the estimated bus (s0 → s0) is added and written to the decoded data candidate series in the state s0 of the a-side data buffer 17a (time t2 in FIG. 6). The above processing is performed for the other three (variable X = 1,
This is performed for all of the states 2) and 3).

By repeating the above operation,
One line of the data buffer 17 at the current time tn selected by the selector 16 becomes a decoded data candidate sequence of the maximum likelihood path in each state. That is, the oldest data in the one-line decoded data candidate sequence is the decoded data at the current time tn.

Here, (11, 1)
FIG. 7 shows transitions of the data buffer 17 and the path metric buffer 18 in the decoding operation when (0, 00, 11, 00, 11, 10) are input. Referring to FIG. 7, looking at the path metric buffer 18b on the b side at the final time t7, the path metric in the state s3 has the minimum value =
1, the decoded data candidate sequences stored in one line of the state s3 of the b-side data buffer 17b are sequentially arranged from the oldest time t1 as (1,1,
0, 0, 0, 1, 1), which indicates that they match the data before being encoded (decoded to correct data).

(3) Trace-back processing In the trace-back processing section 14, each line of the data buffer 17 becomes a maximum likelihood decoded data sequence in each state by the ACS processing. In steps S61 to S64 shown in FIG. 8, it is possible to directly go back to the past by the traceback length.

Therefore, the first effect is that the time for the trace-back processing can be reduced. The reason is that the oldest decoded data candidate can be directly searched in the traceback processing, so that it is not necessary to access the memory to go back to the past one time at a time. Specifically, for example, if the traceback length is 16, the memory access is required 4 + 16 = 20 times in the past, but according to the present invention, the traceback processing is performed by 4 + 1 = 5 memory accesses. It can be performed.

Here, the Viterbi decoding (traceback length = 16) processing is actually performed by a microprocessor (NEC μm).
Comparing the performance data when programming using the PD 705100 (V830), processing that took 90 μs (periodic processing unit: 416 μs) in the conventional method is reduced to 45 μs by the Viterbi decoding method of the present invention. I was able to. In addition, according to the present invention, since the traceback processing can be performed without depending on the traceback length, it is clear that the longer the traceback length, the higher the effect.

The second effect is that the path memory capacity can be reduced. The reason is that by configuring the path memory with a pair of buffer groups, unnecessary path metric memory can be reduced. Specifically, for example,
Assuming traceback length = 16 and number of states = 4,
Whereas 3 × 4 × 16 = 192 (word) path memories were required, according to the present invention, (4 + 4 × 16) ×
Viterbi decoding can be performed with a memory capacity of 2 = 136 (words). Therefore, in a microprocessor having a built-in cache memory, the cache hit rate is improved, and the processing time can be further reduced.

In the above embodiment, the decoded data candidates are stored in the data memory. Alternatively, the maximum likelihood state transition history may be stored.

[0051]

As described above, according to the present invention, A
Since the maximum likelihood decoding information stored in the data buffer and the path metric stored in the path metric buffer are updated for each CS processing unit, the processing performance decreases due to the number of memory accesses to the path memory during the traceback processing. Can be prevented, and the capacity of the path memory can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a Viterbi decoding device according to the present invention.

FIG. 2 is a configuration diagram showing a data buffer and a path metric buffer of FIG. 1;

FIG. 3 is a flowchart showing a branch metric process of the present invention.

FIG. 4 is a flowchart showing an ACS process of the present invention.

FIG. 5 is a flowchart showing an ACS process of the present invention.

FIG. 6 is an explanatory diagram showing an operation of the data buffer of FIG. 1;

FIG. 7 is an explanatory diagram showing transition between the data buffer and the path metric buffer in FIG. 1;

FIG. 8 is a flowchart illustrating a traceback process according to the present invention.

FIG. 9 is a block diagram illustrating a convolutional encoding device.

FIG. 10 is an explanatory diagram showing a state of the device in FIG. 9;

FIG. 11 is an explanatory diagram showing a state transition of the device in FIG. 9;

FIG. 12 is an explanatory diagram showing a trellis diagram of the apparatus shown in FIG. 9;

13 is an explanatory diagram illustrating an example of a state transition of the device in FIG. 9;

FIG. 14 is a block diagram showing a conventional Viterbi decoding device.

FIG. 15 is a block diagram showing the path memory of FIG. 14 in detail;

FIG. 16 is an explanatory diagram showing a state transition in a decoding operation by the traceback method.

FIG. 17 is a flowchart showing a conventional ACS process.

FIG. 18 is a flowchart showing a conventional trace-back process.

[Explanation of symbols]

 12 branch metric processing unit 13 ACS processing unit 14 traceback processing unit 15 path memory 16 selector 17a, 17b data buffer 18a, 18b path metric buffer

Claims (6)

[Claims] 1. A branch metric processing means for calculating branch metrics for all paths transitable in one unit time from a previous time to a current time, maximum likelihood decoding information up to the previous time and maximum likelihood decoding up to the current time A pair of data buffers for respectively storing information, a pair of path metric buffers for respectively storing a path metric up to the previous time and a path metric up to the current time, and the branch metric for each unit time The most probable path in each state at the current time is estimated based on the branch metric calculated by the processing means and the path metric up to the previous time stored in one of the pair of path metric buffers. The maximum likelihood decoding information stored up to the previous time stored in one of the pair of data buffers is rearranged based on the ACS processing means for writing, updating the path metric stored in one of the pair of path metric buffers and writing the updated path metric in the other, and storing the path metric up to the current time stored in the path metric buffer and the data buffer Traceback processing means for searching for decoded data based on the maximum likelihood decoding information up to the current time. 2. The Viterbi decoding apparatus according to claim 1, wherein the data buffer stores a maximum likelihood decoded data candidate for each path as maximum likelihood decoding information. 3. The Viterbi decoding device according to claim 1, wherein the data buffer stores a maximum likelihood state transition history of each path as maximum likelihood decoding information. 4. A branch metric processing step for calculating a branch metric for all paths transitable in one unit time from a previous time to a current time; and a branch calculated by the branch metric processing step for each unit time. The most probable path in each state at the current time is estimated based on the metric and the path metric up to the previous time stored in one of the pair of path metric buffers. An ACS processing step of rearranging the maximum likelihood decoding information stored up to the previous time stored in one of the paired path metric buffers and updating the path metric stored in one of the pair of path metric buffers and writing the same in the other; Path metrics up to the current time stored in a metric buffer and the data buffer Viterbi decoding method with a trace back processing step of retrieving the decoded data based on the maximum likelihood decoding information to the stored current time was. 5. The Viterbi decoding method according to claim 4, wherein the data buffer stores maximum likelihood decoded data candidates of each path as maximum likelihood decoding information. 6. The Viterbi decoding method according to claim 4, wherein the data buffer stores a maximum likelihood state transition history of each path as maximum likelihood decoding information.